flat_atomic_cmpswap_f32 GPU Native ISA AMD Vector

Flat Memory

flat_atomic_cmpswap_f32

Compare two single-precision float values stored in the data comparison register and a location in the flat aperture.

Also written as flat_atomic_fcmpswap. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (FLAT) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format FLAT

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 32-bit single-precision floating point value. (OPR_VGPR, FMT_NUM_F32)
  • ADDR
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Value can be anything. (OPR_VGPR, FMT_ANY)
  • DATA
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Value can be anything. (OPR_VGPR, FMT_ANY)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_FLAT encoding (AMD RDNA 3.5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Flat Memory

Reference

AMDGPU / GFX ISA

Description

Compare two single-precision float values stored in the data comparison register and a location in the flat aperture. Modify the memory location with a value in the data source register iff the comparison is equal. Store the original value from flat aperture into a vector register iff the GLC bit is set.

Example

flat_atomic_cmpswap_f32 v[1:2], v[2:3]

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources