flat_atomic_csub_u32 GPU Native ISA AMD Vector

Flat Memory

flat_atomic_csub_u32

AMDGPU FLAT vector instruction operating on u32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)

Also written as flat_atomic_sub_clamp_u32. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

AMD's machine-readable ISA specification lists this instruction as flat_atomic_sub_clamp_u32. The operands and layout below are from that entry.

Binary Layout (AMD CDNA 5)
IOFFSET
95:72
VADDR
71:64
unassigned
63
VSRC
62:55
TH
54:52
SCOPE
51:50
SVE
49
SCALE_OFFSET
48
unassigned
47:40
VDST
39:32
11101100
31:24
unassigned
23:22
00110111
21:14
unassigned
13:8
NV
7
SADDR
6:0
 

The ENC_VFLAT layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 55 in OP rebuilds 0x0000000000000000EC0DC000, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. Not the same in every generation: AMD RDNA 4 (field layout).

Format FLAT
Width 96 bits
Opcode 55
Identifier 0x0000000000000000EC0DC000

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Value can be anything. (OPR_VGPR, FMT_ANY)
  • VADDR
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Value can be anything. (OPR_VGPR, FMT_ANY)
  • VSRC
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Value can be anything. (OPR_VGPR, FMT_ANY)
  • SADDR
    Read. Any scalar GPR operand including VCC and NULL. Data format: Value can be anything. (OPR_SREG, FMT_ANY)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VFLAT encoding (AMD CDNA 5).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Flat Memory

Reference

AMDGPU / GFX ISA

Sources