flat_atomic_add_f32 GPU Native ISA AMD Vector
FLAT ATOMIC ADD F32 Flat Memory
flat_atomic_add_f32
Add a single-precision float value in the data register to a location in the flat aperture.
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (FLAT)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
| Target | Support |
|---|---|
| gfx1100 | ✅ Supported |
Floating-point addition handles NAN/INF/denorm.
Related
More in Flat Memory
Reference
AMDGPU / GFX ISA
Description
Add a single-precision float value in the data register to a location in the flat aperture. Store the original value from flat aperture into a vector register iff the SC0 bit is set.
Semantics
tmp = MEM[ADDR].f32;
MEM[ADDR].f32 += DATA.f32;
RETURN_DATA = tmp
Example
flat_atomic_add_f32 v[1:2], v2A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
-
"AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗
- Advanced Micro Devices, Inc.
Reference Guide, page 490. - LLVM MC assembler tests for AMDGPU (gfx11) ↗ - LLVM Project