Zfh Instructions
26 RISC-V instructions in this extension - click any row for encoding, pseudocode, and full documentation.
| Mnemonic | Syntax | Format | Summary |
|---|---|---|---|
| FADD.H | FADD.H rd, rs1, rs2 | R-Type | Performs 16-bit floating-point addition. |
| FCLASS.H | FCLASS.H rd, rs1 | R-Type | Examines a 16-bit floating-point number and generates a classification bitmask. |
| FCVT.H.S | FCVT.H.S rd, rs1 | I-Type (Float) | Converts a 32-bit single-precision float to a 16-bit half-precision float. |
| FCVT.H.W | FCVT.H.W rd, rs1 | I-Type (Float) | Converts a 32-bit signed integer to a 16-bit floating-point number. |
| FCVT.H.WU | FCVT.H.WU rd, rs1 | I-Type (Float) | Converts a 32-bit unsigned integer to a 16-bit floating-point number. |
| FCVT.S.H | FCVT.S.H rd, rs1 | I-Type (Float) | Converts a 16-bit half-precision float to a 32-bit single-precision float. |
| FCVT.W.H | FCVT.W.H rd, rs1 | I-Type (Float) | Converts a 16-bit floating-point number to a 32-bit signed integer. |
| FCVT.WU.H | FCVT.WU.H rd, rs1 | I-Type (Float) | Converts a 16-bit floating-point number to a 32-bit unsigned integer. |
| FDIV.H | FDIV.H rd, rs1, rs2 | R-Type | Performs 16-bit floating-point division. |
| FEQ.H | FEQ.H rd, rs1, rs2 | R-Type | Sets integer rd to 1 if half-precision rs1 equals rs2, else 0. |
| FLE.H | FLE.H rd, rs1, rs2 | R-Type | Sets integer rd to 1 if half-precision rs1 is less than or equal to rs2, else 0. |
| FLH | FLH rd, offset(rs1) | I-Type | Loads a 16-bit half-precision float from memory. |
| FLT.H | FLT.H rd, rs1, rs2 | R-Type | Sets integer rd to 1 if half-precision rs1 is less than rs2, else 0. |
| FMADD.H | FMADD.H rd, rs1, rs2, rs3 | R4-Type | Computes (rs1 * rs2) + rs3 with single rounding (16-bit). |
| FMAX.H | FMAX.H rd, rs1, rs2 | R-Type | Writes the larger of two 16-bit floating-point values to rd. |
| FMIN.H | FMIN.H rd, rs1, rs2 | R-Type | Writes the smaller of two 16-bit floating-point values to rd. |
| FMSUB.H | FMSUB.H rd, rs1, rs2, rs3 | R4-Type | Computes (rs1 * rs2) - rs3 with single rounding (16-bit). |
| FMUL.H | FMUL.H rd, rs1, rs2 | R-Type | Performs 16-bit floating-point multiplication. |
| FNMADD.H | FNMADD.H rd, rs1, rs2, rs3 | R4-Type | Computes -(rs1 * rs2) - rs3 with single rounding (16-bit). |
| FNMSUB.H | FNMSUB.H rd, rs1, rs2, rs3 | R4-Type | Computes -(rs1 * rs2) + rs3 with single rounding (16-bit). |
| FSGNJ.H | FSGNJ.H rd, rs1, rs2 | R-Type | Injects the sign of rs2 into rs1 (16-bit). |
| FSGNJN.H | FSGNJN.H rd, rs1, rs2 | R-Type | Injects the negated sign of rs2 into rs1 (16-bit). |
| FSGNJX.H | FSGNJX.H rd, rs1, rs2 | R-Type | Injects the XOR of signs of rs1 and rs2 (16-bit). |
| FSH | FSH rs2, offset(rs1) | S-Type | Stores a 16-bit half-precision float to memory. |
| FSQRT.H | FSQRT.H rd, rs1 | I-Type (Float) | Computes the square root of a 16-bit floating-point number. |
| FSUB.H | FSUB.H rd, rs1, rs2 | R-Type | Performs 16-bit floating-point subtraction. |