sust GPU Virtual ISA NVIDIA

sust Surface Instructions

sust.b.{1d,2d,3d}{.cop}.vec.ctype.clamp [a, b], c; // unformatted

sust.{1d,2d,3d} Store to surface memory using a surface coordinate vector.

Encoding

PTX is a virtual instruction set. It has no single, stable native binary encoding - the compiler lowers this instruction to different native machine code depending on the selected NVIDIA target architecture (compute capability). This page intentionally shows no bit-diagram; see the target/version requirements below for what governs how this instruction compiles.
PTX ISA Version Introduced PTX ISA 1.5
Minimum Target sm_20

Syntax Forms

One mnemonic covers many type / state-space / scope / modifier combinations - each row below is an independently valid form.

Syntax Data Types State Space(s) Modifiers Min. Target Description
sust.b.{1d,2d,3d}{.cop}.vec.ctype.clamp [a, b], c; // unformatted sm_20 sust.{1d,2d,3d} Store to surface memory using a surface coordinate vector. The instruction stores data from operand c to the surface named by operand a at coordinates given by operand b. (see the official PTX ISA docs for the full description)

Operands

At a Glance

Data Types -

Related AMDGPU Concepts

Surface/Image Store ↗
equivalent with restrictions
image_store (AMDGPU)

Related

More in Surface Instructions

Reference

NVIDIA PTX ISA

Description

sust.{1d,2d,3d} Store to surface memory using a surface coordinate vector. The instruction stores data from operand c to the surface named by operand a at coordinates given by operand b. Operand a is a.surfref variable or.u64 register. Operand b is a scalar or singleton tuple for 1d surfaces; is a two-element vector for 2d surfaces; and is a four-element vector for 3d surfaces, where the fourth element is ignored. Coordinate elements are of type.s32. sust.b performs an unformatted store of binary data. The lowest dimension coordinate represents a byte offset into the surface and is not scaled. (see the official PTX ISA docs for the full description)

Examples

sust.p.1d.v4.b32.trap  [surf_B, {x}], {f1,f2,f3,f4};
sust.b.3d.v2.b64.trap  [surf_A, {x,y,z,w}], {r1,r2};
sust.b.a1d.v2.b64      [surf_C, {idx,x}], {r1,r2};
sust.b.a2d.b32         [surf_D, {idx,x,y,z}], r0;  // z ignored

Reproduced from NVIDIA's official PTX ISA documentation for technical accuracy.

Sources