suq GPU Virtual ISA NVIDIA

suq Surface Instructions

suq.query.b32 d, [a];

Query an attribute of a surface.

Encoding

PTX is a virtual instruction set. It has no single, stable native binary encoding - the compiler lowers this instruction to different native machine code depending on the selected NVIDIA target architecture (compute capability). This page intentionally shows no bit-diagram; see the target/version requirements below for what governs how this instruction compiles.
PTX ISA Version Introduced PTX ISA 1.5
Minimum Target sm_20

Syntax Forms

One mnemonic covers many type / state-space / scope / modifier combinations - each row below is an independently valid form.

Syntax Data Types State Space(s) Modifiers Min. Target Description
suq.query.b32 d, [a]; sm_20 Query an attribute of a surface. Operand a is a.surfref variable or a.u64 register. Query Returns.width.height.depth value in elements. (see the official PTX ISA docs for the full description)

Operands

At a Glance

Data Types -

Related AMDGPU Concepts

Surface/Image Query ↗
equivalent with restrictions

Related

More in Surface Instructions

Reference

NVIDIA PTX ISA

Description

Query an attribute of a surface. Operand a is a.surfref variable or a.u64 register. Query Returns.width.height.depth value in elements.channel_data_type Unsigned integer corresponding to source language’s channel data type enumeration. If the source language combines channel data type and channel order into a single enumeration type, that value is returned for both channel_data_type and channel_order queries..channel_order Unsigned integer corresponding to source language’s channel order enumeration. (see the official PTX ISA docs for the full description)

Examples

suq.width.b32       %r1, [surf_A];

Reproduced from NVIDIA's official PTX ISA documentation for technical accuracy.

Sources