sured GPU Virtual ISA NVIDIA
sured Surface Instructions
sured.b.op.geom.ctype.clamp [a,b],c; // byte addressing
Reduction to surface memory using a surface coordinate vector.
Encoding
PTX is a virtual instruction set. It has no single, stable native
binary encoding - the compiler lowers this instruction to different native machine
code depending on the selected NVIDIA target architecture (compute capability).
This page intentionally shows no bit-diagram; see the target/version requirements
below for what governs how this instruction compiles.
Syntax Forms
One mnemonic covers many type / state-space / scope / modifier combinations - each row below is an independently valid form.
| Syntax | Data Types | State Space(s) | Modifiers | Min. Target | Description |
|---|---|---|---|---|---|
| sured.b.op.geom.ctype.clamp [a,b],c; // byte addressing | sm_20 | Reduction to surface memory using a surface coordinate vector. (see the official PTX ISA docs for the full description) |
Operands
At a Glance
Related
More in Surface Instructions
Reference
NVIDIA PTX ISA
Description
Reduction to surface memory using a surface coordinate vector. The instruction performs a reduction
operation with data from operand c to the surface named by operand a at coordinates given by
operand b. Operand a is a.surfref variable or.u64 register. Operand b is a
scalar or singleton tuple for 1d surfaces; is a two-element vector for 2d surfaces; and is a
four-element vector for 3d surfaces, where the fourth element is ignored. Coordinate elements are of
type.s32.
sured.b performs an unformatted reduction on.u32,.s32,.b32,.u64, or.s64 data. The lowest dimension coordinate represents a byte offset into the surface and is not
scaled. (see the official PTX ISA docs for the full description)
Examples
sured.b.add.2d.u32.trap [surf_A, {x,y}], r1;
sured.p.min.1d.u32.trap [surf_B, {x}], r1;
sured.b.max.1d.u64.trap [surf_C, {x}], r1;
sured.p.min.1d.b64.trap [surf_D, {x}], r1;Reproduced from NVIDIA's official PTX ISA documentation for technical accuracy.
Sources
-
Parallel Thread Execution ISA ↗
- NVIDIA Corporation, Chapter 9 - Instruction Set
Deep-linked directly to this instruction's section.