rcp.approx.ftz.f64 GPU Virtual ISA NVIDIA
rcp.approx.ftz.f64 Floating-Point Instructions
rcp.approx.ftz.f64 d, a;
Compute a fast, gross approximation to the reciprocal as follows: extract the most-significant 32 bits of.f64 operand a in 1.11.20 IEEE floating-point format (i.e., ignore the least-significant 32…
Encoding
PTX is a virtual instruction set. It has no single, stable native
binary encoding - the compiler lowers this instruction to different native machine
code depending on the selected NVIDIA target architecture (compute capability).
This page intentionally shows no bit-diagram; see the target/version requirements
below for what governs how this instruction compiles.
Syntax Forms
One mnemonic covers many type / state-space / scope / modifier combinations - each row below is an independently valid form.
| Syntax | Data Types | State Space(s) | Modifiers | Min. Target | Description |
|---|---|---|---|---|---|
| rcp.approx.ftz.f64 d, a; | sm_20 | Compute a fast, gross approximation to the reciprocal as follows: extract the most-significant 32 bits of.f64 operand a in 1.11.20 IEEE floating-point format (i.e. (see the official PTX ISA docs for the full description) |
Operands
-
d
Destination register -
a
Source operand
At a Glance
Related
More in Floating-Point Instructions
Reference
NVIDIA PTX ISA
Description
Compute a fast, gross approximation to the reciprocal as follows:
extract the most-significant 32 bits of.f64 operand a in 1.11.20 IEEE floating-point
format (i.e., ignore the least-significant 32 bits of a ), compute an approximate.f64 reciprocal of this value using the most-significant 20 bits of
the mantissa of operand a, place the resulting 32-bits in 1.11.20 IEEE floating-point format in the most-significant 32-bits
of destination d,and zero the least significant 32 mantissa bits of.f64 destination d.
Semantics
tmp = a[63:32]; // upper word of a, 1.11.20 format
d[63:32] = 1.0 / tmp;
d[31:0] = 0x00000000;
Examples
rcp.approx.ftz.f64 xi,x;Reproduced from NVIDIA's official PTX ISA documentation for technical accuracy.
Sources
-
Parallel Thread Execution ISA ↗
- NVIDIA Corporation, Chapter 9 - Instruction Set
Deep-linked directly to this instruction's section.