mma GPU Virtual ISA NVIDIA

Matrix Multiply-Accumulate (Tensor Core) Warp Level Matrix Multiply-Accumulate Instructions

mma.sync.aligned.shape.row.col.dtype.atype.btype.ctype d, a, b, c;

Cooperative, warp-wide matrix-multiply-accumulate executed on tensor-core hardware.

Encoding

PTX is a virtual instruction set. It has no single, stable native binary encoding - the compiler lowers this instruction to different native machine code depending on the selected NVIDIA target architecture (compute capability). This page intentionally shows no bit-diagram; see the target/version requirements below for what governs how this instruction compiles.
PTX ISA Version Introduced PTX ISA 6.4
Minimum Target sm_70

Syntax Forms

One mnemonic covers many type / state-space / scope / modifier combinations - each row below is an independently valid form.

Syntax Data Types State Space(s) Modifiers Min. Target Description
mma.sync.aligned.shape.row.col.dtype.atype.btype.ctype d, a, b, c; sm_70 Synchronizing warp-wide MMA for a fixed tile shape (e.g. m16n8k16); operand fragments are distributed across the warp's lanes per a hardware-defined layout.

Operands

  • d
    Accumulator fragment (destination)
  • a
    Matrix A fragment
  • b
    Matrix B fragment
  • c
    Accumulator fragment (input)

At a Glance

Data Types -

Related AMDGPU Concepts

Related

More in Warp Level Matrix Multiply-Accumulate Instructions

Reference

NVIDIA PTX ISA

Description

Perform a MxNxK matrix multiply and accumulate operation, D = A*B+C, where the A matrix is MxK, the B matrix is KxN, and the C and D matrices are MxN. Qualifier.block_scale specifies that the matrices A and B are scaled with scale_A and scale_B matrices respectively before performing the matrix multiply and accumulate operation as specified in the section Block Scaling for mma.sync. The data type corresponding to each of the element within scale_A and Scale_B matrices is specified by.stype. Qualifier.scale_vec_size specifies the number of columns of scale_A matrix and number of rows in the matrix scale_B. The valid combinations of.kind,.stype and.scale_vec_size are described in Table 39. (see the official PTX ISA docs for the full description)

Semantics

D = A * B + C for the fixed tile shape, computed cooperatively across all 32 lanes of the warp.

Sources