v_mfma_f32_16x16x16f16 GPU Native ISA AMD Matrix

Matrix Core Operations

v_mfma_f32_16x16x16f16 D, A, B, C

Matrix-fused-multiply-add: cooperative 16x16x16 matrix-multiply-accumulate on matrix-core hardware, fp16 inputs, fp32 accumulate.

Also written as v_mfma_f32_16x16x16_f16. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Binary Layout (AMD CDNA 2)
BLGP
63:61
ACC
60:59
SRC2
58:50
SRC1
49:41
SRC0
40:32
110100111
31:23
1001101
22:16
ACC_CD
15
ABID
14:11
CBSZ
10:8
VDST
7:0
 

The VOP3P_MFMA layout from AMD's machine-readable ISA specification (AMD CDNA 2). Opcode 77 in OP rebuilds 0x00000000D3CD0000, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 1 (field layout).

Format VOP3P-MAI
Width 64 bits
Opcode 77
Identifier 0x00000000D3CD0000
Execution Unit Matrix Core Unit
Register Classes VGPR, AGPR

Operands

  • D
    Accumulator fragment (destination, VGPR range)
  • A
    Matrix A fragment (VGPR range)
  • B
    Matrix B fragment (VGPR range)
  • C
    Accumulator fragment (input, VGPR range)

GFX Target Compatibility

TargetSupport
gfx942✅ Supported
gfx1100- Not implemented

Matrix-core (MFMA) instructions are a CDNA-family feature; gfx1100 (RDNA3) does not implement this specific MFMA variant - see the AMDGPU landing page's target compatibility notes.

Related PTX Concepts

Related

More in Matrix Core Operations

Reference

AMDGPU / GFX ISA

Description

Multiply the 16x16 matrix in the first input by the 16x16 matrix in the second input and add the 16x16 matrix in the third input using fused multiply add. Store the resulting matrix into vector registers.

Semantics

D = A * B + C for a 16x16x16 tile, computed cooperatively across the wavefront; operand fragments are distributed across lanes per a hardware-defined layout specific to the MFMA family and target.

Example

v_mfma_f32_16x16x16f16  a[0:3], v[0:3], v[4:7], a[0:3]   // 16x16x16 MFMA accumulate

Original illustrative example, written for this site (not reproduced from a specific AMD document).

Sources