ldmatrix GPU Virtual ISA NVIDIA

ldmatrix Warp Level Matrix Multiply-Accumulate Instructions

ldmatrix.sync.aligned.shape.num{.trans}{.ss}.type r, [p];

Collectively load one or more matrices across all threads in a warp from the location indicated by the address operand p, from.shared state space into destination register r.

Encoding

PTX is a virtual instruction set. It has no single, stable native binary encoding - the compiler lowers this instruction to different native machine code depending on the selected NVIDIA target architecture (compute capability). This page intentionally shows no bit-diagram; see the target/version requirements below for what governs how this instruction compiles.
PTX ISA Version Introduced PTX ISA 6.5
Minimum Target sm_75

Syntax Forms

One mnemonic covers many type / state-space / scope / modifier combinations - each row below is an independently valid form.

Syntax Data Types State Space(s) Modifiers Min. Target Description
ldmatrix.sync.aligned.shape.num{.trans}{.ss}.type r, [p]; sm_75 Collectively load one or more matrices across all threads in a warp from the location indicated by the address operand p, from.shared state space into destination register r. (see the official PTX ISA docs for the full description)

Operands

At a Glance

Data Types -

Related

More in Warp Level Matrix Multiply-Accumulate Instructions

Reference

NVIDIA PTX ISA

Description

Collectively load one or more matrices across all threads in a warp from the location indicated by the address operand p, from.shared state space into destination register r. If no state space is provided, generic addressing is used, such that the address in p points into.shared space. If the generic address doesn’t fall in.shared state space, then the behavior is undefined. The.shape qualifier indicates the dimensions of the matrices being loaded. (see the official PTX ISA docs for the full description)

Examples

// Load a single 8x8 matrix using 64-bit addressing
.reg .b64 addr;
.reg .b32 d;
ldmatrix.sync.aligned.m8n8.x1.shared::cta.b16 {d}, [addr];

// Load two 8x8 matrices in column-major format
// (truncated - see the official PTX ISA docs for the full example)

Reproduced from NVIDIA's official PTX ISA documentation for technical accuracy.

Sources