tld4 GPU Virtual ISA NVIDIA

tld4 Texture Instructions

tld4.comp.2d.v4.dtype.f32 d[|p], [a, c] {, e} {, f};

Texture fetch of the 4-texel bilerp footprint using a texture coordinate vector.

Encoding

PTX is a virtual instruction set. It has no single, stable native binary encoding - the compiler lowers this instruction to different native machine code depending on the selected NVIDIA target architecture (compute capability). This page intentionally shows no bit-diagram; see the target/version requirements below for what governs how this instruction compiles.
PTX ISA Version Introduced PTX ISA 2.2
Minimum Target sm_20

Syntax Forms

One mnemonic covers many type / state-space / scope / modifier combinations - each row below is an independently valid form.

Syntax Data Types State Space(s) Modifiers Min. Target Description
tld4.comp.2d.v4.dtype.f32 d[|p], [a, c] {, e} {, f}; sm_20 Texture fetch of the 4-texel bilerp footprint using a texture coordinate vector. (see the official PTX ISA docs for the full description)

Operands

At a Glance

Data Types -

Related

More in Texture Instructions

Reference

NVIDIA PTX ISA

Description

Texture fetch of the 4-texel bilerp footprint using a texture coordinate vector. The instruction loads the bilerp footprint from the texture named by operand a at coordinates given by operand c into vector destination d. The texture component fetched for each texel sample is specified by.comp. The four texel samples are placed into destination vector d in counter-clockwise order starting at lower left. An optional texture sampler b may be specified. If no sampler is specified, the sampler behavior is a property of the named texture. The optional destination predicate p is set to True if data from texture at specified coordinates is resident in memory, False otherwise. (see the official PTX ISA docs for the full description)

Examples

//Example of unified mode texturing
tld4.r.2d.v4.s32.f32  {r1,r2,r3,r4}, [tex_a,{f1,f2}];

// Example of independent mode texturing
tld4.r.2d.v4.u32.f32  {u1,u2,u3,u4}, [tex_a,smpl_x,{f1,f2}];
// (truncated - see the official PTX ISA docs for the full example)

Reproduced from NVIDIA's official PTX ISA documentation for technical accuracy.

Sources