Private and Scratch Memory Access Memory

Load and store a thread's own private memory, used for register spills and indexed local arrays.

Vendor-Neutral Definition

Per-thread storage backed by off-chip memory, addressed so that each lane sees a private copy. It is where a local array lands when the compiler cannot keep it in registers.
⚠️ Cross-vendor mappings describe semantic relationships and are not guaranteed one-to-one compiler translations.
equivalent with restrictions Both provide per-thread private storage distinct from global and shared memory, reached through a dedicated address space.
Property NVIDIA PTX AMDGPU
Instruction ld, st scratch_load_dword, scratch_store_dword
ISA Layer Virtual Native
Data Types b16, b32, b64, b8, f16, f32, f64, s16, s32, s64, s8, u16, u32, u64, u8 -
Version / Target Introduced PTX ISA 1.0, PTX ISA 1.0 -

Important Differences

  • PTX names the space in the instruction as ld.local and st.local, sharing the ld and st opcodes with every other space. AMDGPU has dedicated scratch_ instructions instead.
  • Addressing differs in kind: AMDGPU scratch accesses are swizzled so that neighbouring lanes touch neighbouring dwords, which makes a per-lane spill coalesce. PTX leaves the layout to the implementation.
  • On both, this space is the slowest place a value can live, and traffic here is the usual sign of register pressure rather than an intentional choice.

Source Evidence

Verification method: documentation