v_cmpx_f_u16 GPU Native ISA AMD Vector
V CMPX F U16 Comparison
v_cmpx_f_u16
Set the per-lane condition code to 0. Store the result into the EXEC mask and to VCC or a scalar register.
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (VOPC)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
Per-target GFX compatibility has not yet been verified for this instruction.
Related
More in Comparison
Reference
AMDGPU / GFX ISA
Semantics
EXEC.u64[laneId] = D0.u64[laneId] = 1'0U;
// D0 = VCC in VOPC encoding.
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
-
"AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗
- Advanced Micro Devices, Inc.
Reference Guide, page 247.