v_cmpx_f_i16 GPU Native ISA AMD Vector

Comparison

v_cmpx_f_i16

Set the per-lane condition code to 0. Store the result into the EXEC mask and to VCC or a scalar register.

Encoding

Binary Layout (AMD CDNA 4)
0111110
31:25
10110000
24:17
VSRC1
16:9
SRC0
8:0
 

The ENC_VOPC layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 176 in OP rebuilds 0x7D600000, an identifier AMD lists for this encoding. The same in the other 3 generations that define it.

Format VOPC
Width 32 bits
Opcode 176
Identifier 0x7D600000

Operands

  • vcc
    Written. Written in the assembly; this encoding has no field for it. N/A Data format: N/A (OPR_VCC, FMT_NUM_M64)
  • SRC0
    Read. N/A Data format: N/A (OPR_SRC, FMT_NUM_I16)
  • VSRC1
    Read. N/A Data format: N/A (OPR_VGPR, FMT_NUM_I16)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOPC encoding (AMD CDNA 4).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Comparison

Reference

AMDGPU / GFX ISA

Semantics

EXEC.u64[laneId] = D0.u64[laneId] = 1'0U; // D0 = VCC in VOPC encoding.

Example

v_cmpx_f_i16 vcc, 0, v2

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx8_asm_vopc.s). Not from an AMD document, and not authored here.

Sources