s_atomic_inc_x2 GPU Native ISA AMD Scalar

Scalar Memory

s_atomic_inc_x2

Increment an unsigned 64-bit integer value from a location in the scalar memory with wraparound to 0 if the value exceeds a value in the data…

Encoding

Binary Layout (AMD CDNA 4)
SOFFSET
63:57
unassigned
56:53
OFFSET
52:32
110000
31:26
10101011
25:18
IMM
17
GLC
16
NV
15
SOFFSET_EN
14
unassigned
13
SDATA
12:6
SBASE
5:0
 

The ENC_SMEM layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 171 in OP rebuilds 0x00000000C2AC0000, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. The same in the other 3 generations that define it.

Format SMEM
Width 64 bits
Opcode 171
Identifier 0x00000000C2AC0000

Operands

  • SDATA
    Written. N/A Data format: Value can be anything. (OPR_SREG, FMT_ANY)
  • SBASE
    Read. N/A Data format: 64-bit virtual memory address. (OPR_SREG, FMT_BUF)
  • SOFFSET
    Read. N/A Data format: N/A (OPR_SMEM_OFFSET, FMT_NUM_B32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SMEM encoding (AMD CDNA 4).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Scalar Memory

Reference

AMDGPU / GFX ISA

Description

Increment an unsigned 64-bit integer value from a location in the scalar memory with wraparound to 0 if the value exceeds a value in the data register.

Example

s_atomic_inc_x2 vcc, s[2:3], s0

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx9_asm_smem.s). Not from an AMD document, and not authored here.

Sources