s_atc_probe GPU Native ISA AMD Scalar

Scalar Memory

s_atc_probe

Probe or prefetch an address into the scalar data cache.

Encoding

Binary Layout (AMD CDNA 5)
SOFFSET
63:57
SCALE_OFFSET
56
IOFFSET
55:32
111101
31:26
unassigned
25
TH
24:23
SCOPE
22:21
NV
20
unassigned
19
100010
18:13
SDATA
12:6
SBASE
5:0
 

The ENC_SMEM layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 34 in OP rebuilds 0x00000000F4044000, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. Not the same in every generation: AMD CDNA 4 (opcode 38, field layout), AMD CDNA 3 (opcode 38, field layout), AMD CDNA 2 (opcode 38, field layout), AMD CDNA 1 (opcode 38, field layout), AMD RDNA 4 (field layout), AMD RDNA 3.5 (field layout), AMD RDNA 1 (opcode 38, field layout).

Format SMEM
Width 64 bits
Opcode 34
Identifier 0x00000000F4044000

Operands

  • SDATA
    Read. 8-bit integer constant. Data format: 8 bits of arbitrary data. (OPR_SIMM8, FMT_NUM_B8)
  • SBASE
    Read. Any scalar GPR operand including VCC and NULL. Data format: 64-bit virtual memory address. (OPR_SREG, FMT_BUF)
  • SOFFSET
    Read. Operand is a scalar memory offset, which may come from a scalar GPR, from M0 or from a 24-bit immediate constant. Data format: 32 bits of arbitrary data. (OPR_SMEM_OFFSET, FMT_NUM_B32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SMEM encoding (AMD CDNA 5).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Scalar Memory

Reference

AMDGPU / GFX ISA

Example

s_atc_probe 0x0, vcc, s3

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx8_asm_smem.s). Not from an AMD document, and not authored here.

Sources