wgmma.fence GPU Virtual ISA NVIDIA

wgmma.fence Asynchronous Warpgroup Level Matrix Multiply-Accumulate Instructions

wgmma.fence.sync.aligned;

wgmma.fence instruction establishes an ordering between prior accesses to any warpgroup registers and subsequent accesses to the same registers by a wgmma.mma_async instruction.

Encoding

PTX is a virtual instruction set. It has no single, stable native binary encoding - the compiler lowers this instruction to different native machine code depending on the selected NVIDIA target architecture (compute capability). This page intentionally shows no bit-diagram; see the target/version requirements below for what governs how this instruction compiles.
PTX ISA Version Introduced PTX ISA 8.0
Minimum Target sm_90a

Syntax Forms

One mnemonic covers many type / state-space / scope / modifier combinations - each row below is an independently valid form.

Syntax Data Types State Space(s) Modifiers Min. Target Description
wgmma.fence.sync.aligned; sm_90a wgmma.fence instruction establishes an ordering between prior accesses to any warpgroup registers and subsequent accesses to the same registers by a wgmma.mma_async instruction. (see the official PTX ISA docs for the full description)

Operands

At a Glance

Data Types -

Related

More in Asynchronous Warpgroup Level Matrix Multiply-Accumulate Instructions

Reference

NVIDIA PTX ISA

Description

wgmma.fence instruction establishes an ordering between prior accesses to any warpgroup registers and subsequent accesses to the same registers by a wgmma.mma_async instruction. Only the accumulator register and the input registers containing the fragments of matrix A require this ordering. The wgmma.fence instruction must be issued by all warps of the warpgroup at the following locations: Before the first wgmma.mma_async operation in a warpgroup. (see the official PTX ISA docs for the full description)

Examples

// Example 1, first use example:
wgmma.fence.sync.aligned;    // Establishes an ordering w.r.t. prior accesses to the registers s32d<0-3>
wgmma.mma_async.sync.aligned.m64n8k32.s32.u8.u8  {s32d0, s32d1, s32d2, s32d3},
                                                  descA, descB, scaleD;
wgmma.commit_group.sync.aligned;
wgmma.wait_group.sync.aligned 0;
// (truncated - see the official PTX ISA docs for the full example)

Reproduced from NVIDIA's official PTX ISA documentation for technical accuracy.

Sources