vsub2 GPU Virtual ISA NVIDIA

vsub2 SIMD Video Instructions

// SIMD instruction with secondary SIMD merge operation
vsub2.dtype.atype.btype{.sat} d{.mask}, a{.asel}, b{.bsel}, c;

Two-way SIMD parallel arithmetic operation with secondary operation.

Encoding

PTX is a virtual instruction set. It has no single, stable native binary encoding - the compiler lowers this instruction to different native machine code depending on the selected NVIDIA target architecture (compute capability). This page intentionally shows no bit-diagram; see the target/version requirements below for what governs how this instruction compiles.
PTX ISA Version Introduced PTX ISA 3.0
Minimum Target sm_30

Syntax Forms

One mnemonic covers many type / state-space / scope / modifier combinations - each row below is an independently valid form.

Syntax Data Types State Space(s) Modifiers Min. Target Description
// SIMD instruction with secondary SIMD merge operation vsub2.dtype.atype.btype{.sat} d{.mask}, a{.asel}, b{.bsel}, c; sm_30 Two-way SIMD parallel arithmetic operation with secondary operation. (see the official PTX ISA docs for the full description)

Operands

At a Glance

Data Types -

Related

More in SIMD Video Instructions

Reference

NVIDIA PTX ISA

Description

Two-way SIMD parallel arithmetic operation with secondary operation. Elements of each dual half-word source to the operation are selected from any of the four half-words in the two source operands a and b using the asel and bsel modifiers. The selected half-words are then operated on in parallel. The results are optionally clamped to the appropriate range determined by the destination type (signed or unsigned). Saturation cannot be used with the secondary accumulate operation. For instructions with a secondary SIMD merge operation: For half-word positions indicated in mask, the selected half-word results are copied into destination d. (see the official PTX ISA docs for the full description)

Semantics

// extract pairs of half-words and sign- or zero-extend // based on operand type Va = extractAndSignExt_2( a, b, .asel, .atype ); Vb = extractAndSignExt_2( a, b, .bsel, .btype ); Vc = extractAndSignExt_2( c ); for (i=0; i<2; i++) { switch ( vop2 ) { case vadd2: t[i] = Va[i] + Vb[i]; case vsub2: t[i] = Va[i] - Vb[i]; case vavrg2: if ( ( Va[i] + Vb[i] ) >= 0 ) { t[i] = ( Va[i] + Vb[i] + 1 ) >> 1; } else { t[i] = ( Va[i] + Vb[i] ) >> 1; } case vabsdiff2: t[i] = | Va[i] - Vb[i] |; case vmin2: t[i] = MIN( Va[i], Vb[i] ); case vmax2: t[i] = MAX( Va[i], Vb[i] ); } if (.sat) { if ( .dtype == .s32 ) t[i] = CLAMP( t[i], S16_MAX, S16_MIN ); (see the official PTX ISA docs for the full semantics)

Examples

vadd2.s32.s32.u32.sat  r1, r2, r3, r1;
vsub2.s32.s32.s32.sat  r1.h0, r2.h10, r3.h32, r1;
vmin2.s32.u32.u32.add  r1.h10, r2.h00, r3.h22, r1;

Reproduced from NVIDIA's official PTX ISA documentation for technical accuracy.

Sources