tcgen05.shift GPU Virtual ISA NVIDIA

tcgen05.shift Tensor Memory Data Movement Instructions

tcgen05.shift.cta_group.down [taddr];

Instruction tcgen05.shift is an asynchronous instruction which initiates the shifting of 32-byte elements downwards across all the rows, except the last, by one row.

Encoding

PTX is a virtual instruction set. It has no single, stable native binary encoding - the compiler lowers this instruction to different native machine code depending on the selected NVIDIA target architecture (compute capability). This page intentionally shows no bit-diagram; see the target/version requirements below for what governs how this instruction compiles.
PTX ISA Version Introduced PTX ISA 8.6
Minimum Target sm_100a

Syntax Forms

One mnemonic covers many type / state-space / scope / modifier combinations - each row below is an independently valid form.

Syntax Data Types State Space(s) Modifiers Min. Target Description
tcgen05.shift.cta_group.down [taddr]; sm_100a Instruction tcgen05.shift is an asynchronous instruction which initiates the shifting of 32-byte elements downwards across all the rows, except the last, by one row. (see the official PTX ISA docs for the full description)

Operands

At a Glance

Data Types -

Related

More in Tensor Memory Data Movement Instructions

Reference

NVIDIA PTX ISA

Description

Instruction tcgen05.shift is an asynchronous instruction which initiates the shifting of 32-byte elements downwards across all the rows, except the last, by one row. The address operand taddr specifies the base address of the matrix in the Tensor Memory whose rows must be down shifted. The lane of the address operand taddr must be aligned to 32. Qualifier.cta_group specifies the number of CTAs whose Tensor Memory is touched when a single thread of a single CTA executes the tcgen05.shift instruction. When.cta_group::1 is specified, the shift operation is performed in the Tensor Memory of the current CTA. (see the official PTX ISA docs for the full description)

Examples

tcgen05.shift.down.cta_group::1 [taddr0];
tcgen05.shift.down.cta_group::2 [taddr1];

Reproduced from NVIDIA's official PTX ISA documentation for technical accuracy.

Sources