tcgen05.cp GPU Virtual ISA NVIDIA

tcgen05.cp Tensor Memory Data Movement Instructions

tcgen05.cp.cta_group.shape{.multicast}{.dst_fmt.src_fmt} [taddr], s-desc;

Instruction tcgen05.cp initiates an asynchronous copy operation from shared memory to the location specified by the address operand taddr in the Tensor Memory.

Encoding

PTX is a virtual instruction set. It has no single, stable native binary encoding - the compiler lowers this instruction to different native machine code depending on the selected NVIDIA target architecture (compute capability). This page intentionally shows no bit-diagram; see the target/version requirements below for what governs how this instruction compiles.
PTX ISA Version Introduced PTX ISA 8.6
Minimum Target sm_100a

Syntax Forms

One mnemonic covers many type / state-space / scope / modifier combinations - each row below is an independently valid form.

Syntax Data Types State Space(s) Modifiers Min. Target Description
tcgen05.cp.cta_group.shape{.multicast}{.dst_fmt.src_fmt} [taddr], s-desc; sm_100a Instruction tcgen05.cp initiates an asynchronous copy operation from shared memory to the location specified by the address operand taddr in the Tensor Memory. (see the official PTX ISA docs for the full description)

Operands

At a Glance

Data Types -

Related

More in Tensor Memory Data Movement Instructions

Reference

NVIDIA PTX ISA

Description

Instruction tcgen05.cp initiates an asynchronous copy operation from shared memory to the location specified by the address operand taddr in the Tensor Memory. The 64-bit register operand s-desc is the matrix descriptor which represents the source matrix in the shared memory that needs to be copied. The format of the matrix descriptor is described in Matrix Descriptors. The.shape qualifier indicates the dimension of data to be copied as described in the Data Movement Shape. Qualifier.cta_group specifies the number of CTAs whose Tensor Memory is accessed when a single thread of a single CTA executes the tcgen05.cp instruction. When. (see the official PTX ISA docs for the full description)

Examples

tcgen05.cp.cta_group::1.128x256b                 [taddr0], sdesc0;
tcgen05.cp.cta_group::2.128x128b.b8x16.b6x16_p32 [taddr1], sdesc1;
tcgen05.cp.cta_group::1.64x128b.warpx2::02_13    [taddr2], sdesc2;

Reproduced from NVIDIA's official PTX ISA documentation for technical accuracy.

Sources