fabric.try_red.async.tensor GPU Virtual ISA NVIDIA

Fabric Instructions

// Form 0
fabric.try_red.async.tensor{.multimem}.dim.src{.load_mode}.completion_mechanism0
{.level::cache_hint}.override::global_address{.override_attribute}
.sem.sco.redOp.type
[tensorMap, tensorMapLeId, tensorMapOff,
attributeOverrideInfo, tensorCoords], [src], sizeBytes, [mbar] {, cache_policy};

Asynchronously copies sizeBytes bytes from source memory [src] to the tensor at fabric handle [tensorMapLeId, tensorMapOff] with element-wise reduction, where tensorMapLeId is a 32-bit unsigned value…

Encoding

PTX is a virtual instruction set. It has no single, stable native binary encoding - the compiler lowers this instruction to different native machine code depending on the selected NVIDIA target architecture (compute capability). This page intentionally shows no bit-diagram; see the target/version requirements below for what governs how this instruction compiles.
PTX ISA Version Introduced PTX ISA 9.4
Minimum Target sm_107f

Syntax Forms

One mnemonic covers many type / state-space / scope / modifier combinations - each row below is an independently valid form.

Syntax Data Types State Space(s) Modifiers Min. Target Description
// Form 0 fabric.try_red.async.tensor{.multimem}.dim.src{.load_mode}.completion_mechanism0 {.level::cache_hint}.override::global_address{.override_attribute} .sem.sco.redOp.type [tensorMap, tensorMapLeId, tensorMapOff, attributeOverrideInfo, tensorCoords], [src], sizeBytes, [mbar] {, cache_policy}; sm_107f Asynchronously copies sizeBytes bytes from source memory [src] to the tensor at fabric handle [tensorMapLeId, tensorMapOff] with element-wise reduction, where tensorMapLeId is a 32-bit unsigned… (see the official PTX ISA docs for the full description)

Operands

At a Glance

Data Types -

Related

More in Fabric Instructions

Reference

NVIDIA PTX ISA

Description

Asynchronously copies sizeBytes bytes from source memory [src] to the tensor at fabric handle [tensorMapLeId, tensorMapOff] with element-wise reduction, where tensorMapLeId is a 32-bit unsigned value denoting the logical endpoint identifier, and tensorMapOff is a 64-bit unsigned value denoting the base offset of the resource to access within the logical endpoint associated with tensorMapLeId. The sizeBytes operand is 32 bits and specifies the number of bytes to be copied. It must be a multiple of 16; otherwise, the behavior is undefined. The range [src, src + sizeBytes - 1] must be in bounds of the source memory space. (see the official PTX ISA docs for the full description)

Examples

fabric.try_red.async.tensor.2d.shared::cta.tile.mbarrier::complete_tx::16B.mbarrier::report::fabric.override::global_address.override::global_dim_stride.relaxed.sys.max
       [tensorDesc, overrideLeId, overrideLeOff, {overrideSize_0, overrideSize_1}, {overrideLowerStrd_0}, overrideUpperStrd, {u, v}], [srcSmem], numBytes, [mbar];

fabric.try_red.async.tensor.3d.shared::cta.tile.mbarrier::complete_tx::16B.mbarrier::report::fabric.override::global_address.override::global_dim_stride.relaxed.sys.L2::cache_hint.or
       [tensorDesc, overrideLeId, overrideLeOff, {overrideSize_0, overrideSize_1, overrideSize_2}, {overrideLowerStrd_0, overrideLowerStrd_1}, overrideUpperStrd, {u, v, w}], [srcSmem], numBytes, [mbar], mdesc;

Reproduced from NVIDIA's official PTX ISA documentation for technical accuracy.

Sources