fabric.try_get.async.tensor GPU Virtual ISA NVIDIA
Fabric Instructions
fabric.try_get.async.tensor.dim.dst{.load_mode}.completion_mechanism
{.level::cache_hint}.override::global_address{.override_attribute}
.sem.sco.b128
[dstMem], [tensorMap, tensorMapLeId, tensorMapOff,
attributeOverrideInfo, tensorCoords], [mbar] {, cache_policy};
{.level::cache_hint}.override::global_address{.override_attribute}
.sem.sco.b128
[dstMem], [tensorMap, tensorMapLeId, tensorMapOff,
attributeOverrideInfo, tensorCoords], [mbar] {, cache_policy};
Asynchronously copies data from the tensor at fabric handle [tensorMapLeId, tensorMapOff] to destination memory [dstMem], where tensorMapLeId is a 32-bit unsigned value denoting the logical endpoint…
Encoding
PTX is a virtual instruction set. It has no single, stable native
binary encoding - the compiler lowers this instruction to different native machine
code depending on the selected NVIDIA target architecture (compute capability).
This page intentionally shows no bit-diagram; see the target/version requirements
below for what governs how this instruction compiles.
Syntax Forms
One mnemonic covers many type / state-space / scope / modifier combinations - each row below is an independently valid form.
| Syntax | Data Types | State Space(s) | Modifiers | Min. Target | Description |
|---|---|---|---|---|---|
| fabric.try_get.async.tensor.dim.dst{.load_mode}.completion_mechanism {.level::cache_hint}.override::global_address{.override_attribute} .sem.sco.b128 [dstMem], [tensorMap, tensorMapLeId, tensorMapOff, attributeOverrideInfo, tensorCoords], [mbar] {, cache_policy}; | sm_107f | Asynchronously copies data from the tensor at fabric handle [tensorMapLeId, tensorMapOff] to destination memory [dstMem], where tensorMapLeId is a 32-bit unsigned value denoting the logical endpoint… (see the official PTX ISA docs for the full description) |
Operands
At a Glance
Related
More in Fabric Instructions
Reference
NVIDIA PTX ISA
Description
Asynchronously copies data from the tensor at fabric handle [tensorMapLeId, tensorMapOff] to destination memory [dstMem], where tensorMapLeId is a 32-bit unsigned value denoting
the logical endpoint identifier, and tensorMapOff is a 64-bit unsigned value denoting the
base offset of the resource to access within the logical endpoint associated with tensorMapLeId.
The logical endpoint associated with tensorMapLeId must be a unicast logical endpoint.
The range [dstMem, dstMem + size - 1] must be in bounds of the destination memory space,
where size is computed using the tensor descriptor tensorMap, and it is the number of
bytes copied from the source fabric handle. (see the official PTX ISA docs for the full description)
Examples
fabric.try_get.async.tensor.1d.shared::cta.tiled.mbarrier::complete_tx::bytes.mbarrier::report::fabric.override::global_address.relaxed.sys.b128 [dstSmem], [tensorDesc, overrideLeId, overrideLeOff, {u}], [mbar];
fabric.try_get.async.tensor.1d.shared::cta.tiled.mbarrier::complete_tx::bytes.mbarrier::report::fabric.override::global_address.relaxed.sys.l2::cache_hint.b128 [dstSmem], [tensorDesc, overrideLeId, overrideLeOff, {u}], [mbar], mdesc;Reproduced from NVIDIA's official PTX ISA documentation for technical accuracy.
Sources
-
Parallel Thread Execution ISA ↗
- NVIDIA Corporation, Chapter 9 - Instruction Set
Deep-linked directly to this instruction's section.