v_swmmac_f32_16x16x32_bf8_fp8 GPU Native ISA AMD Matrix

Vector Packed Arithmetic

v_swmmac_f32_16x16x32_bf8_fp8

Multiply the 16x32 matrix in the first input by the 32x16 matrix in the second input and accumulate the result into the 16x16 matrix in the…

Encoding

Binary Layout (AMD RDNA 4)
NEG
63:61
OPSEL_HI[1:0]
60:59
SRC2
58:50
SRC1
49:41
SRC0
40:32
11001100
31:24
unassigned
23
1011001
22:16
CLAMP
15
OPSEL_HI[2]
14
OPSEL
13:11
NEG_HI
10:8
VDST
7:0
 

The ENC_VOP3P layout from AMD's machine-readable ISA specification (AMD RDNA 4). Opcode 89 in OP rebuilds 0x00000000CC590000, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. No other generation in the specification defines this instruction.

Format VOP3P
Width 64 bits
Opcode 89
Identifier 0x00000000CC590000

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: WMMA destination (D) or accumulator (C) 16x16 matrix with single precision float values. WMMA DC matrices are 16x16 (or larger) and the individual elements are packed. The total number of VGPRs required depends on the wave size. (OPR_VGPR, FMT_WMMA_DC_16X16_F32)
  • SRC0
    Read. Operand must be a vector GPR. Uses a 9-bit operand field. Data format: WMMA 16x16 multiplicand matrix (A or B) with 8-bit brain floats. WMMA AB matrices are 16x16 (or larger) and the individual elements are packed; each VGPR lane can contain 2 16-bit elements, 4 8-bit elements or 8 4-bit elements. (OPR_SRC_VGPR, FMT_WMMA_AB_16X16_BF8)
  • SRC1
    Read. Operand must be a vector GPR. Uses a 9-bit operand field. Data format: WMMA 16x32 multiplicand matrix (A or B) with 8-bit floats. WMMA AB matrices are 16x16 (or larger) and the individual elements are packed; each VGPR lane can contain 2 16-bit elements, 4 8-bit elements or 8 4-bit elements. (OPR_SRC_VGPR, FMT_WMMA_AB_16X32_FP8)
  • SRC2
    Read. Operand must be a vector GPR. Uses a 9-bit operand field. Data format: Index set for SWMMAC instructions (see OPF_SWMMAC). Consists of 2-bit indices with the constraint that for each pair, index0 < index1. (OPR_SRC_VGPR, FMT_WMMA_INDEX_SET)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP3P encoding (AMD RDNA 4).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Vector Packed Arithmetic

Reference

AMDGPU / GFX ISA

Description

Multiply the 16x32 matrix in the first input by the 32x16 matrix in the second input and accumulate the result into the 16x16 matrix in the destination registers using fused multiply add. Sparse indexes for the first matrix are given in the third input.

Sources