v_smfmac_f32_32x32x32fp8bf8 GPU Native ISA AMD Matrix

Vector Packed Arithmetic

v_smfmac_f32_32x32x32fp8bf8

AMDGPU VOP3P matrix instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)

Also written as v_smfmac_f32_32x32x32_fp8_bf8. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

AMD's machine-readable ISA specification lists this instruction as v_smfmac_f32_32x32x32_fp8_bf8, which has its own page here. The operands and layout below are from that entry.

Binary Layout (AMD CDNA 4)
BLGP
63:61
ACC
60:59
SRC2
58:50
SRC1
49:41
SRC0
40:32
110100111
31:23
1111110
22:16
ACC_CD
15
ABID
14:11
CBSZ
10:8
VDST
7:0
 

The VOP3P_MFMA layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 126 in OP rebuilds 0x00000000D3FE0000, an identifier AMD lists for this encoding. The same in AMD CDNA 3.

Format VOP3P
Width 64 bits
Opcode 126
Identifier 0x00000000D3FE0000

Operands

  • VDST
    Written. N/A Data format: N/A (OPR_VGPR_OR_ACCVGPR, FMT_NUM_PK16_F32)
  • SRC0
    Read. N/A Data format: N/A (OPR_SRC_VGPR_OR_ACCVGPR, FMT_NUM_PK8_FP8)
  • SRC1
    Read. N/A Data format: N/A (OPR_SRC_VGPR_OR_ACCVGPR, FMT_NUM_PK16_BF8)
  • SRC2
    Read. N/A Data format: N/A (OPR_SRC_VGPR, FMT_NUM_B32)

In AMD's order, as its machine-readable ISA specification lists them for the VOP3P_MFMA encoding (AMD CDNA 4).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Vector Packed Arithmetic

Reference

AMDGPU / GFX ISA

Sources