export GPU Native ISA AMD Vector

Export

export

Export graphics data to the next stage of the render pipeline. The target and up to four channels of data are specified as operands.

Also written as exp. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (EXP) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format EXP

Operands

  • TGT
    Written. Target to export shader data to. Data format: Value can be anything. (OPR_TGT, FMT_ANY)
  • VSRC0
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Value can be anything. (OPR_VGPR, FMT_ANY)
  • VSRC1
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Value can be anything. (OPR_VGPR, FMT_ANY)
  • VSRC2
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Value can be anything. (OPR_VGPR, FMT_ANY)
  • VSRC3
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Value can be anything. (OPR_VGPR, FMT_ANY)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VEXPORT encoding (AMD RDNA 4).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Export

Reference

AMDGPU / GFX ISA

Example

export mrt0 v4, v3, v2, v1

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx12_asm_exp.s). Not from an AMD document, and not authored here.

Sources