vsub GPU Virtual ISA NVIDIA

vsub Scalar Video Instructions

// 32-bit scalar operation, with optional secondary operation
vsub.dtype.atype.btype{.sat} d, a{.asel}, b{.bsel};

Perform scalar arithmetic operation with optional saturate, and optional secondary arithmetic operation or subword data merge.

Encoding

PTX is a virtual instruction set. It has no single, stable native binary encoding - the compiler lowers this instruction to different native machine code depending on the selected NVIDIA target architecture (compute capability). This page intentionally shows no bit-diagram; see the target/version requirements below for what governs how this instruction compiles.
PTX ISA Version Introduced PTX ISA 2.0
Minimum Target sm_20

Syntax Forms

One mnemonic covers many type / state-space / scope / modifier combinations - each row below is an independently valid form.

Syntax Data Types State Space(s) Modifiers Min. Target Description
// 32-bit scalar operation, with optional secondary operation vsub.dtype.atype.btype{.sat} d, a{.asel}, b{.bsel}; sm_20 Perform scalar arithmetic operation with optional saturate, and optional secondary arithmetic operation or subword data merge.

Operands

At a Glance

Data Types -

Related

More in Scalar Video Instructions

Reference

NVIDIA PTX ISA

Semantics

// extract byte/half-word/word and sign- or zero-extend // based on source operand type ta = partSelectSignExtend( a, atype, asel ); tb = partSelectSignExtend( b, btype, bsel ); switch ( vop ) { case vadd: tmp = ta + tb; case vsub: tmp = ta - tb; case vabsdiff: tmp = | ta - tb |; case vmin: tmp = MIN( ta, tb ); case vmax: tmp = MAX( ta, tb ); } // saturate, taking into account destination type and merge operations tmp = optSaturate( tmp, sat, isSigned(dtype), dsel ); d = optSecondaryOp( op2, tmp, c ); // optional secondary operation d = optMerge( dsel, tmp, c ); // optional merge with c operand

Examples

vadd.s32.u32.s32.sat      r1, r2.b0, r3.h0;
vsub.s32.s32.u32.sat      r1, r2.h1, r3.h1;
vabsdiff.s32.s32.s32.sat  r1.h0, r2.b0, r3.b2, c;
vmin.s32.s32.s32.sat.add  r1, r2, r3, c;

Reproduced from NVIDIA's official PTX ISA documentation for technical accuracy.

Sources