tcgen05.st GPU Virtual ISA NVIDIA

tcgen05.st Tensor Memory and Register Load/Store Instructions

tcgen05.st.sync.aligned.shape1.num{.unpack}.b32 [taddr], r;

Instruction tcgen05.st asynchronously stores data from the source register r into the Tensor Memory at the location specified by the 32-bit address operand taddr, collectively across all threads of the warps.

Encoding

PTX is a virtual instruction set. It has no single, stable native binary encoding - the compiler lowers this instruction to different native machine code depending on the selected NVIDIA target architecture (compute capability). This page intentionally shows no bit-diagram; see the target/version requirements below for what governs how this instruction compiles.
PTX ISA Version Introduced PTX ISA 8.6
Minimum Target sm_100a

Syntax Forms

One mnemonic covers many type / state-space / scope / modifier combinations - each row below is an independently valid form.

Syntax Data Types State Space(s) Modifiers Min. Target Description
tcgen05.st.sync.aligned.shape1.num{.unpack}.b32 [taddr], r; sm_100a Instruction tcgen05.st asynchronously stores data from the source register r into the Tensor Memory at the location specified by the 32-bit address operand taddr, collectively across all threads of th… (see the official PTX ISA docs for the full description)

Operands

At a Glance

Data Types -

Related

More in Tensor Memory and Register Load/Store Instructions

Reference

NVIDIA PTX ISA

Description

Instruction tcgen05.st asynchronously stores data from the source register r into the Tensor Memory at the location specified by the 32-bit address operand taddr, collectively across all threads of the warps. All the threads in the warp must specify the same value of taddr, which must be the base address of the collective store operation. Otherwise, the behavior is undefined. The.shape qualifier and the.num qualifier together determines the total dimension of the data which is stored to the Tensor Memory. The.shape qualifier indicates the base dimension of data to be accessed as described in the Data Movement Shape. (see the official PTX ISA docs for the full description)

Examples

tcgen05.st.sync.aligned.16x64b.x4.b32               [taddr0], {r0,  r1,  r2,  r3};

tcgen05.st.sync.aligned.16x128b.x1.unpack::16b.b32  [taddr1], {r0,  r1};

Reproduced from NVIDIA's official PTX ISA documentation for technical accuracy.

Sources