tcgen05.dealloc GPU Virtual ISA NVIDIA

tcgen05.dealloc Tensor Memory Allocation and Management Instructions

tcgen05.dealloc.cta_group.sync.aligned.b32 taddr, nCols;

tcgen05.dealloc is a blocking instruction which de-allocates the Tensor Memory specified by the Tensor Memory address taddr. The operand nCols specifies the number of columns to be de-allocated.

Encoding

PTX is a virtual instruction set. It has no single, stable native binary encoding - the compiler lowers this instruction to different native machine code depending on the selected NVIDIA target architecture (compute capability). This page intentionally shows no bit-diagram; see the target/version requirements below for what governs how this instruction compiles.
PTX ISA Version Introduced PTX ISA 8.6
Minimum Target sm_100a

Syntax Forms

One mnemonic covers many type / state-space / scope / modifier combinations - each row below is an independently valid form.

Syntax Data Types State Space(s) Modifiers Min. Target Description
tcgen05.dealloc.cta_group.sync.aligned.b32 taddr, nCols; sm_100a tcgen05.dealloc is a blocking instruction which de-allocates the Tensor Memory specified by the Tensor Memory address taddr. The operand nCols specifies the number of columns to be de-allocated.

Operands

At a Glance

Data Types -

Related

More in Tensor Memory Allocation and Management Instructions

Reference

NVIDIA PTX ISA

Examples

// de-allocate the columns previously allocated at taddr:
tcgen05.dealloc.cta_group::1.sync.aligned.b32  taddr, 32;

Reproduced from NVIDIA's official PTX ISA documentation for technical accuracy.

Sources