Zba Instructions
4 RISC-V instructions in this extension - click any row for encoding, pseudocode, and full documentation.
| Mnemonic | Syntax | Format | Summary |
|---|---|---|---|
| ADD.UW | ADD.UW rd, rs1, rs2 | R-Type | Zero-extends the lower 32 bits of rs1 and adds it to rs2. Useful for 64-bit address calculations with 32-bit unsigned indices. |
| SH1ADD | SH1ADD rd, rs1, rs2 | R-Type | Shifts rs1 left by 1 and adds rs2. Used for calculating addresses of 16-bit elements. |
| SH2ADD | SH2ADD rd, rs1, rs2 | R-Type | Shifts rs1 left by 2 and adds rs2. Used for calculating addresses of 32-bit elements. |
| SH3ADD | SH3ADD rd, rs1, rs2 | R-Type | Shifts rs1 left by 3 and adds rs2. Used for calculating addresses of 64-bit elements. |