Mnemonic	Syntax	Format	Summary
add	add RT, RA, RB	XO-form	Adds the contents of two registers.
addc	addc RT, RA, RB	XO-form	Adds two registers and updates the Carry Architecture (CA) bit.
adde	adde RT, RA, RB	XO-form	Adds two registers plus the current Carry bit.
addi	addi RT, RA, SI	D-form	Adds a 16-bit signed immediate value to a register.
addic	addic RT, RA, SI	D-form	Adds an immediate to a register and updates the Carry bit.
addic.	addic. RT, RA, SI	D-form	Adds an immediate, updates Carry, and updates Condition Register Field 0 (CR0).
addis	addis RT, RA, SI	D-form	Adds a 16-bit immediate shifted left by 16 bits to a register.
addme	addme RT, RA	XO-form	Adds a register, -1, and the Carry bit.
addze	addze RT, RA	XO-form	Adds a register, 0, and the Carry bit.
and	and RA, RS, RB	X-form	Performs a bitwise AND between two registers.
andc	andc RA, RS, RB	X-form	Performs a bitwise AND between RS and the one's complement of RB.
andi.	andi. RA, RS, UI	D-form	Performs a bitwise AND between a register and a 16-bit unsigned immediate (zero-extended). Always updates CR0.
andis.	andis. RA, RS, UI	D-form	Performs a bitwise AND between a register and a 16-bit immediate shifted left by 16 bits. Always updates CR0.
attn	attn	X-form	Stops execution and alerts the hardware debugger.
b	b target_addr	I-form	Unconditionally branches to a target address relative to the current instruction pointer.
ba	ba target_addr	I-form	Unconditionally branches to an absolute address.
bc	bc BO, BI, target_addr	B-form	Branches conditionally based on the Count Register (CTR) and/or a bit in the Condition Register (CR).
bcctr	bcctr BO, BI	XL-form	Branches to the address in the Count Register (CTR) if the condition is met. Used for computed jumps and switch statements.
bcdcfn.	bcdcfn. vD, vB, PS	VX-form	Converts BCD National format to Signed Packed BCD.
bcdcfsq.	bcdcfsq. vD, vB, PS	VX-form	Converts a 128-bit signed integer to BCD.
bcdcfz.	bcdcfz. vD, vB, PS	VX-form	Converts BCD Zoned format to Signed Packed BCD.
bcdctn.	bcdctn. vD, vB	VX-form	Converts Signed Packed BCD to National format.
bcdctsq.	bcdctsq. vD, vB	VX-form	Converts BCD to a 128-bit signed integer.
bcdctz.	bcdctz. vD, vB, PS	VX-form	Converts Signed Packed BCD to Zoned format.
bclr	bclr BO, BI	XL-form	Branches to the address in the Link Register (LR) if the condition is met. Used for function returns.
bctar	bctar BO, BI, BH	XL-form	Branches to the address in the TAR. Used for fast indirect jumps (JIT).
bl	bl target_addr	I-form	Branches to a target address and saves the return address (CIA + 4) in the Link Register (LR). Used for function calls.
bpermd	bpermd RA, RS, RB	X-form	Permutes bits from RS based on the index values in RB. Highly optimized for bit shuffling.
cfuged	cfuged RA, RS, RB	X-form	Separates bits of the source register into two groups based on a mask (Power10 Scalar).
clrbhrb	clrbhrb	X-form	Clears the hardware branch history buffer (Performance tuning).
cmp	cmp BF, L, RA, RB	X-form	Compares two registers as signed integers and records the result in the specified Condition Register Field.
cmpb	cmpb RA, RS, RB	X-form	Compares bytes in two GPRs, result is byte mask.
cmpeqb	cmpeqb RA, RS, RB	X-form	Compares bytes in two GPRs for equality (Scalar).
cmpi	cmpi BF, L, RA, SI	D-form	Compares a register to a 16-bit signed immediate.
cmpl	cmpl BF, L, RA, RB	X-form	Compares two registers as unsigned integers.
cmpli	cmpli BF, L, RA, UI	D-form	Compares a register to a 16-bit unsigned immediate.
cmprb	cmprb BF, L, RA, RB	X-form	Compares a byte against a range of values. (Is byte in [min, max]?)
cntlzd	cntlzd RA, RS	X-form	Counts the number of consecutive 0 bits starting from bit 0 (MSB of 64-bit reg).
cntlzdm	cntlzdm RA, RS, RB	X-form	Counts leading zeros in RS, but only considering bits set in mask RB.
cntlzw	cntlzw RA, RS	X-form	Counts the number of consecutive 0 bits starting from bit 32 (MSB of the low word).
cnttzd	cnttzd RA, RS	X-form	Counts the number of trailing zeros in 64-bits.
cnttzdm	cnttzdm RA, RS, RB	X-form	Counts trailing zeros in RS, but only considering bits set in mask RB.
cnttzw	cnttzw RA, RS	X-form	Counts the number of trailing zeros in the low 32-bits.
copy	copy RA, RB	X-form	Initiates a hardware copy (accelerator) operation.
cp_abort	cp_abort	X-form	Aborts a hardware accelerator copy-paste sequence.
crand	crand BT, BA, BB	XL-form	Performs a bitwise AND between two bits in the Condition Register.
crc32b	crc32b RA, RS	X-form	Accumulates a CRC32 checksum using the low byte of RS.
crc32d	crc32d RA, RS	X-form	Accumulates a CRC32 checksum using the doubleword in RS.
crc32h	crc32h RA, RS	X-form	Accumulates a CRC32 checksum using the low halfword of RS.
crc32w	crc32w RA, RS	X-form	Accumulates a CRC32 checksum using the word in RS.
cror	cror BT, BA, BB	XL-form	Performs a bitwise OR between two bits in the Condition Register.
crxor	crxor BT, BA, BB	XL-form	Performs a bitwise XOR between two bits in the Condition Register. Used to clear CR bits (crxor x,x,x).
dadd	dadd FRT, FRA, FRB	X-form	Adds two 64-bit Decimal Floating Point (DFP) numbers. Used in financial calculations to avoid rounding errors.
daddq	daddq vD, vA, vB	X-form	Adds two 128-bit DFP numbers.
darn	darn RT, L	X-form	Returns a random number from the hardware RNG. (L=3: Raw, L=1: Conditioned, L=0: 32-bit).
dcba	dcba RA, RB	X-form	Allocates a cache block without loading from memory (optimization for overwrite).
dcbf	dcbf RA, RB	X-form	Flushes the cache block from the data cache to main memory and invalidates it. Used for DMA coherency.
dcbi	dcbi RA, RB	X-form	Invalidates a cache block (Privileged).
dcblc	dcblc CT, RA, RB	X-form	Clears a cache line lock.
dcbst	dcbst RA, RB	X-form	Writes the cache block to main memory if it is modified (Clean), but keeps it in the cache.
dcbt	dcbt TH, RA, RB	X-form	Hints to the hardware to prefetch the cache block at the specified address into the cache.
dcbtls	dcbtls CT, RA, RB	X-form	Locks a cache line in the L1 cache.
dcbtst	dcbtst TH, RA, RB	X-form	Prefetches a cache block signaling intent to modify (RFO - Read For Ownership).
dcbtst	dcbtst CT, RA, RB	X-form	Prefetches a cache block for writing (RFO).
dcbz	dcbz RA, RB	X-form	Zeros out an entire cache block (usually 128 bytes) in memory. Critical for optimizing memory clears (memset).
dcbzl	dcbzl RA, RB	X-form	Zeros a cache block (implementation defined size).
dccci	dccci RA, RB	X-form	Invalidates a congruence class in the data cache (Embedded).
dcffix	dcffix FRT, FRB	X-form	Converts a 64-bit integer to DFP.
dcffixq	dcffixq vD, vB	X-form	Converts 64-bit integer to 128-bit DFP.
dcmpo	dcmpo BF, FRA, FRB	X-form	Compares two DFP numbers (Signaling on NaN).
dcmpoq	dcmpoq BF, vA, vB	X-form	Compares two 128-bit DFP numbers (Signaling).
dcmpu	dcmpu BF, FRA, FRB	X-form	Compares two DFP numbers (Non-signaling on NaN).
dcmpuq	dcmpuq BF, vA, vB	X-form	Compares two 128-bit DFP numbers (Non-signaling).
dcread	dcread RT, RA, RB	X-form	Reads a data cache tag or data (Debug).
dctdp	dctdp FRT, FRB	X-form	Converts DFP Short (32-bit compressed) to DFP Long (64-bit).
dctfix	dctfix FRT, FRB	X-form	Converts DFP to a 64-bit integer.
dctfixq	dctfixq vD, vB	X-form	Converts 128-bit DFP to 64-bit integer.
dctqpq	dctqpq vD, FRB	X-form	Converts DFP Long (64-bit) to DFP Quad (128-bit).
ddedpd	ddedpd FRT, FRB, SP	X-form	Decodes BCD to DFP format.
ddedpdq	ddedpdq vD, vB, SP	X-form	Decodes BCD to 128-bit DFP.
ddiv	ddiv FRT, FRA, FRB	X-form	Divides two 64-bit Decimal Floating Point numbers.
ddivq	ddivq vD, vA, vB	X-form	Divides two 128-bit DFP numbers.
denbcd	denbcd FRT, FRB, S	X-form	Encodes a DFP number into BCD format.
denbcdq	denbcdq vD, vB, S	X-form	Encodes 128-bit DFP to BCD.
diex	diex FRT, FRA, FRB	X-form	Combines a sign/coefficient from FRA and exponent from FRB.
diexq	diexq vD, vA, vB	X-form	Inserts exponent into 128-bit DFP.
divd	divd RT, RA, RB	XO-form	Divides the 64-bit value in RA by the 64-bit value in RB (Signed).
divde	divde RT, RA, RB	XO-form	64-bit extended division.
divdeu	divdeu RT, RA, RB	XO-form	64-bit extended unsigned division.
divdu	divdu RT, RA, RB	XO-form	Divides the 64-bit value in RA by the 64-bit value in RB (Unsigned).
divsq	divsq vD, vA, vB	VX-form	Divides a 128-bit signed integer by a 128-bit signed integer (using VSX pairs).
divuq	divuq vD, vA, vB	VX-form	Divides a 128-bit unsigned integer by a 128-bit unsigned integer.
divw	divw RT, RA, RB	XO-form	Divides the lower 32 bits of RA by the lower 32 bits of RB (Signed).
divwe	divwe RT, RA, RB	XO-form	32-bit extended division.
divweu	divweu RT, RA, RB	XO-form	32-bit extended unsigned division.
divwu	divwu RT, RA, RB	XO-form	Divides the lower 32 bits of RA by the lower 32 bits of RB (Unsigned).
dmul	dmul FRT, FRA, FRB	X-form	Multiplies two 64-bit Decimal Floating Point numbers.
dmulq	dmulq vD, vA, vB	X-form	Multiplies two 128-bit DFP numbers.
doze	doze	X-form	Enters Doze power-saving mode (Supervisor only).
dqua	dqua FRT, FRA, FRB	X-form	Adjusts the exponent of a DFP number to match a reference. Critical for aligning decimal points before addition.
dquaq	dquaq vD, vA, vB	X-form	Adjusts exponent of 128-bit DFP number.
drdpq	drdpq FRT, vB	X-form	Rounds DFP Quad (128-bit) to DFP Long (64-bit).
drrndq	drrndq vD, vA, vB	X-form	Rerounds a 128-bit DFP number to fewer digits.
drsp	drsp FRT, FRB	X-form	Rounds DFP Long (64-bit) to DFP Short (32-bit compressed).
dscli	dscli FRT, FRA, SH	Z23-form	Shifts the coefficient of a DFP number left.
dsri	dsri FRT, FRA, SH	Z23-form	Shifts the coefficient of a DFP number right.
dss	dss STRM	X-form	Stops a data stream prefetch operation.
dssall	dssall	X-form	Stops all active data stream prefetch operations.
dst	dst RA, RB, STRM	X-form	Initiates a hardware data stream prefetch (AltiVec Legacy).
dstst	dstst RA, RB, STRM	X-form	Initiates a prefetch for writing.
dststt	dststt RA, RB, STRM	X-form	Initiates a transient prefetch for writing.
dstt	dstt RA, RB, STRM	X-form	Initiates a transient (non-temporal) data stream prefetch.
dsub	dsub FRT, FRA, FRB	X-form	Subtracts two 64-bit Decimal Floating Point numbers.
dsubq	dsubq vD, vA, vB	X-form	Subtracts two 128-bit DFP numbers.
dtstsfi	dtstsfi BF, U, FRB	X-form	Tests DFP significance (number of digits).
dtstsfiq	dtstsfiq BF, U, FRB	X-form	Tests DFP Quad significance.
dxex	dxex FRT, FRB	X-form	Extracts the exponent from a DFP number.
dxexq	dxexq vD, vB	X-form	Extracts exponent from 128-bit DFP.
e_add	e_add RT, RA, RB	E-form	Adds two registers. (RT = RA + RB)
e_add16i	e_add16i RT, RA, SI	E-form	Adds 16-bit immediate.
e_add16is	e_add16is RT, RA, SI	E-form	Adds a 16-bit immediate shifted left by 16 bits.
e_addc	e_addc RT, RA, RB	E-form	Adds two registers and updates Carry (CA).
e_adde	e_adde RT, RA, RB	E-form	Adds two registers and the Carry bit.
e_addi	e_addi RT, RA, SI	E-form	Adds immediate to register.
e_addme	e_addme RT, RA	E-form	Adds register to -1 with Carry.
e_addze	e_addze RT, RA	E-form	Adds register to 0 with Carry.
e_and	e_and RT, RA, RB	E-form	Bitwise AND.
e_and2i	e_and2i RT, UI	E-form	AND with 16-bit immediate.
e_and2is	e_and2is RT, UI	E-form	AND with 16-bit immediate shifted left by 16 bits.
e_andc	e_andc RT, RA, RB	E-form	RT = RA & ~RB.
e_b	e_b BD24	E-form	Unconditional branch (long range).
e_bc	e_bc BO, BI, BD15	E-form	Conditional branch.
e_bdnz	e_bdnz BD	E-form	Decrements CTR, branches if CTR != 0.
e_bdnzf	e_bdnzf BI, BD	E-form	Decrements CTR, branches if CTR != 0 AND CR bit is false.
e_bdnzt	e_bdnzt BI, BD	E-form	Decrements CTR, branches if CTR != 0 AND CR bit is true.
e_bdz	e_bdz BD	E-form	Decrements CTR, branches if CTR == 0.
e_bdzf	e_bdzf BI, BD	E-form	Decrements CTR, branches if CTR == 0 AND CR bit is false.
e_bdzt	e_bdzt BI, BD	E-form	Decrements CTR, branches if CTR == 0 AND CR bit is true.
e_bl	e_bl BD24	E-form	Function call (long range).
e_cmp	e_cmp BF, RA, RB	E-form	Signed comparison.
e_cmp16i	e_cmp16i BF, RA, SI	E-form	Compares word with 16-bit immediate.
e_cmph	e_cmph BF, RA, RB	E-form	Compares 16-bit values.
e_cmph16i	e_cmph16i BF, RA, SI	E-form	Compare halfword with immediate.
e_cmphl	e_cmphl BF, RA, RB	E-form	Unsigned compare 16-bit values.
e_cmphl16i	e_cmphl16i BF, RA, UI	E-form	Unsigned compare halfword with immediate.
e_cmpi	e_cmpi BF, RA, SI	E-form	Compare with immediate.
e_cmpl	e_cmpl BF, RA, RB	E-form	Unsigned comparison.
e_cmpl16i	e_cmpl16i BF, RA, UI	E-form	Unsigned compare word with 16-bit immediate.
e_cmpli	e_cmpli BF, RA, UI	E-form	Unsigned compare with immediate.
e_cntlzw	e_cntlzw RT, RA	E-form	Counts leading zeros.
e_crand	e_crand BT, BA, BB	E-form	CR bit logical AND.
e_crandc	e_crandc BT, BA, BB	E-form	CR bit logical AND with complement (BT = BA & ~BB).
e_creqv	e_creqv BT, BA, BB	E-form	CR bit logical XNOR.
e_crnand	e_crnand BT, BA, BB	E-form	CR bit logical NAND.
e_crnor	e_crnor BT, BA, BB	E-form	CR bit logical NOR.
e_cror	e_cror BT, BA, BB	E-form	CR bit logical OR.
e_crorc	e_crorc BT, BA, BB	E-form	CR bit logical OR with complement (BT = BA | ~BB).
e_crxor	e_crxor BT, BA, BB	E-form	CR bit logical XOR.
e_dcbf	e_dcbf RA, RB	E-form	Flushes a data cache block.
e_dcbst	e_dcbst RA, RB	E-form	Stores a data cache block.
e_dcbt	e_dcbt RA, RB	E-form	Prefetches a data cache block.
e_dcbtst	e_dcbtst RA, RB	E-form	Prefetches a data cache block for writing.
e_dcbz	e_dcbz RA, RB	E-form	Zeros a data cache block.
e_divw	e_divw RT, RA, RB	E-form	Divides two words.
e_divwu	e_divwu RT, RA, RB	E-form	Unsigned division.
e_eqv	e_eqv RT, RA, RB	E-form	Bitwise XNOR.
e_extsb	e_extsb RT, RA	E-form	Sign extends low byte.
e_extsh	e_extsh RT, RA	E-form	Sign extends low halfword.
e_icbi	e_icbi RA, RB	E-form	Invalidates an instruction cache block.
e_icbt	e_icbt RA, RB	E-form	Prefetches an instruction cache block.
e_isync	e_isync	E-form	Waits for previous instructions to complete.
e_lbz	e_lbz RT, D(RA)	E-form	Loads byte with 16-bit offset.
e_lbzu	e_lbzu RT, D(RA)	E-form	Loads byte and updates base register.
e_lhz	e_lhz RT, D(RA)	E-form	Loads halfword with 16-bit offset.
e_lhzu	e_lhzu RT, D(RA)	E-form	Loads halfword and updates base register.
e_lis	e_lis RT, SI	E-form	Loads immediate into upper 16 bits.
e_lmv	e_lmv D(RA)	E-form	Loads volatile registers (R0, R3-R12) from memory.
e_lmvcsrrw	e_lmvcsrrw D(RA)	E-form	Loads volatile Critical SRRs (CSRR0, CSRR1) from memory.
e_lmvdsrrw	e_lmvdsrrw D(RA)	E-form	Loads volatile Debug SRRs (DSRR0, DSRR1) from memory.
e_lmvgprw	e_lmvgprw D(RA)	E-form	Loads volatile GPRs from memory (Word aligned).
e_lmvsprw	e_lmvsprw D(RA)	E-form	Loads volatile SPRs (CR, LR, CTR, XER) from memory.
e_lmvsrrw	e_lmvsrrw D(RA)	E-form	Loads volatile Save/Restore Registers (SRR0, SRR1) from memory.
e_lmw	e_lmw RT, D(RA)	E-form	Loads words from memory into registers RT through R31.
e_lwz	e_lwz RT, D(RA)	E-form	Loads word with 16-bit offset.
e_lwzu	e_lwzu RT, D(RA)	E-form	Loads word and updates base register.
e_mbar	e_mbar MO	E-form	Ensures memory access ordering.
e_mcrf	e_mcrf BF, BFA	E-form	Copies one CR field to another.
e_mfspr	e_mfspr RT, SPR	E-form	Reads an SPR.
e_msync	e_msync	E-form	Synchronizes memory accesses.
e_mtspr	e_mtspr SPR, RS	E-form	Writes an SPR.
e_mulhw	e_mulhw RT, RA, RB	E-form	Multiplies two words, keeps high 32 bits (Signed).
e_mulhwu	e_mulhwu RT, RA, RB	E-form	Multiplies two words, keeps high 32 bits (Unsigned).
e_mull2i	e_mull2i RT, RA, SI	E-form	Multiplies register by immediate.
e_mullw	e_mullw RT, RA, RB	E-form	Multiplies two words.
e_nand	e_nand RT, RA, RB	E-form	Bitwise NAND.
e_neg	e_neg RT, RA	E-form	Negates a register (RT = -RA).
e_nor	e_nor RT, RA, RB	E-form	Bitwise NOR.
e_or	e_or RT, RA, RB	E-form	Bitwise OR.
e_or2i	e_or2i RT, UI	E-form	OR with 16-bit immediate.
e_or2is	e_or2is RT, UI	E-form	OR with 16-bit immediate shifted left by 16 bits.
e_orc	e_orc RT, RA, RB	E-form	RT = RA | ~RB.
e_rlw	e_rlw RA, RS, RB	E-form	Rotates word left.
e_rlwimi	e_rlwimi RA, RS, SH, MB, ME	E-form	Rotate and insert (Masking).
e_rlwinm	e_rlwinm RA, RS, SH, MB, ME	E-form	Rotate and mask.
e_sc	e_sc	E-form	System call (32-bit encoding).
e_slw	e_slw RA, RS, RB	E-form	Shifts word left.
e_slw	e_slw RA, RS, RB	E-form	Shifts word left.
e_sraw	e_sraw RA, RS, RB	E-form	Arithmetic right shift.
e_sraw	e_sraw RA, RS, RB	E-form	Arithmetic right shift.
e_srawi	e_srawi RA, RS, SH	E-form	Arithmetic right shift by immediate.
e_srw	e_srw RA, RS, RB	E-form	Shifts word right.
e_srw	e_srw RA, RS, RB	E-form	Shifts word right.
e_stb	e_stb RS, D(RA)	E-form	Stores byte with 16-bit offset.
e_stbu	e_stbu RS, D(RA)	E-form	Stores byte and updates base register.
e_sth	e_sth RS, D(RA)	E-form	Stores halfword with 16-bit offset.
e_sthu	e_sthu RS, D(RA)	E-form	Stores halfword and updates base register.
e_stmv	e_stmv D(RA)	E-form	Stores volatile registers (R0, R3-R12) to memory.
e_stmvcsrrw	e_stmvcsrrw D(RA)	E-form	Stores volatile Critical SRRs (CSRR0, CSRR1) to memory.
e_stmvdsrrw	e_stmvdsrrw D(RA)	E-form	Stores volatile Debug SRRs (DSRR0, DSRR1) to memory.
e_stmvgprw	e_stmvgprw D(RA)	E-form	Stores volatile GPRs to memory (Word aligned).
e_stmvsprw	e_stmvsprw D(RA)	E-form	Stores volatile SPRs (CR, LR, CTR, XER) to memory.
e_stmvsrrw	e_stmvsrrw D(RA)	E-form	Stores volatile Save/Restore Registers (SRR0, SRR1) to memory.
e_stmw	e_stmw RT, D(RA)	E-form	Stores words from registers RT through R31 to memory.
e_stmw	e_stmw RS, D(RA)	E-form	Stores words from registers RT through R31 to memory.
e_stw	e_stw RS, D(RA)	E-form	Stores word with 16-bit offset.
e_stwu	e_stwu RS, D(RA)	E-form	Stores word and updates base register.
e_subf	e_subf RT, RA, RB	E-form	Subtracts RA from RB (RT = RB - RA).
e_subfc	e_subfc RT, RA, RB	E-form	Subtracts RA from RB and updates Carry.
e_subfe	e_subfe RT, RA, RB	E-form	Subtracts RA from RB with Carry.
e_subfic	e_subfic RT, RA, SI	E-form	Subtracts register from immediate.
e_subfme	e_subfme RT, RA	E-form	Subtracts register from -1 with Carry.
e_subfze	e_subfze RT, RA	E-form	Subtracts register from 0 with Carry.
e_tlbivax	e_tlbivax RA, RB	E-form	Invalidates a TLB entry by address.
e_tlbre	e_tlbre	E-form	Reads a TLB entry.
e_tlbsx	e_tlbsx RA, RB	E-form	Searches for a TLB entry.
e_tlbwe	e_tlbwe	E-form	Writes a TLB entry.
e_trap	e_trap	E-form	Unconditional trap (32-bit).
e_wait	e_wait	E-form	Waits for an interrupt.
e_xor	e_xor RT, RA, RB	E-form	Bitwise XOR.
e_xor2i	e_xor2i RT, UI	E-form	XOR with 16-bit immediate.
e_xor2is	e_xor2is RT, UI	E-form	XOR with 16-bit immediate shifted left by 16 bits.
eciwx	eciwx RT, RA, RB	X-form	Loads a word from an external device using the EAR register.
ecowx	ecowx RS, RA, RB	X-form	Stores a word to an external device using the EAR register.
efdabs	efdabs RT, RA	SPE-form	Double precision absolute value.
efdadd	efdadd RT, RA, RB	SPE-form	Double precision add (SPE Float).
efdcfs	efdcfs RT, RB	SPE-form	Converts single-precision to double-precision.
efdcmpeq	efdcmpeq BF, RA, RB	SPE-form	Double precision compare equal.
efdcmpgt	efdcmpgt BF, RA, RB	SPE-form	Double precision compare greater than.
efdcmplt	efdcmplt BF, RA, RB	SPE-form	Double precision compare less than.
efddiv	efddiv RT, RA, RB	SPE-form	Double precision divide (SPE Float).
efdmul	efdmul RT, RA, RB	SPE-form	Double precision multiply (SPE Float).
efdneg	efdneg RT, RA	SPE-form	Double precision negate.
efdsub	efdsub RT, RA, RB	SPE-form	Double precision subtract (SPE Float).
efdtsteq	efdtsteq BF, RA, RB	SPE-form	Tests if two double-precision floats are equal.
efdtstgt	efdtstgt BF, RA, RB	SPE-form	Tests if double-precision A > B.
efdtstlt	efdtstlt BF, RA, RB	SPE-form	Tests if double-precision A < B.
efsabs	efsabs RT, RA	SPE-form	Single precision absolute value.
efsadd	efsadd RT, RA, RB	SPE-form	Single precision add (SPE Float).
efscfd	efscfd RT, RB	SPE-form	Converts double-precision to single-precision.
efscfsf	efscfsf RT, RB	SPE-form	Converts 32-bit signed fractional to float.
efscfsi	efscfsi RT, RB	SPE-form	Converts vector of signed integers to floats.
efscfsi	efscfsi RT, RB	SPE-form	Converts signed 32-bit integer to single-precision float.
efscfuf	efscfuf RT, RB	SPE-form	Converts 32-bit unsigned fractional to float.
efscfui	efscfui RT, RB	SPE-form	Converts unsigned 32-bit integer to single-precision float.
efscmpeq	efscmpeq BF, RA, RB	SPE-form	Single precision compare equal.
efscmpgt	efscmpgt BF, RA, RB	SPE-form	Single precision compare greater than.
efscmplt	efscmplt BF, RA, RB	SPE-form	Single precision compare less than.
efsctsi	evfsctsi RT, RB	SPE-form	Converts vector of floats to signed integers.
efsctsi	efsctsi RT, RB	SPE-form	Converts single-precision float to signed 32-bit integer.
efsctsiz	efsctsiz RT, RB	SPE-form	Converts float to integer (Truncate).
efsctui	efsctui RT, RB	SPE-form	Converts single-precision float to unsigned 32-bit integer.
efsctuiz	efsctuiz RT, RB	SPE-form	Converts float to unsigned integer (Truncate).
efsdiv	efsdiv RT, RA, RB	SPE-form	Single precision divide (SPE Float).
efsmul	efsmul RT, RA, RB	SPE-form	Single precision multiply (SPE Float).
efsneg	efsneg RT, RA	SPE-form	Single precision negate.
efssub	efssub RT, RA, RB	SPE-form	Single precision subtract (SPE Float).
efststeq	efststeq BF, RA, RB	SPE-form	Tests if two single-precision floats are equal, setting CR field.
efststgt	efststgt BF, RA, RB	SPE-form	Tests if single-precision A > B.
efststlt	efststlt BF, RA, RB	SPE-form	Tests if single-precision A < B.
ehpriv	ehpriv OC	X-form	Enters embedded hypervisor privileged state.
eieio	eieio	X-form	Ensures that load/store instructions preceding the EIEIO complete before those following it. Used for Memory-Mapped I/O synchronization.
eqv	eqv RA, RS, RB	X-form	Performs a bitwise Equivalence (XNOR) operation. (RA = ~(RS ^ RB)).
evabs	evabs RT, RA	SPE-form	Computes absolute value of words in a 64-bit vector.
evaddw	evaddw RT, RA, RB	SPE-form	Adds two 64-bit vectors of two 32-bit words.
evand	evand RT, RA, RB	SPE-form	Bitwise AND of two 64-bit vectors.
evandc	evandc RT, RA, RB	SPE-form	RT = RA & ~RB.
evcmpeq	evcmpeq BF, RA, RB	SPE-form	Compares two vectors for equality, setting CR field.
evcmpgts	evcmpgts BF, RA, RB	SPE-form	Compares vectors (signed A > B).
evcmpgtu	evcmpgtu BF, RA, RB	SPE-form	Compares vectors (unsigned A > B).
evcmplts	evcmplts BF, RA, RB	SPE-form	Compares vectors (signed A < B).
evcmpltu	evcmpltu BF, RA, RB	SPE-form	Compares vectors (unsigned A < B).
evcntlsw	evcntlsw RT, RA	SPE-form	Counts leading sign bits in each word.
evcntlzw	evcntlzw RT, RA	SPE-form	Counts leading zeros in each word.
eveqv	eveqv RT, RA, RB	SPE-form	Bitwise Equivalence (XNOR).
evextsb	evextsb RT, RA	SPE-form	Sign extends the low byte of each word to 32 bits.
evextsh	evextsh RT, RA	SPE-form	Sign extends the low halfword of each word to 32 bits.
evfsabs	evfsabs RT, RA	SPE-form	Computes absolute value of floats in vector.
evfsadd	evfsadd RT, RA, RB	SPE-form	Adds two vectors of single-precision floats.
evfscfsi	evfscfsi RT, RB	SPE-form	Converts vector of signed integers to floats.
evfsctsi	evfsctsi RT, RB	SPE-form	Converts vector of floats to signed integers.
evfsdiv	evfsdiv RT, RA, RB	SPE-form	Divides two vectors of single-precision floats.
evfsmul	evfsmul RT, RA, RB	SPE-form	Multiplies two vectors of single-precision floats.
evfsneg	evfsneg RT, RA	SPE-form	Negates floats in vector.
evfssub	evfssub RT, RA, RB	SPE-form	Subtracts two vectors of single-precision floats.
evldd	evldd RT, D(RA)	SPE-form	Loads 64 bits from memory into a vector GPR.
evldh	evldh RT, D(RA)	SPE-form	Loads 4 halfwords from memory into a vector.
evldw	evldw RT, D(RA)	SPE-form	Loads two words from memory (aligned) into a vector.
evlhhesplat	evlhhesplat RT, D(RA)	SPE-form	Loads a halfword and duplicates it into the even halfwords of the target.
evlhhossplat	evlhhossplat RT, D(RA)	SPE-form	Loads a halfword and duplicates it into the odd halfwords (sign extended).
evlhhousplat	evlhhousplat RT, D(RA)	SPE-form	Loads a halfword and duplicates it into the odd halfwords (zero extended).
evlwhe	evlwhe RT, D(RA)	SPE-form	Loads two words and places them in the even halfword positions.
evlwhos	evlwhos RT, D(RA)	SPE-form	Loads words into odd positions (sign extended).
evlwhou	evlwhou RT, D(RA)	SPE-form	Loads words into odd positions (zero extended).
evmhegsmfaa	evmhegsmfaa RT, RA, RB	SPE-form	Fractional multiply accumulate (DSP).
evmhegsmfan	evmhegsmfan RT, RA, RB	SPE-form	Fractional multiply negative accumulate.
evmhegum	evmhegum RT, RA, RB	SPE-form	Unsigned multiply.
evmhesmia	evmhesmia RT, RA, RB	SPE-form	Integer multiply accumulate.
evmhesmian	evmhesmian RT, RA, RB	SPE-form	Integer multiply negative accumulate.
evmheumia	evmheumia RT, RA, RB	SPE-form	Unsigned multiply accumulate.
evmheumian	evmheumian RT, RA, RB	SPE-form	Unsigned multiply negative accumulate.
evmhosm	evmhosm RT, RA, RB	SPE-form	Signed modulo multiply.
evmhosmi	evmhosmi RT, RA, RB	SPE-form	Signed integer modulo multiply.
evmhossf	evmhossf RT, RA, RB	SPE-form	Saturating fractional multiply.
evmhossfa	evmhossfa RT, RA, RB	SPE-form	Saturating fractional multiply accumulate.
evmhoumi	evmhoumi RT, RA, RB	SPE-form	Unsigned integer modulo multiply.
evmwhsm	evmwhsm RT, RA, RB	SPE-form	Multiplies high 16-bits of words.
evmwhsmi	evmwhsmi RT, RA, RB	SPE-form	Multiplies high 16-bits of words (integer).
evmwhssf	evmwhssf RT, RA, RB	SPE-form	Fractional multiply of high words.
evmwhssfa	evmwhssfa RT, RA, RB	SPE-form	Fractional multiply accumulate of high words.
evmwlumi	evmwlumi RT, RA, RB	SPE-form	Multiplies low 16-bits of words.
evmwlumia	evmwlumia RT, RA, RB	SPE-form	Multiply accumulate low words.
evmwlumiaa	evmwlumiaa RT, RA, RB	SPE-form	Multiply and double accumulate low words.
evmwlusiaaw	evmwlusiaaw RT, RA, RB	SPE-form	Complex mixed-sign accumulation.
evmwsmia	evmwsmia RT, RA, RB	SPE-form	Signed integer multiply accumulate.
evmwsmiaa	evmwsmiaa RT, RA, RB	SPE-form	Signed integer multiply double accumulate.
evmwsmiaaw	evmwsmiaaw RT, RA, RB	SPE-form	Signed integer multiply accumulate word.
evmwssfaa	evmwssfaa RT, RA, RB	SPE-form	Saturating fractional multiply double accumulate.
evmwssfaaw	evmwssfaaw RT, RA, RB	SPE-form	Saturating fractional multiply accumulate word.
evmwumia	evmwumia RT, RA, RB	SPE-form	Unsigned multiply accumulate.
evmwumiaa	evmwumiaa RT, RA, RB	SPE-form	Unsigned multiply double accumulate.
evmwumiaaw	evmwumiaaw RT, RA, RB	SPE-form	Unsigned multiply accumulate word.
evnand	evnand RT, RA, RB	SPE-form	Bitwise NAND of two 64-bit vectors.
evneg	evneg RT, RA	SPE-form	Negates words in a 64-bit vector.
evnor	evnor RT, RA, RB	SPE-form	Bitwise NOR of two 64-bit vectors.
evor	evor RT, RA, RB	SPE-form	Bitwise OR of two 64-bit vectors.
evorc	evorc RT, RA, RB	SPE-form	RT = RA | ~RB.
evrlw	evrlw RT, RA, RB	SPE-form	Rotates words in RA left by amount in RB.
evrlwi	evrlwi RT, RA, UIM	SPE-form	Rotates words left by immediate value.
evrndw	evrndw RT, RA	SPE-form	Rounds words in the vector.
evsel	evsel RT, RA, RB, CR	SPE-form	Selects bits from RA or RB based on CR field.
evslw	evslw RT, RA, RB	SPE-form	Shifts words in RA left by amount in RB.
evslwi	evslwi RT, RA, UIM	SPE-form	Shifts words left by immediate value.
evsplatfi	evsplatfi RT, SIM	SPE-form	Splats a 5-bit immediate (scaled) into both words.
evsplati	evsplati RT, SIM	SPE-form	Splats a signed 5-bit immediate into both words.
evsrwis	evsrwis RT, RA, UIM	SPE-form	Arithmetic right shift by immediate.
evsrwiu	evsrwiu RT, RA, UIM	SPE-form	Logical right shift by immediate.
evsrws	evsrws RT, RA, RB	SPE-form	Arithmetic right shift of words.
evsrwu	evsrwu RT, RA, RB	SPE-form	Logical right shift of words.
evstdd	evstdd RS, D(RA)	SPE-form	Stores 64-bit vector to memory.
evstdh	evstdh RS, D(RA)	SPE-form	Stores 4 halfwords from vector to memory.
evstdw	evstdw RS, D(RA)	SPE-form	Stores two words from vector to memory.
evstwhe	evstwhe RS, D(RA)	SPE-form	Stores even halfwords to memory.
evstwho	evstwho RS, D(RA)	SPE-form	Stores odd halfwords to memory.
evstwwe	evstwwe RS, D(RA)	SPE-form	Stores the even word (upper 32-bits) to memory.
evstwwo	evstwwo RS, D(RA)	SPE-form	Stores the odd word (lower 32-bits) to memory.
evsubfsmiaaw	evsubfsmiaaw RT, RA, RB	SPE-form	Complex subtraction accumulate.
evsubfssiaaw	evsubfssiaaw RT, RA, RB	SPE-form	Complex subtraction saturate accumulate.
evsubfw	evsubfw RT, RA, RB	SPE-form	Subtracts words (Alternate syntax for evsubw).
evsubifw	evsubifw RT, UIM, RB	SPE-form	Subtracts immediate from word.
evsubw	evsubw RT, RA, RB	SPE-form	Subtracts two 64-bit vectors of two 32-bit words.
evxor	evxor RT, RA, RB	SPE-form	Bitwise XOR of two 64-bit vectors.
extsb	extsb RA, RS	X-form	Sign-extends the low byte (8 bits) of a register to 64 bits.
extsh	extsh RA, RS	X-form	Sign-extends the low halfword (16 bits) of a register to 64 bits.
extsw	extsw RA, RS	X-form	Sign-extends the low word (32 bits) of a register to 64 bits.
fabs	fabs FRT, FRB	X-form	Computes absolute value of a float.
fadd	fadd FRT, FRA, FRB	A-form	Adds two double-precision floating-point registers.
fcfid	fcfid FRT, FRB	X-form	Converts 64-bit Int to Double.
fcfids	fcfids FRT, FRB	X-form	Converts 64-bit Int to Single.
fcfidu	fcfidu FRT, FRB	X-form	Converts 64-bit Unsigned Int to Double.
fcfidus	fcfidus FRT, FRB	X-form	Converts 64-bit Unsigned Int to Single.
fcmpu	fcmpu BF, FRA, FRB	X-form	Compares two floating-point registers and sets the Condition Register (CR) field. Does not trap on NaNs.
fcpsgn	fcpsgn FRT, FRA, FRB	X-form	Copies sign from FRB to FRA.
fctid	fctid FRT, FRB	X-form	Converts Double to 64-bit Int.
fctidz	fctidz FRT, FRB	X-form	Converts Double to 64-bit Int (Truncate).
fctiw	fctiw FRT, FRB	X-form	Converts a float to a 32-bit signed integer (using the current rounding mode) and stores it in the lower half of the FPR.
fctiwz	fctiwz FRT, FRB	X-form	Converts Double to 32-bit Int (Truncate).
fmadd	fmadd FRT, FRA, FRC, FRB	A-form	A*C + B
fmr	fmr FRT, FRB	X-form	Copies a float register (Pseudo: for FRB).
fmsub	fmsub FRT, FRA, FRC, FRB	A-form	A*C - B
fmul	fmul FRT, FRA, FRC	A-form	Multiplies two double-precision floating-point registers.
fnabs	fnabs FRT, FRB	X-form	Computes negative absolute value of a float.
fneg	fneg FRT, FRB	X-form	Negates a float.
fnmadd	fnmadd FRT, FRA, FRC, FRB	A-form	-(A*C + B)
fnmsub	fnmsub FRT, FRA, FRC, FRB	A-form	-(A*C - B)
fre	fre FRT, FRB	A-form	Estimates 1/x (Double Precision).
fres	fres FRT, FRB	A-form	Estimates 1/x (Single Precision).
frsp	frsp FRT, FRB	X-form	Rounds Double to Single.
frsqrte	frsqrte FRT, FRB	A-form	Estimates 1/sqrt(x) (Double Precision).
frsqrtes	frsqrtes FRT, FRB	A-form	Estimates 1/sqrt(x) (Single Precision).
fsel	fsel FRT, FRA, FRC, FRB	A-form	Selects FRA if FRC >= 0, else FRB (Optional).
fsqrt	fsqrt FRT, FRB	X-form	Computes square root (Double).
fsqrts	fsqrts FRT, FRB	X-form	Computes square root (Single).
ftdiv	ftdiv BF, FRA, FRB	X-form	Tests for conditions that would cause a divide exception.
ftsqrt	ftsqrt BF, FRB	X-form	Tests for conditions that would cause a sqrt exception.
hashchk	hashchk RA	X-form	Checks the hash of the Return Address Stack (ROP Protection).
hashchkp	hashchkp RA	X-form	Privileged version of hash check.
hashst	hashst RA	X-form	Stores the hash of the Return Address.
hashstp	hashstp RA	X-form	Privileged version of hash store.
hrfid	hrfid	XL-form	Returns from a hypervisor interrupt.
icbi	icbi RA, RB	X-form	Invalidates the instruction cache block associated with the address. Critical for self-modifying code or JITs.
icblc	icblc CT, RA, RB	X-form	Clears an instruction cache line lock.
icbt	icbt RA, RB	X-form	Prefetches an instruction cache block.
icbt	icbt CT, RA, RB	X-form	Prefetches an instruction cache block.
icbtls	icbtls CT, RA, RB	X-form	Locks an instruction cache line.
iccci	iccci RA, RB	X-form	Invalidates a congruence class in the instruction cache (Embedded).
icread	icread RA, RB	X-form	Reads an instruction cache tag or data (Debug).
isel	isel RT, RA, RB, BC	A-form	Conditionally copies RA or RB to RT based on a CR bit. (Equivalent to C ternary operator 'cond ? a : b').
isync	isync	XL-form	Waits for previous instructions to complete.
lbarx	lbarx RT, RA, RB	X-form	Atomic Load Byte.
lbz	lbz RT, D(RA)	D-form	Loads a byte from memory into the low 8 bits of a register and clears the upper 56 bits.
lbzci	lbzci RT, RA, RB	X-form	Loads a byte bypassing the cache. Used for memory-mapped I/O.
lbzepx	lbzepx RT, RA, RB	X-form	Loads a byte using the External PID (for OS kernels accessing user memory).
ld	ld RT, DS(RA)	DS-form	Loads a doubleword (64 bits) from memory.
ldarx	ldarx RT, RA, RB	X-form	Loads a doubleword and creates a reservation. 64-bit version of lwarx.
ldbrx	ldbrx RT, RA, RB	X-form	Loads 64 bits and swaps bytes.
ldci	ldci RT, RA, RB	X-form	Loads a doubleword bypassing the cache.
lha	lha RT, D(RA)	D-form	Loads a halfword (16 bits) from memory and sign-extends it to 64 bits.
lharx	lharx RT, RA, RB	X-form	Atomic Load Halfword.
lhbrx	lhbrx RT, RA, RB	X-form	Loads a halfword and swaps bytes (Little-Endian load).
lhz	lhz RT, D(RA)	D-form	Loads a halfword (16 bits) from memory and clears the upper 48 bits.
lhzci	lhzci RT, RA, RB	X-form	Loads a halfword bypassing the cache.
lhzepx	lhzepx RT, RA, RB	X-form	Loads a halfword using the External PID.
li	li RT, SIM	D-form	Loads a 16-bit signed immediate into a register. (Alias for 'addi RT, 0, SIM').
lis	lis RT, SIM	D-form	Loads a 16-bit immediate into the upper half of a 32-bit word. (Alias for 'addis RT, 0, SIM').
lmw	lmw RT, D(RA)	D-form	Loads words from memory into registers RT through R31 (Context Switch).
lq	lq RTp, DQ(RA)	DQ-form	Loads 128 bits into two adjacent GPRs (Even/Odd pair).
lqarx	lqarx RTp, RA, RB	X-form	Atomic Load 128-bit Quadword.
lswi	lswi RT, RA, NB	X-form	Loads N bytes from memory into registers.
lswx	lswx RT, RA, RB	X-form	Loads N bytes from memory (N in XER).
lvx	lvx vD, RA, RB	X-form	Loads a 128-bit vector from memory into a Vector Register. Address must be 16-byte aligned (bits 60-63 of effective address are ignored).
lwa	lwa RT, DS(RA)	DS-form	Loads a word (32 bits) from memory and sign-extends it to 64 bits.
lwarx	lwarx RT, RA, RB	X-form	Loads a word and creates a reservation for use with 'stwcx.'. Critical for implementing atomic primitives (mutexes).
lwbrx	lwbrx RT, RA, RB	X-form	Loads a word and swaps bytes.
lwdi	lwdi RT, RA, RB	X-form	Loads a word and sends decoration sideband signals to the bus.
lwsync	lwsync	Pseudo	Orders loads with loads, stores with stores, and loads with stores. Does NOT order stores with loads. (Encoded as sync 1).
lwz	lwz RT, D(RA)	D-form	Loads a word (32 bits) from memory and clears the upper 32 bits.
lwzci	lwzci RT, RA, RB	X-form	Loads a word bypassing the cache.
lwzepx	lwzepx RT, RA, RB	X-form	Loads a word using the External PID.
lxsiwax	lxsiwax XT, RA, RB	XX1-form	Loads a 32-bit signed integer into a VSX register (scalar).
lxsiwzx	lxsiwzx XT, RA, RB	XX1-form	Loads a 32-bit unsigned integer into a VSX register (scalar).
lxv	lxv XT, DQ(RA)	DQ-form	Loads a 128-bit vector from memory (VSX aligned offset).
lxvd2x	lxvd2x XT, RA, RB	XX1-form	Loads a 128-bit vector from memory into a VSX register. Does NOT require 16-byte alignment (unlike lvx).
lxvdsx	lxvdsx XT, RA, RB	X-form	Loads a doubleword and duplicates it to fill the vector.
lxvl	lxvl XT, RA, RB	XX1-form	Loads N bytes into a vector, where N is specified in a GPR.
lxvp	lxvp XT, DQ(RA)	DQ-form	Loads a 256-bit vector pair (two VSRs).
lxvw4x	lxvw4x XT, RA, RB	XX1-form	Loads four words into a vector (unaligned).
lxvwsx	lxvwsx XT, RA, RB	XX1-form	Loads a 32-bit word and replicates it across the vector.
macchw	macchw RT, RA, RB	XO-form	Multiply bottom half of RA by top half of RB, add to RT.
macchws	macchws RT, RA, RB	XO-form	Signed Multiply Accumulate Cross Halfword with Saturation.
macchwsu	macchwsu RT, RA, RB	XO-form	Mixed Sign Multiply Accumulate Cross Halfword with Saturation.
macchwu	macchwu RT, RA, RB	XO-form	Unsigned Multiply Accumulate Cross Halfword.
machhw	machhw RT, RA, RB	XO-form	Multiply top half of RA by top half of RB, add to RT.
machhws	machhws RT, RA, RB	XO-form	Signed Multiply Accumulate High Halfword with Saturation.
machhwsu	machhwsu RT, RA, RB	XO-form	Mixed Sign Multiply Accumulate High Halfword with Saturation.
machhwu	machhwu RT, RA, RB	XO-form	Unsigned Multiply Accumulate High Halfword.
maclhw	maclhw RT, RA, RB	XO-form	Multiply bottom half of RA by bottom half of RB, add to RT.
maclhws	maclhws RT, RA, RB	XO-form	Signed Multiply Accumulate Low Halfword with Saturation.
maclhwsu	maclhwsu RT, RA, RB	XO-form	Mixed Sign Multiply Accumulate Low Halfword with Saturation.
maclhwu	maclhwu RT, RA, RB	XO-form	Unsigned Multiply Accumulate Low Halfword.
mbar	mbar MO	X-form	Ensures memory access ordering (Embedded version of 'sync').
mcrf	mcrf BF, BFA	XL-form	Copies the contents of one Condition Register field to another. Used to save comparison results.
mcrfs	mcrfs BF, BFA	X-form	Copies FPSCR exception bits to the Condition Register.
mcrxrx	mcrxrx BF	X-form	Copies XER[OV, SO] to a Condition Register field.
mfbhrbe	mfbhrbe RT, BHRBE	X-form	Reads a specific entry from the BHRB.
mfcr	mfcr RT	X-form	Copies the entire 32-bit Condition Register into a General Purpose Register.
mfctr	mfctr RT	XFX-form	Moves CTR to GPR. (Alias for 'mfspr RT, 9').
mfdcr	mfdcr RT, DCRN	XFX-form	Reads an on-chip peripheral register (DCR).
mffs	mffs FRT	X-form	Copies the Floating-Point Status and Control Register to a float register.
mflr	mflr RT	XFX-form	Moves LR to GPR. (Alias for 'mfspr RT, 8').
mfmsr	mfmsr RT	X-form	Reads the MSR (Privileged).
mfocrf	mfocrf RT, FXM	XFX-form	Moves a single CR field to a GPR.
mfpmr	mfpmr RT, PMRN	X-form	Reads a performance monitor register (Embedded).
mfpvr	mfpvr RT	X-form	Reads the PVR (Processor ID).
mfspr	mfspr RT, SPR	XFX-form	Copies a value from a system SPR to a general-purpose register.
mfsr	mfsr RT, SR	X-form	Legacy 32-bit segment register read.
mfsrin	mfsrin RT, RB	X-form	Indirect read of segment register using RB.
mftar	mftar RT	XFX-form	Reads the TAR into a GPR.
mftb	mftb RT	XFX-form	Reads the hardware timebase register (Timestamp).
mftbu	mftbu RT	XFX-form	Reads the upper 32 bits of the Timebase (32-bit implementations).
mfvsrd	mfvsrd RA, XS	XX1-form	Moves 64 bits from a VSR to a GPR.
mfvsrld	mfvsrld RA, XS	XX1-form	Extracts the lower 64-bits of a VSR to a GPR.
mfvsrwz	mfvsrwz RA, XS	XX1-form	Moves low 32 bits from VSR to GPR (zero extend).
modsd	modsd RT, RA, RB	X-form	Calculates remainder of signed doubleword division.
modsq	modsq vD, vA, vB	VX-form	Computes remainder of 128-bit signed division.
modsw	modsw RT, RA, RB	X-form	Calculates remainder of signed word division.
modud	modud RT, RA, RB	X-form	Calculates remainder of unsigned doubleword division.
moduq	moduq vD, vA, vB	VX-form	Computes remainder of 128-bit unsigned division.
moduw	moduw RT, RA, RB	X-form	Calculates remainder of unsigned word division.
mr	mr RA, RS	Pseudo	Copies the contents of one register to another. (Encoded as OR RA, RS, RS).
mr	mr RA, RS	X-form	Copies contents of RS to RA. (Alias for 'or RA, RS, RS').
msgclr	msgclr RB	X-form	Clears a pending doorbell interrupt (Inter-processor comms).
msgclrp	msgclrp RB	X-form	Clears a privileged doorbell interrupt.
msgslp	msgslp RB	X-form	Transitions the processor to a sleep state via message.
msgsnd	msgsnd RB	X-form	Sends a doorbell interrupt to another processor.
msgsndp	msgsndp RB	X-form	Sends a privileged doorbell interrupt.
msgsync	msgsync	X-form	Waits for previous messages to be accepted.
msync	msync	X-form	Synchronizes memory accesses (Alias for sync).
mtcrf	mtcrf FXM, RS	XFX-form	Copies bits from a register into the Condition Register, updated only the fields specified by the mask (FXM).
mtctr	mtctr RS	XFX-form	Moves GPR to CTR. (Alias for 'mtspr 9, RS').
mtdcr	mtdcr DCRN, RS	XFX-form	Writes an on-chip peripheral register (DCR).
mtfsb0	mtfsb0 BT	X-form	Clears a specific bit in the FPSCR.
mtfsb1	mtfsb1 BT	X-form	Sets a specific bit in the FPSCR.
mtfsf	mtfsf FLM, FRB, W, L	XFL-form	Writes fields of the FPSCR from a float register.
mtfsfi	mtfsfi BF, U	X-form	Writes a 4-bit immediate to a specific FPSCR field.
mtlr	mtlr RS	XFX-form	Moves GPR to LR. (Alias for 'mtspr 8, RS').
mtmsr	mtmsr RS, L	X-form	Writes the MSR (Privileged).
mtmsrd	mtmsrd RS, L	X-form	Writes the 64-bit MSR.
mtocrf	mtocrf FXM, RS	XFX-form	Moves a GPR field to a single CR field.
mtpmr	mtpmr PMRN, RS	X-form	Writes a performance monitor register (Embedded).
mtspr	mtspr SPR, RS	XFX-form	Copies a value from a general-purpose register to a system SPR (e.g., CTR, LR, XER).
mtsr	mtsr SR, RS	X-form	Legacy 32-bit segment register write.
mtsrin	mtsrin RS, RB	X-form	Indirect write of segment register using RB.
mttar	mttar RS	XFX-form	Moves a GPR value to the TAR.
mtvsrd	mtvsrd XT, RA	XX1-form	Moves 64 bits from a GPR to a VSR.
mtvsrdd	mtvsrdd XT, RA, RB	X-form	Moves two 64-bit GPRs into one 128-bit VSR.
mtvsrwa	mtvsrwa XT, RA	XX1-form	Moves low 32 bits from GPR to VSR (sign extend).
mtvsrws	mtvsrws XT, RA	XX1-form	Moves a 32-bit word from a GPR and replicates it across the vector.
mulchw	mulchw RT, RA, RB	XO-form	Multiply bottom half of RA by top half of RB.
mulchwu	mulchwu RT, RA, RB	XO-form	Unsigned Multiply Cross Halfword.
mulhd	mulhd RT, RA, RB	XO-form	Multiplies two 64-bit integers and returns the upper 64 bits of the 128-bit result (Signed).
mulhdu	mulhdu RT, RA, RB	XO-form	Multiplies two 64-bit integers and returns the upper 64 bits of the 128-bit result (Unsigned).
mulhhw	mulhhw RT, RA, RB	XO-form	Multiply top half of RA by top half of RB.
mulhhwu	mulhhwu RT, RA, RB	XO-form	Unsigned Multiply High Halfword.
mulhw	mulhw RT, RA, RB	XO-form	Multiplies two 32-bit integers and returns the upper 32 bits (Signed).
mulhwu	mulhwu RT, RA, RB	XO-form	Multiplies two 32-bit integers and returns the upper 32 bits (Unsigned).
mulld	mulld RT, RA, RB	XO-form	Multiplies two 64-bit integers and stores the lower 64 bits of the 128-bit result.
mullhw	mullhw RT, RA, RB	XO-form	Multiply bottom half of RA by bottom half of RB.
mullhwu	mullhwu RT, RA, RB	XO-form	Unsigned Multiply Low Halfword.
mullw	mullw RT, RA, RB	XO-form	Multiplies two 32-bit integers and stores the lower 32 bits of the 64-bit result.
nand	nand RA, RS, RB	X-form	Bitwise NAND. RA = ~(RS & RB).
nap	nap	X-form	Enters Nap power-saving mode (Supervisor only).
neg	neg RT, RA	XO-form	Computes the two's complement negation of a register (0 - RT).
nmacchw	nmacchw RT, RA, RB	XO-form	Negate product of cross halfwords and add to accumulator.
nmacchws	nmacchws RT, RA, RB	XO-form	Negate product of cross halfwords and add to accumulator (Signed Saturation).
nmachhw	nmachhw RT, RA, RB	XO-form	Negate product of high halfwords and add to accumulator.
nmachhws	nmachhws RT, RA, RB	XO-form	Negate product of high halfwords and add to accumulator (Signed Saturation).
nmaclhw	nmaclhw RT, RA, RB	XO-form	Negate product of low halfwords and add to accumulator.
nmaclhws	nmaclhws RT, RA, RB	XO-form	Negate product of low halfwords and add to accumulator (Signed Saturation).
nop	nop	D-form	Does nothing. (Alias for 'ori 0, 0, 0').
nor	nor RA, RS, RB	X-form	Bitwise NOR. RA = ~(RS | RB).
not	not RA, RS	X-form	Ones' complement (Bitwise NOT). (Alias for 'nor RA, RS, RS').
or	or RA, RS, RB	X-form	Performs a bitwise OR comparison.
orc	orc RA, RS, RB	X-form	Bitwise OR with complement. RA = RS | ~RB.
ori	ori RA, RS, UI	D-form	Performs a bitwise OR with a 16-bit unsigned immediate.
oris	oris RA, RS, UI	D-form	Performs a bitwise OR with a 16-bit immediate shifted left by 16 bits.
paddi	paddi RT, RA, SI, R	MLS:D-form	Adds 34-bit immediate.
paddi	paddi RT, RA, SI34, R	MLS:D-form (64-bit)	Adds a 34-bit signed immediate to a register. Supports PC-relative addressing (LEA).
paste	paste RA, RB	X-form	Completes a hardware copy (paste) operation.
paste.	paste. RA, RB	X-form	Paste operation that updates CR0 to indicate success/fail.
pdepd	pdepd RA, RS, RB	X-form	Deposits bits from RS to RA under control of mask RB (Scalar).
pextd	pextd RA, RS, RB	X-form	Extracts bits from RS to RA under control of mask RB (Scalar).
pla	pla RT, label	Pseudo	Pseudo-instruction for paddi with R=1. Loads the address of a label.
plbz	plbz RT, D34(RA), R	MLS:D-form	Loads a byte and zero-extends it, using a 34-bit offset.
pld	pld RT, D34(RA), R	MLS:D-form	Loads a 64-bit value from memory using a 34-bit immediate offset (PC-relative or absolute).
plh	plh RT, D(RA), R	MLS:D-form	Loads 16-bit halfword using 34-bit offset.
plha	plha RT, D(RA), R	MLS:D-form	Loads 16-bit halfword (Sign Extended) using 34-bit offset.
pli	pli RT, SI34	MLS:D-form	Loads a 34-bit signed immediate into a register. (Replaces multiple 'lis/ori' instructions).
plq	plq RTp, D(RA), R	MLS:D-form	Loads 128 bits into two GPRs using a 34-bit offset.
plwa	plwa RT, D(RA), R	MLS:D-form	Loads 32-bit word (Sign Extended) using 34-bit offset.
plwz	plwz RT, D34(RA), R	MLS:D-form	Loads a 32-bit word and zero-extends it to 64 bits, using a 34-bit offset.
plxvp	plxvp XT, D(RA), R	8LS:D-form	Loads a 256-bit vector pair with 34-bit offset.
pmxvbf16ger2	pmxvbf16ger2 AT, XA, XB, XMSK, YMSK	MMIRR-form	Matrix Multiply Assist (MMA) instruction. Computes ACC <- ACC + (A * B) using BF16 inputs.
pmxvf64ger	pmxvf64ger AT, XA, XB, XMSK, YMSK	MMIRR-form	Masked version of Double-Precision MMA.
pmxvi4ger8	pmxvi4ger8 AT, XA, XB, XMSK, YMSK	MMIRR-form	Masked 4-bit integer matrix multiply.
pmxvi4ger8pp	pmxvi4ger8pp AT, XA, XB, XMSK, YMSK	MMIRR-form	Masked unsigned 4-bit integer matrix multiply.
pmxvi8ger4	pmxvi8ger4 AT, XA, XB, XMSK, YMSK	MMIRR-form	Masked version of 8-bit integer MMA.
popcntd	popcntd RA, RS	X-form	Counts the number of set bits (1s) in a 64-bit register.
popcntw	popcntw RA, RS	X-form	Counts the number of set bits (1s) in the lower 32 bits of a register.
prtyd	prtyd RA, RS	X-form	Calculates parity of a doubleword (Scalar).
prtyw	prtyw RA, RS	X-form	Calculates parity of a word (Scalar).
ps_add	ps_add FRT, FRA, FRB	A-form	Adds two paired singles.
ps_madd	ps_madd FRT, FRA, FRC, FRB	A-form	Multiply-Add on paired singles.
ps_mul	ps_mul FRT, FRA, FRC	A-form	Multiplies two paired singles.
ps_sub	ps_sub FRT, FRA, FRB	A-form	Subtracts two paired singles.
psq_l	psq_l FRT, D(RA), W, I	X-form	Loads a paired single from memory (Embedded/Legacy).
psq_st	psq_st FRS, D(RA), W, I	X-form	Stores a paired single to memory (Embedded/Legacy).
pstb	pstb RS, D(RA), R	MLS:D-form	Stores byte using 34-bit offset.
psth	psth RS, D(RA), R	MLS:D-form	Stores halfword using 34-bit offset.
pstq	pstq RSp, D(RA), R	MLS:D-form	Stores 128 bits from two GPRs using a 34-bit offset.
pststd	pststd RS, D34(RA), R	MLS:D-form	Stores a 64-bit value to memory using a 34-bit immediate offset.
pstw	pstw RS, D(RA), R	MLS:D-form	Stores word using 34-bit offset.
pstxvp	pstxvp XS, D(RA), R	8LS:D-form	Stores a 256-bit vector pair with 34-bit offset.
rfebb	rfebb S	XL-form	Returns from an event handler (EBB).
rfid	rfid	XL-form	Returns from an interrupt handler. Restores PC from SRR0 and MSR from SRR1.
rfscv	rfscv	XL-form	Returns from a vectored system call.
ripv	ripv	X-form	Enters Deep Sleep mode (Supervisor only).
rldic	rldic RA, RS, SH, MB	MD-form	Rotates a 64-bit value left, then clears bits based on a mask.
rldic	rldic RA, RS, SH, MB	MD-form	Rotates a 64-bit register left, then clears bits based on a mask. 64-bit equivalent of rlwinm.
rldicl	rldicl RA, RS, SH, MB	MD-form	Rotates left and clears upper bits (Extract/Shift Right logic).
rldicr	rldicr RA, RS, SH, ME	MD-form	Rotates left and clears lower bits (Shift Left logic).
rldicr	rldicr RA, RS, SH, ME	MD-form	Rotates 64-bit RS left by SH, then clears the low-order bits (ME+1 to 63).
rldimi	rldimi RA, RS, SH, MB	MD-form	Rotates 64-bit value and inserts into target under mask.
rlwimi	rlwimi RA, RS, SH, MB, ME	M-form	Rotates a word left, then inserts bits into the target under a mask. Used for inserting bitfields.
rlwinm	rlwinm RA, RS, SH, MB, ME	M-form	Rotates a word left, then ANDs with a mask. Used for extracting bitfields.
rlwnm	rlwnm RA, RS, RB, MB, ME	M-form	Rotates a word left by amount in RB, then ANDs with a mask.
sc	sc LEV	SC-form	Invokes the operating system (Supervisor Call).
scv	scv LEV	SC-form	Performs a system call to a fixed vector address (Faster than 'sc').
se_add	se_add RX, RY	SE-form	Adds two registers (16-bit encoding). RX = RX + RY.
se_addaddi	se_addaddi RX, RY, OIM	SE-form	Complex add (RX = RX + RY + OIM).
se_addi	se_addi RX, OIM	SE-form	RX = RX + Immediate.
se_and	se_and RX, RY	SE-form	Bitwise AND (16-bit). RX = RX & RY.
se_andi	se_andi RX, UIM	SE-form	RX = RX & Immediate.
se_b	se_b BD8	SE-form	Unconditional short branch (8-bit displacement).
se_bc	se_bc BO, BI, BD8	SE-form	Branches if CR bit is set/clear.
se_bclri	se_bclri RX, UIM	SE-form	Clears a specific bit in RX.
se_bctr	se_bctr	SE-form	Computed jump.
se_bgeni	se_bgeni RX, UI5	SE-form	Generates a single bit.
se_bgeni	se_bgeni RX, UIM	SE-form	Generates a value with a single bit set.
se_bl	se_bl BD8	SE-form	Function call (8-bit displacement).
se_blr	se_blr	SE-form	Return from function.
se_bmaski	se_bmaski RX, UI5	SE-form	Creates a mask.
se_bmaski	se_bmaski RX, UIM	SE-form	Generates a mask of ones.
se_bseti	se_bseti RX, UIM	SE-form	Sets a specific bit in RX.
se_btsti	se_btsti RX, UIM	SE-form	Tests a bit in RX and updates CR0.
se_cmp	se_cmp RX, RY	SE-form	Signed comparison of RX and RY.
se_cmpi	se_cmpi RX, OIM	SE-form	Compares RX with immediate.
se_cmpl	se_cmpl RX, RY	SE-form	Unsigned comparison of RX and RY.
se_cmpli	se_cmpli RX, UIM	SE-form	Unsigned comparison of RX with immediate.
se_extsb	se_extsb RX	SE-form	Sign extends byte.
se_extsh	se_extsh RX	SE-form	Sign extends halfword.
se_extzb	se_extzb RX	SE-form	Zero extends byte.
se_extzh	se_extzh RX	SE-form	Zero extends halfword.
se_lbz	se_lbz RZ, SD4(RX)	SE-form	Loads byte with 4-bit offset.
se_lhz	se_lhz RZ, SD4(RX)	SE-form	Loads halfword with 4-bit offset.
se_li	se_li RX, UI7	SE-form	Loads small immediate.
se_li	se_li RX, UIM	SE-form	Loads a 7-bit immediate into RX.
se_lwz	se_lwz RZ, SD4(RX)	SE-form	Loads word with 4-bit compressed offset.
se_mfar	se_mfar RX, ARY	SE-form	Moves AR to RX (16-bit).
se_mfctr	se_mfctr RX	SE-form	Reads CTR.
se_mflr	se_mflr RX	SE-form	Reads LR.
se_mtar	se_mtar ARX, RY	SE-form	Moves RX to AR (16-bit).
se_mtctr	se_mtctr RX	SE-form	Writes CTR.
se_mtlr	se_mtlr RX	SE-form	Writes LR.
se_mullw	se_mullw RX, RY	SE-form	Multiplies two words (16-bit). RX = RX * RY.
se_neg	se_neg RX	SE-form	Negates a register (16-bit). RX = -RX.
se_not	se_not RX	SE-form	Bitwise NOT (16-bit). RX = ~RX.
se_or	se_or RX, RY	SE-form	Bitwise OR (16-bit). RX = RX | RY.
se_rfci	se_rfci	SE-form	Returns from critical interrupt.
se_rfdi	se_rfdi	SE-form	Returns from debug interrupt.
se_rfi	se_rfi	SE-form	Returns from standard interrupt.
se_rfmci	se_rfmci	SE-form	Returns from machine check.
se_sc	se_sc	SE-form	System call (16-bit encoding).
se_slw	se_slw RX, RY	SE-form	Shifts word left (16-bit). RX = RX << RY.
se_srw	se_srw RX, RY	SE-form	Shifts word right (16-bit). RX = RX >> RY.
se_stb	se_stb RZ, SD4(RX)	SE-form	Stores byte with 4-bit offset.
se_sth	se_sth RZ, SD4(RX)	SE-form	Stores halfword with 4-bit offset.
se_stw	se_stw RZ, SD4(RX)	SE-form	Stores word with 4-bit compressed offset.
se_sub	se_sub RX, RY	SE-form	Subtracts two registers (16-bit). RX = RX - RY.
se_trap	se_trap	SE-form	Unconditional trap (16-bit).
se_xor	se_xor RX, RY	SE-form	Bitwise XOR (16-bit). RX = RX ^ RY.
setb	setb RT, BFA	X-form	Sets RT to -1, 0, or 1 based on CR field.
setbc	setbc RT, BI	X-form	Sets RT to 1 if CR bit is set, else 0. (Branchless logic).
setbcr	setbcr RT, BI	X-form	Sets RT to 1 if CR bit is clear, else 0.
setnbc	setnbc RT, BI	X-form	Sets RT to -1 if CR bit is set, else 0.
setnbcr	setnbcr RT, BI	X-form	Sets RT to -1 if CR bit is clear, else 0.
slbia	slbia IH	X-form	Invalidates all Segment Lookaside Buffer entries (OS Management).
slbie	slbie RB	X-form	Invalidates an SLB entry. Critical for memory management on Power systems.
slbmfee	slbmfee RT, RB	X-form	Reads the ESID part of an SLB entry.
slbmfev	slbmfev RT, RB	X-form	Reads the VSID part of an SLB entry.
slbmte	slbmte RS, RB	X-form	Writes an SLB entry (Mapping effective to virtual address).
slbsync	slbsync	X-form	Ensures SLB invalidations have propagated.
sld	sld RA, RS, RB	X-form	Shifts a 64-bit value left by amount in RB.
sld	sld RA, RS, RB	X-form	Shifts a 64-bit register left by the amount specified in RB.
sleep	sleep	X-form	Enters Sleep power-saving mode (Supervisor only).
slw	slw RA, RS, RB	X-form	Shifts a 32-bit register left by the amount specified in RB.
srad	srad RA, RS, RB	X-form	Arithmetic right shift of 64-bit value (preserves sign).
sradi	sradi RA, RS, SH	XS-form	Arithmetic right shift by immediate.
sradi	sradi RA, RS, SH	XS-form	Performs an arithmetic right shift on a 64-bit doubleword by a constant amount.
sraw	sraw RA, RS, RB	X-form	Performs an arithmetic right shift (sign bit replicated) on a 32-bit word. Updates Carry (CA) if bits are shifted out.
srawi	srawi RA, RS, SH	X-form	Performs an arithmetic right shift on a 32-bit word by a constant amount.
srd	srd RA, RS, RB	X-form	Logical right shift of 64-bit value.
srw	srw RA, RS, RB	X-form	Performs a logical right shift (zeros shifted in) on a 32-bit word.
stb	stb RS, D(RA)	D-form	Stores the low 8 bits of a register to memory.
stbci	stbci RS, RA, RB	X-form	Stores a byte bypassing the cache.
stbcx.	stbcx. RS, RA, RB	X-form	Atomic Store Byte.
stbepx	stbepx RS, RA, RB	X-form	Stores a byte using the External PID.
std	std RS, DS(RA)	DS-form	Stores a 64-bit doubleword to memory.
stdbrx	stdbrx RS, RA, RB	X-form	Swaps bytes and stores 64 bits.
stdci	stdci RS, RA, RB	X-form	Stores a doubleword bypassing the cache.
stdcx.	stdcx. RS, RA, RB	X-form	Atomic Store Doubleword.
stdi	stdi RS, RA, RB	X-form	Stores a word and sends decoration sideband signals.
sth	sth RS, D(RA)	D-form	Stores the low 16 bits of a register to memory.
sthbrx	sthbrx RS, RA, RB	X-form	Swaps bytes and stores a halfword.
sthci	sthci RS, RA, RB	X-form	Stores a halfword bypassing the cache.
sthcx.	sthcx. RS, RA, RB	X-form	Atomic Store Halfword.
sthep	sthepx RS, RA, RB	X-form	Stores a halfword using the External PID.
stmw	stmw RT, D(RA)	D-form	Stores words from registers RT through R31 to memory (Context Switch).
stop	stop	X-form	Stops instruction execution and enters a power-saving state (replaces nap/doze on P9+).
stq	stq RSp, DQ(RA)	DQ-form	Stores 128 bits from two adjacent GPRs.
stqcx.	stqcx. RS, RA, RB	X-form	Atomic 128-bit store. Stores if reservation exists.
stswi	stswi RT, RA, NB	X-form	Stores N bytes from registers to memory.
stswx	stswx RT, RA, RB	X-form	Stores N bytes to memory (N in XER).
stvx	stvx vS, RA, RB	X-form	Stores a 128-bit vector to memory. Address must be 16-byte aligned.
stw	stw RS, D(RA)	D-form	Stores the low 32 bits of a register to memory.
stwbrx	stwbrx RS, RA, RB	X-form	Swaps bytes and stores a word.
stwci	stwci RS, RA, RB	X-form	Stores a word bypassing the cache.
stwcx.	stwcx. RS, RA, RB	X-form	Atomic Store Word (checks reservation).
stwepx	stwepx RS, RA, RB	X-form	Stores a word using the External PID.
stxsiwx	stxsiwx XS, RA, RB	XX1-form	Stores the low 32 bits of a VSX register to memory.
stxv	stxv XS, DQ(RA)	DQ-form	Stores a 128-bit vector to memory (VSX aligned offset).
stxvd2x	stxvd2x XS, RA, RB	XX1-form	Stores a 128-bit VSX register to memory. Does NOT require alignment.
stxvl	stxvl XS, RA, RB	XX1-form	Stores N bytes from a vector to memory.
stxvp	stxvp XS, DQ(RA)	DQ-form	Stores a 256-bit vector pair.
stxvw4x	stxvw4x XS, RA, RB	XX1-form	Stores four words from a vector (unaligned).
sync	sync L	X-form	The master memory barrier. Ensures all previous instructions appear to complete before any subsequent instructions start. (L=0: Heavyweight, L=1: Lightweight/LWSYNC).
tabort.	tabort. RA	X-form	Forces a transaction failure and rollback.
tabortdc	tabortdc TO, RA, RB	X-form	Aborts a transaction if the condition is met (Doubleword comparison).
tabortdci	tabortdci TO, RA, SI	X-form	Aborts transaction if doubleword condition (Immediate) is met.
tabortwc	tabortwc TO, RA, RB	X-form	Aborts a transaction if the condition is met (Word comparison).
tabortwci	tabortwci TO, RA, SI	X-form	Aborts transaction if word condition (Immediate) is met.
tbegin.	tbegin. R	X-form	Initiates a hardware transaction. If the transaction fails, execution rolls back to this point. Sets CR0 based on success/failure.
tcheck	tcheck BF	X-form	Checks transaction status and updates CR.
td	td TO, RA, RB	X-form	Traps if condition (comparison of doublewords) is met.
tdi	tdi TO, RA, SIM	D-form	Traps if condition (comparison with immediate) is met.
tend.	tend. A	X-form	Commits the current hardware transaction. If successful, memory changes become visible atomically.
tlbia	tlbia	X-form	Invalidates the entire Translation Lookaside Buffer.
tlbie	tlbie RB, RS	X-form	Invalidates a TLB entry corresponding to the address in RB.
tlbiel	tlbiel RB	X-form	Invalidates a TLB entry on the current processor only.
tlbilx	tlbilx T, RA, RB	X-form	Invalidates TLB entries on the local processor based on Process ID (PID).
tlbivax	tlbivax RA, RB	X-form	Invalidates a TLB entry by virtual address.
tlbre	tlbre	X-form	Reads a TLB entry into MAS registers.
tlbsx	tlbsx RA, RB	X-form	Searches the TLB for an address.
tlbsync	tlbsync	X-form	Ensures TLB invalidations have propagated to all processors.
tlbwe	tlbwe	X-form	Writes a TLB entry from MAS registers.
trap	trap	Pseudo	Unconditional trap. Forces an exception. (Encoded as tw 31, 0, 0).
trechkpt	trechkpt	X-form	Updates the transaction checkpoint.
tresume	tresume.	X-form	Resumes a suspended transaction.
tsr	tsr L	X-form	Suspends or resumes a transaction based on L.
tsuspend	tsuspend.	X-form	Suspends the current transaction.
tw	tw TO, RA, RB	X-form	Traps if condition (comparison of words) is met.
twi	twi TO, RA, SIM	D-form	Traps if condition (comparison with immediate) is met.
urfid	urfid	XL-form	Returns from an ultravisor interrupt.
vabsdub	vabsdub vD, vA, vB	VA-form	Computes |A - B| for bytes.
vabsduh	vabsduh vD, vA, vB	VA-form	Computes |A - B| for halfwords.
vabsduw	vabsduw vD, vA, vB	VA-form	Computes |A - B| for words.
vaddcuq	vaddcuq vD, vA, vB	VX-form	Calculates carry-out for quadword addition.
vaddcuw	vaddcuw vD, vA, vB	VX-form	Calculates carry-out for word addition.
vaddfp	vaddfp vD, vA, vB	VA-form	Adds four single-precision floats (Classic VMX).
vaddsbs	vaddsbs vD, vA, vB	VX-form	Adds 16 signed bytes with saturation (-128..127).
vaddshs	vaddshs vD, vA, vB	VX-form	Adds 8 signed halfwords with saturation.
vaddsws	vaddsws vD, vA, vB	VX-form	Adds 4 signed words with saturation.
vaddubm	vaddubm vD, vA, vB	VA-form	Adds sixteen 8-bit integers from two vectors. Arithmetic is modulo 256 (wraps around).
vaddubs	vaddubs vD, vA, vB	VX-form	Adds 16 unsigned bytes with saturation (0..255).
vaddudm	vaddudm vD, vA, vB	VX-form	Adds 2 doublewords modulo 2^64.
vadduhm	vadduhm vD, vA, vB	VX-form	Adds 8 halfwords modulo 65536.
vadduhs	vadduhs vD, vA, vB	VX-form	Adds 8 unsigned halfwords with saturation.
vadduqm	vadduqm vD, vA, vB	VA-form	Adds two 128-bit integers.
vadduwm	vadduwm vD, vA, vB	VX-form	Adds 4 words modulo 2^32.
vadduws	vadduws vD, vA, vB	VX-form	Adds 4 unsigned words with saturation.
vand	vand vD, vA, vB	VX-form	Bitwise AND of two 128-bit vectors.
vandc	vandc vD, vA, vB	VX-form	Bitwise AND of vA with the ones' complement of vB (vA & ~vB).
vavgsb	vavgsb vD, vA, vB	VA-form	Computes (a+b+1)/2 for signed bytes.
vavgsh	vavgsh vD, vA, vB	VA-form	Computes (a+b+1)/2 for signed halfwords.
vavgsw	vavgsw vD, vA, vB	VA-form	Computes (a+b+1)/2 for signed words.
vavgub	vavgub vD, vA, vB	VA-form	Computes (a+b+1)/2 for bytes.
vavguh	vavguh vD, vA, vB	VA-form	Computes (a+b+1)/2 for halfwords.
vavguw	vavguw vD, vA, vB	VA-form	Computes (a+b+1)/2 for words.
vbcdadd	vbcdadd vD, vA, vB, PS	VX-form	Adds two BCD (Binary Coded Decimal) vectors.
vbcdsub	vbcdsub vD, vA, vB, PS	VX-form	Subtracts two BCD vectors.
vbrd	vbrd vD, vB	VX-form	Reverses bytes within each doubleword.
vbrh	vbrh vD, vB	VX-form	Reverses bytes within each halfword (Endian Swap).
vbrq	vbrq vD, vB	VX-form	Reverses bytes within the entire 128-bit quadword.
vbrw	vbrw vD, vB	VX-form	Reverses bytes within each word.
vcfsx	vcfsx vD, vB, UIM	VX-form	Converts 4 signed 32-bit integers to floats.
vcfuged	vcfuged vD, vA, vB	VX-form	Separates bits of source into two groups based on mask (Power10).
vcfux	vcfux vD, vB, UIM	VX-form	Converts 4 unsigned 32-bit integers to floats.
vcipher	vcipher vD, vA, vB	VX-form	Performs one round of AES encryption (SubBytes, ShiftRows, MixColumns, AddRoundKey).
vcipherlast	vcipherlast vD, vA, vB	VX-form	Performs the final round of AES encryption (SubBytes, ShiftRows, AddRoundKey). No MixColumns.
vclrlb	vclrlb vD, vA, RB	VX-form	Clears the N leftmost bytes of a vector.
vclrrb	vclrrb vD, vA, RB	VX-form	Clears the N rightmost bytes of a vector.
vclzb	vclzb vD, vB	VX-form	Counts leading zeros in each byte.
vclzd	vclzd vD, vB	VX-form	Counts leading zeros in each doubleword.
vclzh	vclzh vD, vB	VX-form	Counts leading zeros in each halfword.
vclzlsbb	vclzlsbb RA, vB	VX-form	Counts leading zeros on the LSB of each byte.
vclzw	vclzw vD, vB	VX-form	Counts leading zeros in each word.
vcmpbfp	vcmpbfp vD, vA, vB	VC-form	Compares 4 floats to see if they are within bounds.
vcmpeqfp	vcmpeqfp vD, vA, vB	VC-form	Compares 4 floats for equality.
vcmpequb	vcmpequb vD, vA, vB	VC-form	Compares 16 bytes. Result is 0xFF (True) or 0x00 (False) per byte.
vcmpequd	vcmpequd vD, vA, vB	VC-form	Compares 2 doublewords for equality.
vcmpequh	vcmpequh vD, vA, vB	VC-form	Compares 8 halfwords for equality.
vcmpequw	vcmpequw vD, vA, vB	VC-form	Compares words for equality. Sets result bits to all 1s (True) or all 0s (False).
vcmpgefp	vcmpgefp vD, vA, vB	VC-form	Compares 4 floats (A >= B).
vcmpgtfp	vcmpgtfp vD, vA, vB	VC-form	Compares 4 floats (A > B).
vcmpgtsb	vcmpgtsb vD, vA, vB	VC-form	Signed > comparison for 16 bytes.
vcmpgtsd	vcmpgtsd vD, vA, vB	VC-form	Signed > comparison for 2 doublewords.
vcmpgtsh	vcmpgtsh vD, vA, vB	VC-form	Signed > comparison for 8 halfwords.
vcmpgtsw	vcmpgtsw vD, vA, vB	VC-form	Signed > comparison for 4 words.
vcmpgtub	vcmpgtub vD, vA, vB	VC-form	Unsigned > comparison for 16 bytes.
vcmpgtud	vcmpgtud vD, vA, vB	VC-form	Unsigned > comparison for 2 doublewords.
vcmpgtuh	vcmpgtuh vD, vA, vB	VC-form	Unsigned > comparison for 8 halfwords.
vcmpgtuw	vcmpgtuw vD, vA, vB	VC-form	Unsigned > comparison for 4 words.
vcmpneb	vcmpneb vD, vA, vB	VC-form	Compares bytes for inequality.
vcmpneh	vcmpneh vD, vA, vB	VC-form	Compares halfwords for inequality.
vcmpnew	vcmpnew vD, vA, vB	VC-form	Compares words for inequality.
vctsxs	vctsxs vD, vB, UIM	VX-form	Converts 4 floats to 4 signed 32-bit integers.
vctuxs	vctuxs vD, vB, UIM	VX-form	Converts 4 floats to 4 unsigned 32-bit integers.
vctzb	vctzb vD, vB	VX-form	Counts trailing zeros in each byte.
vctzd	vctzd vD, vB	VX-form	Counts trailing zeros in each doubleword.
vctzh	vctzh vD, vB	VX-form	Counts trailing zeros in each halfword.
vctzlsbb	vctzlsbb RA, vB	VX-form	Counts trailing zeros on the LSB of each byte.
vctzw	vctzw vD, vB	VX-form	Counts trailing zeros in each word.
vexpandbm	vexpandbm vD, vB	VX-form	Expands bits from a GPR mask into a byte-element vector.
vexpanddm	vexpanddm vD, vB	VX-form	Expands bits from a GPR mask into a doubleword-element vector.
vexpandhm	vexpandhm vD, vB	VX-form	Expands bits from a GPR mask into a halfword-element vector.
vexpandqm	vexpandqm vD, vB	VX-form	Expands bits from a GPR mask into a quadword-element vector.
vexpandwm	vexpandwm vD, vB	VX-form	Expands bits from a GPR mask into a word-element vector.
vextractbm	vextractbm RA, vB	VX-form	Extracts MSB of each byte into a GPR mask.
vextractd	vextractd RA, vB, UIM	VX-form	Extracts a doubleword from a vector into a GPR.
vextractdm	vextractdm RA, vB	VX-form	Extracts MSB of each doubleword into a GPR mask.
vextracthm	vextracthm RA, vB	VX-form	Extracts MSB of each halfword into a GPR mask.
vextractqm	vextractqm RA, vB	VX-form	Extracts MSB of quadword into a GPR mask.
vextractub	vextractub RA, vB, UIM	VX-form	Extracts a specific byte from a vector into a GPR.
vextractuh	vextractuh RA, vB, UIM	VX-form	Extracts a halfword from a vector into a GPR.
vextractuw	vextractuw RA, vB, UIM	VX-form	Extracts a word from a vector into a GPR.
vextractwm	vextractwm RA, vB	VX-form	Extracts MSB of each word into a GPR mask.
vextsb2d	vextsb2d vD, vB	VX-form	Sign-extends bytes to doublewords.
vextsb2w	vextsb2w vD, vB	VX-form	Sign-extends bytes to words.
vextsh2d	vextsh2d vD, vB	VX-form	Sign-extends halfwords to doublewords.
vextsh2w	vextsh2w vD, vB	VX-form	Sign-extends halfwords to words.
vextsw2d	vextsw2d vD, vB	VX-form	Sign-extends words to doublewords.
vgbbd	vgbbd vD, vB	VX-form	Gathers the LSB of each byte into a single word. (Highly specific permutation).
vgnb	vgnb vD, vB, UIM	VX-form	Gathers non-zero bytes from a vector into the bottom of the target.
vinsertb	vinsertb vD, vB, UIM	VX-form	Inserts a byte from a GPR into a vector.
vinsertd	vinsertd vD, vB, UIM	VX-form	Inserts a doubleword from a GPR into a vector.
vinsertd_p	vinsertd vD, RB, UIM	VX-form	Inserts doubleword from GPR into Vector.
vinserth	vinserth vD, vB, UIM	VX-form	Inserts a halfword from a GPR into a vector.
vinserth_p	vinserth vD, RB, UIM	VX-form	Inserts halfword from GPR into Vector.
vinsertw	vinsertw vD, vB, UIM	VX-form	Inserts a word from a GPR into a vector.
vinsertw_p	vinsertw vD, RB, UIM	VX-form	Inserts word from GPR into Vector.
vmaxsb	vmaxsb vD, vA, vB	VA-form	Selects maximum value per byte (signed).
vmaxsh	vmaxsh vD, vA, vB	VA-form	Selects maximum value per halfword (signed).
vmaxsw	vmaxsw vD, vA, vB	VA-form	Selects maximum value per word (signed).
vmaxub	vmaxub vD, vA, vB	VA-form	Selects maximum value per byte (unsigned).
vmaxuh	vmaxuh vD, vA, vB	VA-form	Selects maximum value per halfword (unsigned).
vmaxuw	vmaxuw vD, vA, vB	VA-form	Selects maximum value per word (unsigned).
vminsb	vminsb vD, vA, vB	VA-form	Selects minimum value per byte (signed).
vminsh	vminsh vD, vA, vB	VA-form	Selects minimum value per halfword (signed).
vminsw	vminsw vD, vA, vB	VA-form	Selects minimum value per word (signed).
vminub	vminub vD, vA, vB	VA-form	Selects minimum value per byte (unsigned).
vminuh	vminuh vD, vA, vB	VA-form	Selects minimum value per halfword (unsigned).
vminuw	vminuw vD, vA, vB	VA-form	Selects minimum value per word (unsigned).
vmrgew	vmrgew vD, vA, vB	VX-form	Merges even words from two vectors.
vmrghb	vmrghb vD, vA, vB	VX-form	Interleaves high-order bytes from two vectors (Permutation).
vmrghh	vmrghh vD, vA, vB	VX-form	Interleaves high-order halfwords.
vmrghw	vmrghw vD, vA, vB	VX-form	Interleaves high-order words.
vmrglb	vmrglb vD, vA, vB	VX-form	Interleaves low-order bytes.
vmrglh	vmrglh vD, vA, vB	VX-form	Interleaves low-order halfwords.
vmrglw	vmrglw vD, vA, vB	VX-form	Interleaves low-order words.
vmrgow	vmrgow vD, vA, vB	VX-form	Merges odd words from two vectors.
vmsumshm	vmsumshm vD, vA, vB, vC	VA-form	Multiplies halfwords and sums adjacent results into words.
vmsumshs	vmsumshs vD, vA, vB, vC	VA-form	Multiplies halfwords and sums with saturation.
vmsumubm	vmsumubm vD, vA, vB, vC	VA-form	Multiplies bytes and sums adjacent results into words.
vmulesb	vmulesb vD, vA, vB	VX-form	Multiplies even signed bytes to halfwords.
vmulesh	vmulesh vD, vA, vB	VX-form	Multiplies even signed halfwords to words.
vmulesw	vmulesw vD, vA, vB	VX-form	Multiplies even words (0,2) to 64-bit signed result.
vmuleub	vmuleub vD, vA, vB	VX-form	Multiplies even unsigned bytes to halfwords.
vmuleuh	vmuleuh vD, vA, vB	VX-form	Multiplies even unsigned halfwords to words.
vmuleuw	vmuleuw vD, vA, vB	VX-form	Multiplies even words (0,2) to 64-bit result.
vmulfp	vmulfp vD, vA, vB	VA-form	Multiplies four single-precision floats (Classic VMX).
vmulhsd	vmulhsd vD, vA, vB	VX-form	Multiplies signed doublewords, returning the high 64 bits.
vmulhsw	vmulhsw vD, vA, vB	VX-form	Multiplies signed words, returning the high 32 bits.
vmulhud	vmulhud vD, vA, vB	VX-form	Multiplies unsigned doublewords, returning the high 64 bits.
vmulhuw	vmulhuw vD, vA, vB	VX-form	Multiplies unsigned words, returning the high 32 bits.
vmulosb	vmulosb vD, vA, vB	VX-form	Multiplies odd signed bytes to halfwords.
vmulosh	vmulosh vD, vA, vB	VX-form	Multiplies odd signed halfwords to words.
vmulosw	vmulosw vD, vA, vB	VX-form	Multiplies odd words (1,3) to 64-bit signed result.
vmuloub	vmuloub vD, vA, vB	VX-form	Multiplies odd unsigned bytes to halfwords.
vmulouh	vmulouh vD, vA, vB	VX-form	Multiplies odd unsigned halfwords to words.
vmulouw	vmulouw vD, vA, vB	VA-form	Multiplies the 1st and 3rd words of the source vectors to produce two 64-bit results.
vmulouw	vmulouw vD, vA, vB	VX-form	Multiplies odd words (1,3) to 64-bit result.
vncipher	vncipher vD, vA, vB	VX-form	Performs one round of AES decryption.
vncipherlast	vncipherlast vD, vA, vB	VX-form	Performs the final round of AES decryption.
vnegd	vnegd vD, vB	VX-form	Negates each doubleword integer.
vnegw	vnegw vD, vB	VX-form	Negates each word integer.
vnor	vnor vD, vA, vB	VX-form	Bitwise NOR of two 128-bit vectors. (NOT (A OR B)).
vor	vor vD, vA, vB	VX-form	Bitwise OR of two 128-bit vectors.
vpdepd	vpdepd vD, vA, vB	VX-form	Deposits bits from source to target under control of a mask (Power10).
vperm	vperm vD, vA, vB, vC	VA-form	The signature AltiVec instruction. Constructs a new vector by selecting bytes from two source vectors based on a permute control vector.
vpermr	vpermr vD, vA, vB, vC	VA-form	Bitwise byte shuffle similar to vperm but for little-endian access optimization.
vpermxor	vpermxor vD, vA, vB, vC	VA-form	Permutes bytes from vA and vB, then XORs with vC. Used for finite field arithmetic.
vpextd	vpextd vD, vA, vB	VX-form	Extracts bits from source based on a mask (Power10).
vpkpx	vpkpx vD, vA, vB	VX-form	Packs 8 words into 8 pixels (1/5/5/5 format).
vpkshss	vpkshss vD, vA, vB	VX-form	Saturates 8 signed halfwords to 16 signed bytes.
vpkswss	vpkswss vD, vA, vB	VX-form	Saturates 4 signed words to 8 signed halfwords.
vpkuhum	vpkuhum vD, vA, vB	VX-form	Truncates 8 halfwords to 16 bytes (modulo 256).
vpkuhus	vpkuhus vD, vA, vB	VX-form	Saturates 8 halfwords to 16 unsigned bytes.
vpkuwum	vpkuwum vD, vA, vB	VX-form	Truncates 4 words to 8 halfwords.
vpmsumb	vpmsumb vD, vA, vB	VX-form	Performs GF(2) polynomial arithmetic (Carryless Multiply) on bytes.
vpmsumd	vpmsumd vD, vA, vB	VX-form	Performs GF(2) polynomial arithmetic on doublewords.
vpmsumh	vpmsumh vD, vA, vB	VX-form	Performs GF(2) polynomial arithmetic on halfwords.
vpmsumw	vpmsumw vD, vA, vB	VX-form	Performs GF(2) polynomial arithmetic on words.
vpopcntb	vpopcntb vD, vB	VX-form	Counts set bits in each byte.
vpopcntd	vpopcntd vD, vB	VX-form	Counts set bits in each doubleword.
vpopcnth	vpopcnth vD, vB	VX-form	Counts set bits in each halfword.
vpopcntw	vpopcntw vD, vB	VX-form	Counts set bits in each word.
vprtybd	vprtybd vD, vB	VX-form	Computes parity of bytes within doublewords.
vprtybq	vprtybq vD, vB	VX-form	Computes parity of bytes within quadword.
vprtybw	vprtybw vD, vB	VX-form	Computes parity of bytes within words.
vrfim	vrfim vD, vB	VX-form	Rounds 4 floats to integer (floor).
vrfin	vrfin vD, vB	VX-form	Rounds 4 floats to nearest integer.
vrfip	vrfip vD, vB	VX-form	Rounds 4 floats to integer (ceil).
vrfiz	vrfiz vD, vB	VX-form	Rounds 4 floats to integer (trunc).
vrlb	vrlb vD, vA, vB	VX-form	Rotates each byte left.
vrld	vrld vD, vA, vB	VX-form	Rotates each doubleword left.
vrlh	vrlh vD, vA, vB	VX-form	Rotates each halfword left.
vrlq	vrlq vD, vA, vB	VX-form	Rotates a 128-bit quadword left.
vrlw	vrlw vD, vA, vB	VX-form	Rotates each word left.
vsbox	vsbox vD, vA	VX-form	Performs the SubBytes operation (S-Box lookup) on a vector.
vsel	vsel vD, vA, vB, vC	VA-form	Bitwise selection. copies bits from vA if the corresponding bit in vC is 0, or from vB if vC is 1. (Like 'mux').
vshasigmad	vshasigmad vD, vA, ST, SIX	VX-form	Performs the Sigma0/Sigma1 functions for SHA-512.
vshasigmaw	vshasigmaw vD, vA, ST, SIX	VX-form	Performs the Sigma0/Sigma1/sigma0/sigma1 functions for SHA-256.
vsl	vsl vD, vA, vB	VX-form	Shifts vector left by octet count in vB.
vslb	vslb vD, vA, vB	VX-form	Shifts each byte left.
vslh	vslh vD, vA, vB	VX-form	Shifts each halfword left.
vslo	vslo vD, vA, vB	VX-form	Shifts vector left by byte count.
vslq	vslq vD, vA, vB	VX-form	Shifts a 128-bit quadword left.
vslw	vslw vD, vA, vB	VX-form	Shifts each of the four words in vA left by the number of bits specified in the corresponding word of vB.
vspltb	vspltb vD, vB, UIM	VX-form	Duplicates a byte element across the vector.
vsplth	vsplth vD, vB, UIM	VX-form	Duplicates a halfword element across the vector.
vspltisb	vspltisb vD, SIM	VX-form	Fills vector with immediate 5-bit signed value (-16 to 15).
vspltish	vspltish vD, SIM	VX-form	Fills vector with immediate 5-bit signed value.
vspltisw	vspltisw vD, SIM	VX-form	Fills vector with immediate 5-bit signed value.
vspltw	vspltw vD, vB, UIM	VX-form	Copies a single word element from the source vector into all four word elements of the destination.
vsr	vsr vD, vA, vB	VX-form	Shifts vector right by octet count in vB.
vsrab	vsrab vD, vA, vB	VX-form	Arithmetic right shift of bytes.
vsrah	vsrah vD, vA, vB	VX-form	Arithmetic right shift of halfwords.
vsraq	vsraq vD, vA, vB	VX-form	Arithmetic right shift of a 128-bit quadword.
vsraw	vsraw vD, vA, vB	VX-form	Arithmetic right shift of words.
vsrb	vsrb vD, vA, vB	VX-form	Shifts each byte right.
vsrh	vsrh vD, vA, vB	VX-form	Shifts each halfword right.
vsro	vsro vD, vA, vB	VX-form	Shifts vector right by byte count.
vsrq	vsrq vD, vA, vB	VX-form	Shifts a 128-bit quadword right.
vsrw	vsrw vD, vA, vB	VX-form	Shifts each word right.
vstribl	vstribl vD, vB	VX-form	Identifies the first zero byte from the left.
vstribr	vstribr vD, vB	VX-form	Identifies the first zero byte from the right.
vstril	vstril vD, vB	VX-form	Isolates the leftmost element that matches the condition.
vstril_p	vstril. vD, vB	VX-form	Isolates the leftmost element and updates CR6.
vstrir	vstrir vD, vB	VX-form	Isolates the rightmost element that matches the condition.
vstrir_p	vstrir. vD, vB	VX-form	Isolates the rightmost element and updates CR6.
vsubcuq	vsubcuq vD, vA, vB	VX-form	Calculates carry-out for quadword subtraction.
vsubcuw	vsubcuw vD, vA, vB	VX-form	Calculates carry-out for word subtraction.
vsubfp	vsubfp vD, vA, vB	VA-form	Subtracts four single-precision floats (Classic VMX).
vsubsbs	vsubsbs vD, vA, vB	VX-form	Subtracts 16 signed bytes with saturation.
vsubshs	vsubshs vD, vA, vB	VX-form	Subtracts 8 signed halfwords with saturation.
vsubsws	vsubsws vD, vA, vB	VX-form	Subtracts 4 signed words with saturation.
vsububm	vsububm vD, vA, vB	VX-form	Subtracts 16 bytes modulo 256.
vsububs	vsububs vD, vA, vB	VX-form	Subtracts 16 unsigned bytes with saturation.
vsubudm	vsubudm vD, vA, vB	VX-form	Subtracts 2 doublewords modulo 2^64.
vsubuhm	vsubuhm vD, vA, vB	VX-form	Subtracts 8 halfwords modulo 65536.
vsubuhs	vsubuhs vD, vA, vB	VX-form	Subtracts 8 unsigned halfwords with saturation.
vsubuqm	vsubuqm vD, vA, vB	VA-form	Subtracts two 128-bit integers.
vsubuwm	vsubuwm vD, vA, vB	VA-form	Subtracts four 32-bit integers in parallel.
vsubuws	vsubuws vD, vA, vB	VX-form	Subtracts 4 unsigned words with saturation.
vsum2sws	vsum2sws vD, vA, vB	VA-form	Sums pairs of words into signed words.
vsum4sbs	vsum4sbs vD, vA, vB	VA-form	Sums every 4 signed bytes into a word.
vsum4shs	vsum4shs vD, vA, vB	VA-form	Sums every 2 halfwords into a word.
vsum4ubs	vsum4ubs vD, vA, vB	VA-form	Sums every 4 bytes into a word.
vsumsws	vsumsws vD, vA, vB	VA-form	Sums all 4 words into a single word result.
vupkhpx	vupkhpx vD, vB	VX-form	Unpacks high 4 pixels to 4 words.
vupkhsb	vupkhsb vD, vB	VX-form	Unpacks high 8 signed bytes to 8 signed halfwords.
vupkhsh	vupkhsh vD, vB	VX-form	Unpacks high 4 signed halfwords to 4 signed words.
vupklpx	vupklpx vD, vB	VX-form	Unpacks low 4 pixels to 4 words.
vupklsb	vupklsb vD, vB	VX-form	Unpacks low 8 signed bytes to 8 signed halfwords.
vupklsh	vupklsh vD, vB	VX-form	Unpacks low 4 signed halfwords to 4 signed words.
vxor	vxor vD, vA, vB	VX-form	Bitwise XOR of two 128-bit vectors.
wait	wait WC	X-form	Stops instruction execution and places the processor in a lower power state until an interrupt occurs.
wait	wait	X-form	Pauses execution to save power.
waitimpl	waitimpl	X-form	Waits for a specific implementation event.
waitrsv	waitrsv	X-form	Waits until a reservation is lost (Multithreading sync).
wrtee	wrtee RS	X-form	Updates the EE bit of the MSR from a GPR.
wrteei	wrteei E	X-form	Updates the EE bit of the MSR from an immediate.
xor	xor RA, RS, RB	X-form	Performs a bitwise Exclusive OR comparison.
xori	xori RA, RS, UI	D-form	Performs a bitwise XOR with a 16-bit unsigned immediate.
xoris	xoris RA, RS, UI	D-form	Performs a bitwise XOR with a 16-bit immediate shifted left by 16 bits.
xsabsdp	xsabsdp XT, XB	XX2-form	Scalar absolute value (64-bit float).
xsabsqp	xsabsqp vD, vB	X-form	Computes absolute value of a Quad float.
xsadddp	xsadddp XT, XA, XB	XX3-form	Adds the low doubleword of two VSX registers (scalar operation). The high doublewords are undefined or zeroed.
xsaddqp	xsaddqp vD, vA, vB	X-form	Adds two 128-bit Quad-Precision floating-point numbers held in VSX registers (pairs).
xsaddqpo	xsaddqpo vD, vA, vB	X-form	Used for Quad-Precision arithmetic on hardware that splits quads.
xsaddsp	xsaddsp XT, XA, XB	XX3-form	Scalar float addition (32-bit).
xscmpexpdp	xscmpexpdp BF, XA, XB	XX3-form	Compares exponents of two double-precision floats.
xscmpexpqp	xscmpexpqp BF, vA, vB	X-form	Compares exponents of two Quad floats.
xscmpodp	xscmpodp BF, XA, XB	XX3-form	Scalar compare (Exceptions on NaN).
xscmpopoqp	xscmpopoqp BF, vA, vB	X-form	Compares Quad floats (Signaling on NaN).
xscmpudp	xscmpudp BF, XA, XB	XX3-form	Scalar compare (No exceptions on NaN).
xscmpuqp	xscmpuqp BF, vA, vB	X-form	Compares Quad floats (Non-signaling on NaN).
xscpsgnqp	xscpsgnqp vD, vA, vB	X-form	Copies sign from B to A (128-bit).
xscvdphp	xscvdphp XT, XB	XX2-form	Converts a 64-bit double to 16-bit float.
xscvdpqp	xscvdpqp vD, vB	X-form	Converts a 64-bit Double to a 128-bit Quad float.
xscvdpsp	xscvdpsp XT, XB	XX2-form	Demotes a Double to a Single.
xscvdpsxds	xscvdpsxds XT, XB	XX2-form	Converts scalar Double to 64-bit Signed Integer.
xscvdpuxds	xscvdpuxds XT, XB	XX2-form	Converts scalar Double to 64-bit Unsigned Integer.
xscvhpdp	xscvhpdp XT, XB	XX2-form	Converts a 16-bit float to 64-bit double.
xscvqpdp	xscvqpdp vD, vB	X-form	Demotes 128-bit Float to 64-bit Float.
xscvqpsd	xscvqpsd vD, vB	X-form	Converts 128-bit Float to 64-bit Signed Integer.
xscvqpud	xscvqpud vD, vB	X-form	Converts 128-bit Float to 64-bit Unsigned Integer.
xscvsdqp	xscvsdqp vD, vB	X-form	Converts 64-bit Signed Integer to 128-bit Float.
xscvspdp	xscvspdp XT, XB	XX2-form	Promotes a Single to a Double.
xscvudqp	xscvudqp vD, vB	X-form	Converts 64-bit Unsigned Integer to 128-bit Float.
xsdivqp	xsdivqp vD, vA, vB	X-form	Divides two 128-bit Quad-Precision floats.
xsdivqpo	xsdivqpo vD, vA, vB	X-form	Used for Quad-Precision arithmetic on hardware that splits quads.
xsdivsp	xsdivsp XT, XA, XB	XX3-form	Scalar float division (32-bit).
xsiexpdp	xsiexpdp XT, XA, XB	XX3-form	Inserts exponent from one double into another.
xsmaxcdp	xsmaxcdp XT, XA, XB	XX3-form	Max of two doubles (IEEE 754-2008 compliant).
xsmaxcqp	xsmaxcqp vD, vA, vB	X-form	Max of Quad float (IEEE 754-2008 specific rules).
xsmaxdp	xsmaxdp XT, XA, XB	XX3-form	Scalar maximum (64-bit float).
xsmaxjdp	xsmaxjdp XT, XA, XB	XX3-form	Max of two doubles (Java compliant).
xsmaxqp	xsmaxqp vD, vA, vB	X-form	Selects maximum of two Quad floats.
xsmincdp	xsmincdp XT, XA, XB	XX3-form	Min of two doubles (IEEE 754-2008 compliant).
xsmincqp	xsmincqp vD, vA, vB	X-form	Min of Quad float (IEEE 754-2008 specific rules).
xsmindp	xsmindp XT, XA, XB	XX3-form	Scalar minimum (64-bit float).
xsminjdp	xsminjdp XT, XA, XB	XX3-form	Min of two doubles (Java compliant).
xsminqp	xsminqp vD, vA, vB	X-form	Selects minimum of two Quad floats.
xsmulqp	xsmulqp vD, vA, vB	X-form	Multiplies two 128-bit Quad-Precision floating-point numbers.
xsmulsp	xsmulsp XT, XA, XB	XX3-form	Scalar float multiplication (32-bit).
xsnegdp	xsnegdp XT, XB	XX2-form	Scalar negation (64-bit float).
xsnegqp	xsnegqp vD, vB	X-form	Negates a 128-bit Quad float.
xsrintqp	xsrintqp vD, vB	X-form	Rounds Quad float to nearest Integer.
xsrqpi	xsrqpi vD, vB, R	Z23-form	Rounds a Quad float to a Quad integer.
xsrqpix	xsrqpix vD, vB, R	Z23-form	Rounds a Quad float to a Quad integer (Exact).
xssqrtdp	xssqrtdp XT, XB	XX2-form	Scalar square root (64-bit float).
xssqrtqp	xssqrtqp vD, vB	X-form	Computes square root of a 128-bit Quad-Precision float.
xssqrtqpo	xssqrtqpo vD, vB	X-form	Used for Quad-Precision arithmetic on hardware that splits quads.
xssubqp	xssubqp vD, vA, vB	X-form	Subtracts two 128-bit Quad-Precision floats.
xssubqpo	xssubqpo vD, vA, vB	X-form	Used for Quad-Precision arithmetic on hardware that splits quads.
xssubsp	xssubsp XT, XA, XB	XX3-form	Scalar float subtraction (32-bit).
xststdcdp	xststdcdp BF, XB, DCM	XX2-form	Tests if a double falls into a specific class (NaN, Inf, Zero, Denormal).
xststdcqp	xststdcqp BF, vB, DCM	X-form	Tests class of Quad float (NaN/Inf/Zero).
xststdcsp	xststdcsp BF, vB, DCM	XX2-form	Tests a Single-Precision float for class membership (NaN, Inf, etc.).
xsxexpdp	xsxexpdp XT, XB	XX2-form	Extracts exponent from double as an integer.
xsxsigdp	xsxsigdp XT, XB	XX2-form	Extracts significand from double as an integer.
xvabsdp	xvabsdp XT, XB	XX2-form	Computes absolute value for two double-precision floats.
xvabssp	xvabssp XT, XB	XX2-form	Computes absolute value for four single-precision floats.
xvadddp	xvadddp XT, XA, XB	XX3-form	Adds two pairs of double-precision floating-point numbers.
xvaddsp	xvaddsp XT, XA, XB	XX3-form	Adds four single-precision floats.
xvbf16ger2	xvbf16ger2 AT, XA, XB	XX3-form	Performs BFloat16 (Brain Float) matrix multiply accumulate.
xvcmpeqdp	xvcmpeqdp XT, XA, XB	XX3-form	Compares doubles for equality. Sets result to all 1s or 0s.
xvcmpeqsp	xvcmpeqsp XT, XA, XB	XX3-form	Compares four floats for equality.
xvcmpgedp	xvcmpgedp XT, XA, XB	XX3-form	Compares doubles (A >= B).
xvcmpgesp	xvcmpgesp XT, XA, XB	XX3-form	Compares four floats (A >= B).
xvcmpgtdp	xvcmpgtdp XT, XA, XB	XX3-form	Compares doubles (A > B).
xvcmpgtsp	xvcmpgtsp XT, XA, XB	XX3-form	Compares four floats (A > B).
xvcvdpsp	xvcvdpsp XT, XB	XX2-form	Converts two doubles to two floats.
xvcvdpsxds	xvcvdpsxds XT, XB	XX2-form	Converts two doubles to two 64-bit signed integers.
xvcvdpuxds	xvcvdpuxds XT, XB	XX2-form	Converts two doubles to two 64-bit unsigned integers.
xvcvhpsp	xvcvhpsp XT, XB	XX2-form	Converts four 16-bit floats to four 32-bit floats.
xvcvspdp	xvcvspdp XT, XB	XX2-form	Converts two floats to two doubles.
xvcvsphp	xvcvsphp XT, XB	XX2-form	Converts four 32-bit floats to four 16-bit floats.
xvcvspsxds	xvcvspsxds XT, XB	XX2-form	Converts two floats to two 64-bit signed integers.
xvcvsxwsp	xvcvsxwsp XT, XB	XX2-form	Converts four 32-bit signed integers to four floats.
xvcvuxwsp	xvcvuxwsp XT, XB	XX2-form	Converts four 32-bit unsigned integers to four floats.
xvdivdp	xvdivdp XT, XA, XB	XX3-form	Divides two pairs of double-precision floats.
xvdivsp	xvdivsp XT, XA, XB	XX3-form	Divides four single-precision floats.
xvf16ger2	xvf16ger2 AT, XA, XB	XX3-form	Performs IEEE Float16 matrix multiply accumulate.
xvf32ger	xvf32ger AT, XA, XB	XX3-form	Performs Single-Precision Float matrix multiply accumulate.
xvf64ger	xvf64ger AT, XA, XB	XX3-form	Performs Double-Precision Float matrix multiply accumulate.
xvi16ger2	xvi16ger2 AT, XA, XB	XX3-form	Performs a 16-bit integer outer product and accumulates.
xvi16ger2s	xvi16ger2s AT, XA, XB	XX3-form	Performs a 16-bit integer outer product with saturation.
xvi4ger8	xvi4ger8 AT, XA, XB	XX3-form	Performs 4-bit integer matrix multiply accumulate (AI Quantization).
xvi4ger8pp	xvi4ger8pp AT, XA, XB	XX3-form	Unsigned 4-bit integer matrix multiply accumulate.
xvi8ger4	xvi8ger4 AT, XA, XB	XX3-form	Performs an 8-bit integer outer product (GER) and accumulates into a 512-bit register.
xvi8ger4pp	xvi8ger4pp AT, XA, XB	XX3-form	Signed/Unsigned variations of 8-bit matrix multiply accumulate.
xvmaddadp	xvmaddadp XT, XA, XB	XX3-form	Performs (A * B) + T on vectors of doubles.
xvmaxdp	xvmaxdp XT, XA, XB	XX3-form	Selects maximum value for two pairs of doubles.
xvmaxsp	xvmaxsp XT, XA, XB	XX3-form	Selects maximum value for four floats.
xvmindp	xvmindp XT, XA, XB	XX3-form	Selects minimum value for two pairs of doubles.
xvminsp	xvminsp XT, XA, XB	XX3-form	Selects minimum value for four floats.
xvmuldp	xvmuldp XT, XA, XB	XX3-form	Multiplies two pairs of double-precision floats.
xvmulsp	xvmulsp XT, XA, XB	XX3-form	Multiplies four single-precision floats.
xvnegdp	xvnegdp XT, XB	XX2-form	Negates two double-precision floats.
xvnegsp	xvnegsp XT, XB	XX2-form	Negates four single-precision floats.
xvsqrtdp	xvsqrtdp XT, XB	XX2-form	Computes square root for two double-precision floats.
xvsqrtsp	xvsqrtsp XT, XB	XX2-form	Computes square root for four single-precision floats.
xvsubdp	xvsubdp XT, XA, XB	XX3-form	Subtracts two pairs of double-precision floats. (vD = vA - vB)
xvsubsp	xvsubsp XT, XA, XB	XX3-form	Subtracts four single-precision floats.
xxblendvb	xxblendvb XT, XA, XB, XC	XX4-form	Selects bytes from XA or XB based on the MSB of bytes in XC.
xxblendvd	xxblendvd XT, XA, XB, XC	XX4-form	Selects doublewords from XA or XB based on the MSB of doublewords in XC.
xxblendvh	xxblendvh XT, XA, XB, XC	XX4-form	Selects halfwords from XA or XB based on the MSB of halfwords in XC.
xxblendvw	xxblendvw XT, XA, XB, XC	XX4-form	Selects words from XA or XB based on the MSB of words in XC.
xxeval	xxeval XT, XA, XB, XC, IMM	8RR:XX4-form	Performs an arbitrary 3-input boolean logic function (LUT3) on vectors. The 8-bit immediate 'IMM' defines the truth table.
xxextractuw	xxextractuw RT, XS, UIM	XX2-form	Extracts a 32-bit word from a VSR into a GPR.
xxgenpcvbm	xxgenpcvbm XT, XB, IMM	XX2-form	Generates a Permute Control Vector from a byte mask.
xxgenpcvdm	xxgenpcvdm XT, XB, IMM	XX2-form	Generates a Permute Control Vector from a doubleword mask.
xxgenpcvhm	xxgenpcvhm XT, XB, IMM	XX2-form	Generates a Permute Control Vector from a halfword mask.
xxgenpcvwm	xxgenpcvwm XT, XB, IMM	XX2-form	Generates a Permute Control Vector from a word mask.
xxinsertw	xxinsertw XT, RB, UIM	XX2-form	Inserts a 32-bit word from a GPR into a specific element of a VSR.
xxland	xxland XT, XA, XB	XX3-form	Bitwise AND.
xxlandc	xxlandc XT, XA, XB	XX3-form	vD = vA & ~vB
xxleqv	xxleqv XT, XA, XB	XX3-form	vD = ~(vA ^ vB) (XNOR)
xxlnand	xxlnand XT, XA, XB	XX3-form	vD = ~(vA & vB)
xxlnor	xxlnor XT, XA, XB	XX3-form	Bitwise NOR.
xxlor	xxlor XT, XA, XB	XX3-form	Bitwise OR.
xxlorc	xxlorc XT, XA, XB	XX3-form	vD = vA | ~vB
xxlxor	xxlxor XT, XA, XB	XX3-form	Bitwise XOR.
xxmfacc	xxmfacc AT	X-form	Copies data from an Accumulator back to 4 adjacent VSRs.
xxmrghd	xxmrghd XT, XA, XB	XX3-form	Merges high doublewords from XA and XB.
xxmrghw	xxmrghw XT, XA, XB	XX3-form	Merges high words from two VSRs.
xxmrgld	xxmrgld XT, XA, XB	XX3-form	Merges low doublewords from XA and XB.
xxmrglw	xxmrglw XT, XA, XB	XX3-form	Merges low words from two VSRs.
xxmtacc	xxmtacc AT	X-form	Copies data from 4 adjacent VSRs into an Accumulator.
xxperm	xxperm XT, XA, XB, XC	XX4-form	General permute for VSX registers.
xxpermdi	xxpermdi XT, XA, XB, DM	XX3-form	Selects two doublewords from the four available in source registers XA and XB based on a 2-bit selector.
xxpermr	xxpermr XT, XA, XB, XC	XX4-form	Little-endian optimized permute.
xxpermx	xxpermx XT, XA, XB, XC, UIM	XX4-form	Permutes bytes from two source vectors using a control vector and a 3-bit selector.
xxsel	xxsel XT, XA, XB, XC	XX4-form	Bitwise select between XA and XB based on XC.
xxsetaccz	xxsetaccz AT	X-form	Clears a 512-bit Accumulator register (composed of 4 VSRs) to zero.
xxsplti32dx	xxsplti32dx XT, IX, IMM	8RR:D-form	Splats a 32-bit immediate into a doubleword index.
xxspltib	xxspltib XT, IMM	X-form	Splats an 8-bit immediate into all bytes.
xxspltidp	xxspltidp XT, IMM	8RR:D-form	Spatially duplicates a 32-bit immediate (converted to double) into both double elements.
xxspltiw	xxspltiw XT, IMM	8RR:D-form	Spatially duplicates a 32-bit immediate into all 4 words of the target.
xxspltw	xxspltw XT, XS, UIM	XX2-form	Replicates one word element across the entire vector.
xxswapd	xxswapd XT, XB	XX2-form	Swaps the two doublewords in the register.