# ISA Database

> The modern, free reference for CPU and GPU instruction sets. 6,468 instructions documented across 4 CPU and 2 GPU architectures, with 73 cross-architecture concept mappings linking equivalent operations between them.

## Architectures

- [PowerISA](https://instructionsets.com/powerisa/): 1,187 instructions. A native, general-purpose CPU instruction set architecture spanning embedded, server, and HPC implementations.
- [x86](https://instructionsets.com/x86/): 957 instructions. The dominant native CPU instruction set architecture for desktop, server, and laptop computing.
- [ARM](https://instructionsets.com/arm/): 1,145 instructions. A native, license-based CPU instruction set architecture powering mobile, embedded, and increasingly server and desktop systems.
- [RISC-V](https://instructionsets.com/risc-v/): 547 instructions. An open, royalty-free native CPU instruction set architecture with a modular base-plus-extensions design.
- [PTX](https://instructionsets.com/ptx/): 190 instructions. A portable, low-level virtual GPU instruction set that NVIDIA's compiler stack lowers to a native target architecture (SASS) at install- or run-time. PTX is versioned text, not a stable binary encoding - the same PTX instruction can compile to different native machine code depending on the selected target.
- [AMDGPU](https://instructionsets.com/amdgpu/): 2,442 instructions. AMD's native, low-level GPU instruction set family, assembled directly (no virtual intermediate layer). Supported instructions and their exact encodings vary by GFX compatibility target.

## Cross-Architecture Comparisons

- [GPU concept comparisons](https://instructionsets.com/compare/): maps equivalent operations (e.g. atomic add, warp/wavefront shuffle, matrix multiply) between NVIDIA PTX and AMDGPU/GFX, 73 mappings total.
- [CPU cross-ISA comparisons](https://instructionsets.com/compare/cpu/): 42 operations compared across x86, ARM, RISC-V, and PowerISA, including where an architecture has no instruction for an operation and why.

## Browse by Extension

- [PowerISA extensions](https://instructionsets.com/powerisa/extensions/): 12 ISA extensions, each listing every instruction it introduces.
- [x86 extensions](https://instructionsets.com/x86/extensions/): 109 ISA extensions, each listing every instruction it introduces.
- [ARM extensions](https://instructionsets.com/arm/extensions/): 75 ISA extensions, each listing every instruction it introduces.
- [RISC-V extensions](https://instructionsets.com/risc-v/extensions/): 42 ISA extensions, each listing every instruction it introduces.

## Browse by Category

- [PTX categories](https://instructionsets.com/ptx/categories/): 24 functional categories, each listing every instruction in it.
- [AMDGPU categories](https://instructionsets.com/amdgpu/categories/): 19 functional categories, each listing every instruction in it.

## Compiler Intrinsics

- [x86 intrinsics](https://instructionsets.com/x86/intrinsics/): 3,623 compiler intrinsics from the Intel SDM, each mapped to the instruction it compiles to. The site search matches intrinsic names directly.

## Reference

- [Decoder](https://instructionsets.com/decode/): paste a 32-bit ARM or RISC-V instruction word, or a 32, 64 or 96-bit AMDGPU instruction for a chosen GPU generation, and get the mnemonic with every field broken out. Only encodings whose bit pattern rebuilds their own stored opcode are included.
- [Dataset](https://instructionsets.com/data/): the whole corpus as JSON and JSONL, released into the public domain under CC0. No permission or attribution required. Ships its own licence, dataset card and accuracy report.
- [API](https://instructionsets.com/api/): a JSON API with one URL per mnemonic, for example https://instructionsets.com/api/v1/x86/add.json, returning every record for it. No key, cross-origin reads allowed, same public-domain records as the dataset, with a JSON Schema at https://instructionsets.com/api/v1/schema.json.
- [Sitemap](https://instructionsets.com/sitemap.xml): every instruction page on the site (7,076 total pages).
- [What's new](https://instructionsets.com/changes/): dated changes to the site and data, also as an RSS feed at https://instructionsets.com/changes/feed.xml.

## Notes

- [What a zero is worth: checking a GPU decoder](https://instructionsets.com/notes/checking-the-gpu-decoder/): The AMD GPU decoder was checked against 162,054 lines LLVM assembled and named none of them wrongly. How far that zero reaches, why most lines get no answer, and the first version of the check, which would have reported zero while checking nothing.
- [Measuring the reference instead of the data](https://instructionsets.com/notes/measuring-the-reference/): How we measured the accuracy of an instruction reference built by a language model, the 18 wrong RISC-V encodings it found, and the four times the audit itself was the problem.