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[RDI].","page":"https://instructionsets.com/x86/cmpsq/","api":"https://instructionsets.com/api/v1/x86/cmpsq.json"},{"mnemonic":"cmpss","slug":"cmpss","records":1,"summary":"Compares low single-precision values and returns mask.","page":"https://instructionsets.com/x86/cmpss/","api":"https://instructionsets.com/api/v1/x86/cmpss.json"},{"mnemonic":"cmpsw","slug":"cmpsw","records":1,"summary":"Compares word at [ESI] with [EDI].","page":"https://instructionsets.com/x86/cmpsw/","api":"https://instructionsets.com/api/v1/x86/cmpsw.json"},{"mnemonic":"cmpxchg","slug":"cmpxchg","records":1,"summary":"Compares accumulator with dest; if equal, dest = src; else accumulator = dest.","page":"https://instructionsets.com/x86/cmpxchg/","api":"https://instructionsets.com/api/v1/x86/cmpxchg.json"},{"mnemonic":"cmpxchg16b","slug":"cmpxchg16b","records":1,"summary":"Atomically compares 128-bit memory with RDX:RAX.","page":"https://instructionsets.com/x86/cmpxchg16b/","api":"https://instructionsets.com/api/v1/x86/cmpxchg16b.json"},{"mnemonic":"cmpxchg8b","slug":"cmpxchg8b","records":1,"summary":"Atomically compares EDX:EAX with memory; swaps if equal.","page":"https://instructionsets.com/x86/cmpxchg8b/","api":"https://instructionsets.com/api/v1/x86/cmpxchg8b.json"},{"mnemonic":"comisd","slug":"comisd","records":1,"summary":"Compares low double and sets EFLAGS (Signaling NaN raises exception).","page":"https://instructionsets.com/x86/comisd/","api":"https://instructionsets.com/api/v1/x86/comisd.json"},{"mnemonic":"comiss","slug":"comiss","records":1,"summary":"Compares low float and sets EFLAGS (Signaling NaN raises exception).","page":"https://instructionsets.com/x86/comiss/","api":"https://instructionsets.com/api/v1/x86/comiss.json"},{"mnemonic":"cpuid","slug":"cpuid","records":1,"summary":"Returns processor information based on EAX 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floats.","page":"https://instructionsets.com/x86/cvtdq2ps/","api":"https://instructionsets.com/api/v1/x86/cvtdq2ps.json"},{"mnemonic":"cvtpd2dq","slug":"cvtpd2dq","records":1,"summary":"Converts two doubles to two 32-bit integers (Rounded).","page":"https://instructionsets.com/x86/cvtpd2dq/","api":"https://instructionsets.com/api/v1/x86/cvtpd2dq.json"},{"mnemonic":"cvtpd2ps","slug":"cvtpd2ps","records":1,"summary":"Converts two doubles to two floats.","page":"https://instructionsets.com/x86/cvtpd2ps/","api":"https://instructionsets.com/api/v1/x86/cvtpd2ps.json"},{"mnemonic":"cvtps2dq","slug":"cvtps2dq","records":1,"summary":"Converts four floats to 32-bit integers (Rounded).","page":"https://instructionsets.com/x86/cvtps2dq/","api":"https://instructionsets.com/api/v1/x86/cvtps2dq.json"},{"mnemonic":"cvtps2pd","slug":"cvtps2pd","records":1,"summary":"Converts lower two floats to doubles.","page":"https://instructionsets.com/x86/cvtps2pd/","api":"https://instructionsets.com/api/v1/x86/cvtps2pd.json"},{"mnemonic":"cvtsd2si","slug":"cvtsd2si","records":1,"summary":"Converts low double to integer (Rounded according to MXCSR).","page":"https://instructionsets.com/x86/cvtsd2si/","api":"https://instructionsets.com/api/v1/x86/cvtsd2si.json"},{"mnemonic":"cvtsd2sq","slug":"cvtsd2sq","records":1,"summary":"Converts double to 64-bit integer (Rounded).","page":"https://instructionsets.com/x86/cvtsd2sq/","api":"https://instructionsets.com/api/v1/x86/cvtsd2sq.json"},{"mnemonic":"cvtsd2ss","slug":"cvtsd2ss","records":1,"summary":"Converts double to float.","page":"https://instructionsets.com/x86/cvtsd2ss/","api":"https://instructionsets.com/api/v1/x86/cvtsd2ss.json"},{"mnemonic":"cvtsi2sd","slug":"cvtsi2sd","records":1,"summary":"Converts 32-bit int to double.","page":"https://instructionsets.com/x86/cvtsi2sd/","api":"https://instructionsets.com/api/v1/x86/cvtsi2sd.json"},{"mnemonic":"cvtsi2ss","slug":"cvtsi2ss","records":1,"summary":"Converts 32-bit int to float.","page":"https://instructionsets.com/x86/cvtsi2ss/","api":"https://instructionsets.com/api/v1/x86/cvtsi2ss.json"},{"mnemonic":"cvtsq2sd","slug":"cvtsq2sd","records":1,"summary":"Converts 64-bit integer to double.","page":"https://instructionsets.com/x86/cvtsq2sd/","api":"https://instructionsets.com/api/v1/x86/cvtsq2sd.json"},{"mnemonic":"cvtsq2ss","slug":"cvtsq2ss","records":1,"summary":"Converts 64-bit integer to float.","page":"https://instructionsets.com/x86/cvtsq2ss/","api":"https://instructionsets.com/api/v1/x86/cvtsq2ss.json"},{"mnemonic":"cvtss2sd","slug":"cvtss2sd","records":1,"summary":"Converts float to double.","page":"https://instructionsets.com/x86/cvtss2sd/","api":"https://instructionsets.com/api/v1/x86/cvtss2sd.json"},{"mnemonic":"cvtss2si","slug":"cvtss2si","records":1,"summary":"Converts low float to integer (Rounded according to MXCSR).","page":"https://instructionsets.com/x86/cvtss2si/","api":"https://instructionsets.com/api/v1/x86/cvtss2si.json"},{"mnemonic":"cvtss2sq","slug":"cvtss2sq","records":1,"summary":"Converts float to 64-bit integer (Rounded).","page":"https://instructionsets.com/x86/cvtss2sq/","api":"https://instructionsets.com/api/v1/x86/cvtss2sq.json"},{"mnemonic":"cvttpd2dq","slug":"cvttpd2dq","records":1,"summary":"Converts two doubles to two 32-bit integers (Truncated).","page":"https://instructionsets.com/x86/cvttpd2dq/","api":"https://instructionsets.com/api/v1/x86/cvttpd2dq.json"},{"mnemonic":"cvttps2dq","slug":"cvttps2dq","records":1,"summary":"Converts four floats to 32-bit integers (Truncated).","page":"https://instructionsets.com/x86/cvttps2dq/","api":"https://instructionsets.com/api/v1/x86/cvttps2dq.json"},{"mnemonic":"cvttps2pi","slug":"cvttps2pi","records":1,"summary":"Converts packed floats to packed MMX integers (Truncate).","page":"https://instructionsets.com/x86/cvttps2pi/","api":"https://instructionsets.com/api/v1/x86/cvttps2pi.json"},{"mnemonic":"cvttsd2si","slug":"cvttsd2si","records":1,"summary":"Converts double to 32-bit int (Truncate).","page":"https://instructionsets.com/x86/cvttsd2si/","api":"https://instructionsets.com/api/v1/x86/cvttsd2si.json"},{"mnemonic":"cvttsd2sq","slug":"cvttsd2sq","records":1,"summary":"Converts double to 64-bit integer (Truncated).","page":"https://instructionsets.com/x86/cvttsd2sq/","api":"https://instructionsets.com/api/v1/x86/cvttsd2sq.json"},{"mnemonic":"cvttss2si","slug":"cvttss2si","records":1,"summary":"Converts float to 32-bit int (Truncate).","page":"https://instructionsets.com/x86/cvttss2si/","api":"https://instructionsets.com/api/v1/x86/cvttss2si.json"},{"mnemonic":"cvttss2sq","slug":"cvttss2sq","records":1,"summary":"Converts float to 64-bit integer (Truncated).","page":"https://instructionsets.com/x86/cvttss2sq/","api":"https://instructionsets.com/api/v1/x86/cvttss2sq.json"},{"mnemonic":"cwd","slug":"cwd","records":1,"summary":"Sign-extends AX into DX:AX.","page":"https://instructionsets.com/x86/cwd/","api":"https://instructionsets.com/api/v1/x86/cwd.json"},{"mnemonic":"cwtl","slug":"cwtl","records":1,"summary":"Sign-extends AX into EAX (also CWDE).","page":"https://instructionsets.com/x86/cwtl/","api":"https://instructionsets.com/api/v1/x86/cwtl.json"},{"mnemonic":"daa","slug":"daa","records":1,"summary":"Adjusts AL after addition for packed BCD.","page":"https://instructionsets.com/x86/daa/","api":"https://instructionsets.com/api/v1/x86/daa.json"},{"mnemonic":"das","slug":"das","records":1,"summary":"Adjusts AL after subtraction for packed BCD.","page":"https://instructionsets.com/x86/das/","api":"https://instructionsets.com/api/v1/x86/das.json"},{"mnemonic":"dec","slug":"dec","records":1,"summary":"Decrements the operand by 1.","page":"https://instructionsets.com/x86/dec/","api":"https://instructionsets.com/api/v1/x86/dec.json"},{"mnemonic":"div","slug":"div","records":1,"summary":"Unsigned divide (AX / src).","page":"https://instructionsets.com/x86/div/","api":"https://instructionsets.com/api/v1/x86/div.json"},{"mnemonic":"divpd","slug":"divpd","records":1,"summary":"Divides two 64-bit doubles.","page":"https://instructionsets.com/x86/divpd/","api":"https://instructionsets.com/api/v1/x86/divpd.json"},{"mnemonic":"divps","slug":"divps","records":1,"summary":"Divides four 32-bit floats.","page":"https://instructionsets.com/x86/divps/","api":"https://instructionsets.com/api/v1/x86/divps.json"},{"mnemonic":"divsd","slug":"divsd","records":1,"summary":"Divides the low double-precision floating-point value.","page":"https://instructionsets.com/x86/divsd/","api":"https://instructionsets.com/api/v1/x86/divsd.json"},{"mnemonic":"divss","slug":"divss","records":1,"summary":"Divides the low single-precision floating-point value.","page":"https://instructionsets.com/x86/divss/","api":"https://instructionsets.com/api/v1/x86/divss.json"},{"mnemonic":"dppd","slug":"dppd","records":1,"summary":"Computes the dot product of two double vectors.","page":"https://instructionsets.com/x86/dppd/","api":"https://instructionsets.com/api/v1/x86/dppd.json"},{"mnemonic":"dpps","slug":"dpps","records":1,"summary":"Computes the dot product of two float vectors.","page":"https://instructionsets.com/x86/dpps/","api":"https://instructionsets.com/api/v1/x86/dpps.json"},{"mnemonic":"emms","slug":"emms","records":1,"summary":"Clears the FPU tag word to allow FP instructions after MMX.","page":"https://instructionsets.com/x86/emms/","api":"https://instructionsets.com/api/v1/x86/emms.json"},{"mnemonic":"encls","slug":"encls","records":1,"summary":"Executes an SGX supervisor function specified by EAX.","page":"https://instructionsets.com/x86/encls/","api":"https://instructionsets.com/api/v1/x86/encls.json"},{"mnemonic":"enclu","slug":"enclu","records":1,"summary":"Executes an SGX user function specified by EAX.","page":"https://instructionsets.com/x86/enclu/","api":"https://instructionsets.com/api/v1/x86/enclu.json"},{"mnemonic":"encodekey128","slug":"encodekey128","records":1,"summary":"Wraps a 128-bit AES key into a handle.","page":"https://instructionsets.com/x86/encodekey128/","api":"https://instructionsets.com/api/v1/x86/encodekey128.json"},{"mnemonic":"encodekey256","slug":"encodekey256","records":1,"summary":"Wraps a 256-bit AES key into a handle.","page":"https://instructionsets.com/x86/encodekey256/","api":"https://instructionsets.com/api/v1/x86/encodekey256.json"},{"mnemonic":"endbr32","slug":"endbr32","records":1,"summary":"Marker instruction for Indirect Branch Tracking (IBT).","page":"https://instructionsets.com/x86/endbr32/","api":"https://instructionsets.com/api/v1/x86/endbr32.json"},{"mnemonic":"endbr64","slug":"endbr64","records":1,"summary":"Marker instruction for Indirect Branch Tracking (IBT).","page":"https://instructionsets.com/x86/endbr64/","api":"https://instructionsets.com/api/v1/x86/endbr64.json"},{"mnemonic":"enqcmd","slug":"enqcmd","records":1,"summary":"Writes a command to a device (DSA/IAA accelerator).","page":"https://instructionsets.com/x86/enqcmd/","api":"https://instructionsets.com/api/v1/x86/enqcmd.json"},{"mnemonic":"enqcmds","slug":"enqcmds","records":1,"summary":"Writes a command to a device (Supervisor mode).","page":"https://instructionsets.com/x86/enqcmds/","api":"https://instructionsets.com/api/v1/x86/enqcmds.json"},{"mnemonic":"enter","slug":"enter","records":1,"summary":"Creates a stack frame for procedure parameters.","page":"https://instructionsets.com/x86/enter/","api":"https://instructionsets.com/api/v1/x86/enter.json"},{"mnemonic":"erets","slug":"erets","records":1,"summary":"Returns from an event handler to supervisor mode (FRED).","page":"https://instructionsets.com/x86/erets/","api":"https://instructionsets.com/api/v1/x86/erets.json"},{"mnemonic":"eretu","slug":"eretu","records":1,"summary":"Returns from an event handler to user mode (FRED).","page":"https://instructionsets.com/x86/eretu/","api":"https://instructionsets.com/api/v1/x86/eretu.json"},{"mnemonic":"extractps","slug":"extractps","records":1,"summary":"Extracts a single float from XMM to an integer register.","page":"https://instructionsets.com/x86/extractps/","api":"https://instructionsets.com/api/v1/x86/extractps.json"},{"mnemonic":"extrq","slug":"extrq","records":1,"summary":"Extracts bit field from register (AMD SSE4a).","page":"https://instructionsets.com/x86/extrq/","api":"https://instructionsets.com/api/v1/x86/extrq.json"},{"mnemonic":"f2xm1","slug":"f2xm1","records":1,"summary":"Computes (2^ST(0)) - 1.","page":"https://instructionsets.com/x86/f2xm1/","api":"https://instructionsets.com/api/v1/x86/f2xm1.json"},{"mnemonic":"fabs","slug":"fabs","records":1,"summary":"Replaces ST(0) with its absolute value.","page":"https://instructionsets.com/x86/fabs/","api":"https://instructionsets.com/api/v1/x86/fabs.json"},{"mnemonic":"fadd","slug":"fadd","records":1,"summary":"Adds src to dest (ST(0) += src).","page":"https://instructionsets.com/x86/fadd/","api":"https://instructionsets.com/api/v1/x86/fadd.json"},{"mnemonic":"fchs","slug":"fchs","records":1,"summary":"Reverses the sign of ST(0).","page":"https://instructionsets.com/x86/fchs/","api":"https://instructionsets.com/api/v1/x86/fchs.json"},{"mnemonic":"fclex","slug":"fclex","records":1,"summary":"Clears floating-point exception flags.","page":"https://instructionsets.com/x86/fclex/","api":"https://instructionsets.com/api/v1/x86/fclex.json"},{"mnemonic":"fcmovb","slug":"fcmovb","records":1,"summary":"Moves ST(i) to ST(0) if CF=1.","page":"https://instructionsets.com/x86/fcmovb/","api":"https://instructionsets.com/api/v1/x86/fcmovb.json"},{"mnemonic":"fcmovbe","slug":"fcmovbe","records":1,"summary":"Moves ST(i) to ST(0) if CF=1 or ZF=1.","page":"https://instructionsets.com/x86/fcmovbe/","api":"https://instructionsets.com/api/v1/x86/fcmovbe.json"},{"mnemonic":"fcmove","slug":"fcmove","records":1,"summary":"Moves ST(i) to ST(0) if ZF=1.","page":"https://instructionsets.com/x86/fcmove/","api":"https://instructionsets.com/api/v1/x86/fcmove.json"},{"mnemonic":"fcmovnb","slug":"fcmovnb","records":1,"summary":"Moves ST(i) to ST(0) if CF=0.","page":"https://instructionsets.com/x86/fcmovnb/","api":"https://instructionsets.com/api/v1/x86/fcmovnb.json"},{"mnemonic":"fcmovnbe","slug":"fcmovnbe","records":1,"summary":"Moves ST(i) to ST(0) if CF=0 and ZF=0.","page":"https://instructionsets.com/x86/fcmovnbe/","api":"https://instructionsets.com/api/v1/x86/fcmovnbe.json"},{"mnemonic":"fcmovne","slug":"fcmovne","records":1,"summary":"Moves ST(i) to ST(0) if ZF=0.","page":"https://instructionsets.com/x86/fcmovne/","api":"https://instructionsets.com/api/v1/x86/fcmovne.json"},{"mnemonic":"fcmovnu","slug":"fcmovnu","records":1,"summary":"Moves ST(i) to ST(0) if PF=0.","page":"https://instructionsets.com/x86/fcmovnu/","api":"https://instructionsets.com/api/v1/x86/fcmovnu.json"},{"mnemonic":"fcmovu","slug":"fcmovu","records":1,"summary":"Moves ST(i) to ST(0) if PF=1.","page":"https://instructionsets.com/x86/fcmovu/","api":"https://instructionsets.com/api/v1/x86/fcmovu.json"},{"mnemonic":"fcom","slug":"fcom","records":1,"summary":"Compares ST(0) with source.","page":"https://instructionsets.com/x86/fcom/","api":"https://instructionsets.com/api/v1/x86/fcom.json"},{"mnemonic":"fcomi","slug":"fcomi","records":1,"summary":"Compares ST(0) with ST(i) and sets CPU EFLAGS directly.","page":"https://instructionsets.com/x86/fcomi/","api":"https://instructionsets.com/api/v1/x86/fcomi.json"},{"mnemonic":"fcos","slug":"fcos","records":1,"summary":"Computes cosine of ST(0) (in radians).","page":"https://instructionsets.com/x86/fcos/","api":"https://instructionsets.com/api/v1/x86/fcos.json"},{"mnemonic":"fdecstp","slug":"fdecstp","records":1,"summary":"Decrements the TOP field in the FPU status word.","page":"https://instructionsets.com/x86/fdecstp/","api":"https://instructionsets.com/api/v1/x86/fdecstp.json"},{"mnemonic":"fdiv","slug":"fdiv","records":1,"summary":"Divides dest by src.","page":"https://instructionsets.com/x86/fdiv/","api":"https://instructionsets.com/api/v1/x86/fdiv.json"},{"mnemonic":"ffree","slug":"ffree","records":1,"summary":"Sets the tag for ST(i) to empty.","page":"https://instructionsets.com/x86/ffree/","api":"https://instructionsets.com/api/v1/x86/ffree.json"},{"mnemonic":"fild","slug":"fild","records":1,"summary":"Converts integer in memory to double-extended-precision float and pushes to ST(0).","page":"https://instructionsets.com/x86/fild/","api":"https://instructionsets.com/api/v1/x86/fild.json"},{"mnemonic":"fincstp","slug":"fincstp","records":1,"summary":"Increments the TOP field in the FPU status word.","page":"https://instructionsets.com/x86/fincstp/","api":"https://instructionsets.com/api/v1/x86/fincstp.json"},{"mnemonic":"finit","slug":"finit","records":1,"summary":"Resets FPU to default state.","page":"https://instructionsets.com/x86/finit/","api":"https://instructionsets.com/api/v1/x86/finit.json"},{"mnemonic":"fist","slug":"fist","records":1,"summary":"Converts ST(0) to integer and stores in memory.","page":"https://instructionsets.com/x86/fist/","api":"https://instructionsets.com/api/v1/x86/fist.json"},{"mnemonic":"fistp","slug":"fistp","records":1,"summary":"Converts ST(0) to integer, stores in memory, and pops stack.","page":"https://instructionsets.com/x86/fistp/","api":"https://instructionsets.com/api/v1/x86/fistp.json"},{"mnemonic":"fld","slug":"fld","records":1,"summary":"Pushes a floating-point value onto the FPU register stack (ST0).","page":"https://instructionsets.com/x86/fld/","api":"https://instructionsets.com/api/v1/x86/fld.json"},{"mnemonic":"fld1","slug":"fld1","records":1,"summary":"Pushes +1.0 onto the FPU register stack.","page":"https://instructionsets.com/x86/fld1/","api":"https://instructionsets.com/api/v1/x86/fld1.json"},{"mnemonic":"fldcw","slug":"fldcw","records":1,"summary":"Loads FPU control word from memory.","page":"https://instructionsets.com/x86/fldcw/","api":"https://instructionsets.com/api/v1/x86/fldcw.json"},{"mnemonic":"fldl2e","slug":"fldl2e","records":1,"summary":"Pushes log2(e) onto the FPU register stack.","page":"https://instructionsets.com/x86/fldl2e/","api":"https://instructionsets.com/api/v1/x86/fldl2e.json"},{"mnemonic":"fldl2t","slug":"fldl2t","records":1,"summary":"Pushes log2(10) onto the FPU register stack.","page":"https://instructionsets.com/x86/fldl2t/","api":"https://instructionsets.com/api/v1/x86/fldl2t.json"},{"mnemonic":"fldlg2","slug":"fldlg2","records":1,"summary":"Pushes log10(2) onto the FPU register stack.","page":"https://instructionsets.com/x86/fldlg2/","api":"https://instructionsets.com/api/v1/x86/fldlg2.json"},{"mnemonic":"fldln2","slug":"fldln2","records":1,"summary":"Pushes ln(2) onto the FPU register stack.","page":"https://instructionsets.com/x86/fldln2/","api":"https://instructionsets.com/api/v1/x86/fldln2.json"},{"mnemonic":"fldpi","slug":"fldpi","records":1,"summary":"Pushes Pi onto the FPU register stack.","page":"https://instructionsets.com/x86/fldpi/","api":"https://instructionsets.com/api/v1/x86/fldpi.json"},{"mnemonic":"fldz","slug":"fldz","records":1,"summary":"Pushes +0.0 onto the FPU register stack.","page":"https://instructionsets.com/x86/fldz/","api":"https://instructionsets.com/api/v1/x86/fldz.json"},{"mnemonic":"fmul","slug":"fmul","records":1,"summary":"Multiplies dest by src.","page":"https://instructionsets.com/x86/fmul/","api":"https://instructionsets.com/api/v1/x86/fmul.json"},{"mnemonic":"fpatan","slug":"fpatan","records":1,"summary":"Computes arctan(ST(1)/ST(0)).","page":"https://instructionsets.com/x86/fpatan/","api":"https://instructionsets.com/api/v1/x86/fpatan.json"},{"mnemonic":"fprem","slug":"fprem","records":1,"summary":"Computes remainder of ST(0) / ST(1).","page":"https://instructionsets.com/x86/fprem/","api":"https://instructionsets.com/api/v1/x86/fprem.json"},{"mnemonic":"fptan","slug":"fptan","records":1,"summary":"Computes tangent of ST(0) and pushes 1.0.","page":"https://instructionsets.com/x86/fptan/","api":"https://instructionsets.com/api/v1/x86/fptan.json"},{"mnemonic":"frndint","slug":"frndint","records":1,"summary":"Rounds ST(0) to integer according to RC field.","page":"https://instructionsets.com/x86/frndint/","api":"https://instructionsets.com/api/v1/x86/frndint.json"},{"mnemonic":"frstor","slug":"frstor","records":1,"summary":"Loads FPU state from memory.","page":"https://instructionsets.com/x86/frstor/","api":"https://instructionsets.com/api/v1/x86/frstor.json"},{"mnemonic":"fsave","slug":"fsave","records":1,"summary":"Stores FPU state to memory and re-initializes FPU.","page":"https://instructionsets.com/x86/fsave/","api":"https://instructionsets.com/api/v1/x86/fsave.json"},{"mnemonic":"fscale","slug":"fscale","records":1,"summary":"Scales ST(0) by ST(1) (ST(0) * 2^ST(1)).","page":"https://instructionsets.com/x86/fscale/","api":"https://instructionsets.com/api/v1/x86/fscale.json"},{"mnemonic":"fsin","slug":"fsin","records":1,"summary":"Computes sine of ST(0) (in radians).","page":"https://instructionsets.com/x86/fsin/","api":"https://instructionsets.com/api/v1/x86/fsin.json"},{"mnemonic":"fsincos","slug":"fsincos","records":1,"summary":"Computes sine and cosine of ST(0), pushing both to stack.","page":"https://instructionsets.com/x86/fsincos/","api":"https://instructionsets.com/api/v1/x86/fsincos.json"},{"mnemonic":"fsqrt","slug":"fsqrt","records":1,"summary":"Computes square root of ST(0).","page":"https://instructionsets.com/x86/fsqrt/","api":"https://instructionsets.com/api/v1/x86/fsqrt.json"},{"mnemonic":"fst","slug":"fst","records":1,"summary":"Copies the value in ST(0) to memory or another register.","page":"https://instructionsets.com/x86/fst/","api":"https://instructionsets.com/api/v1/x86/fst.json"},{"mnemonic":"fstcw","slug":"fstcw","records":1,"summary":"Stores FPU control word to memory.","page":"https://instructionsets.com/x86/fstcw/","api":"https://instructionsets.com/api/v1/x86/fstcw.json"},{"mnemonic":"fstp","slug":"fstp","records":1,"summary":"Copies ST(0) to destination and pops the register stack.","page":"https://instructionsets.com/x86/fstp/","api":"https://instructionsets.com/api/v1/x86/fstp.json"},{"mnemonic":"fstsw","slug":"fstsw","records":1,"summary":"Stores FPU status word to AX or memory.","page":"https://instructionsets.com/x86/fstsw/","api":"https://instructionsets.com/api/v1/x86/fstsw.json"},{"mnemonic":"fsub","slug":"fsub","records":1,"summary":"Subtracts src from dest.","page":"https://instructionsets.com/x86/fsub/","api":"https://instructionsets.com/api/v1/x86/fsub.json"},{"mnemonic":"fucom","slug":"fucom","records":1,"summary":"Compares ST(0) with source (supports NaNs).","page":"https://instructionsets.com/x86/fucom/","api":"https://instructionsets.com/api/v1/x86/fucom.json"},{"mnemonic":"fxch","slug":"fxch","records":1,"summary":"Exchanges contents of ST(0) and ST(i).","page":"https://instructionsets.com/x86/fxch/","api":"https://instructionsets.com/api/v1/x86/fxch.json"},{"mnemonic":"fxtract","slug":"fxtract","records":1,"summary":"Separates exponent and significand of ST(0).","page":"https://instructionsets.com/x86/fxtract/","api":"https://instructionsets.com/api/v1/x86/fxtract.json"},{"mnemonic":"fyl2x","slug":"fyl2x","records":1,"summary":"Computes ST(1) * log2(ST(0)).","page":"https://instructionsets.com/x86/fyl2x/","api":"https://instructionsets.com/api/v1/x86/fyl2x.json"},{"mnemonic":"fyl2xp1","slug":"fyl2xp1","records":1,"summary":"Computes ST(1) * log2(ST(0) + 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GF(2^8).","page":"https://instructionsets.com/x86/gf2p8mulb/","api":"https://instructionsets.com/api/v1/x86/gf2p8mulb.json"},{"mnemonic":"haddpd","slug":"haddpd","records":1,"summary":"Adds adjacent double-precision elements horizontally.","page":"https://instructionsets.com/x86/haddpd/","api":"https://instructionsets.com/api/v1/x86/haddpd.json"},{"mnemonic":"haddps","slug":"haddps","records":1,"summary":"Adds adjacent float elements horizontally.","page":"https://instructionsets.com/x86/haddps/","api":"https://instructionsets.com/api/v1/x86/haddps.json"},{"mnemonic":"hlt","slug":"hlt","records":1,"summary":"Stops instruction execution and places processor in HALT state.","page":"https://instructionsets.com/x86/hlt/","api":"https://instructionsets.com/api/v1/x86/hlt.json"},{"mnemonic":"hreset","slug":"hreset","records":1,"summary":"Resets processor history (prediction) structures.","page":"https://instructionsets.com/x86/hreset/","api":"https://instructionsets.com/api/v1/x86/hreset.json"},{"mnemonic":"hsubpd","slug":"hsubpd","records":1,"summary":"Subtracts adjacent double-precision elements horizontally.","page":"https://instructionsets.com/x86/hsubpd/","api":"https://instructionsets.com/api/v1/x86/hsubpd.json"},{"mnemonic":"hsubps","slug":"hsubps","records":1,"summary":"Subtracts adjacent single-precision elements horizontally.","page":"https://instructionsets.com/x86/hsubps/","api":"https://instructionsets.com/api/v1/x86/hsubps.json"},{"mnemonic":"idiv","slug":"idiv","records":1,"summary":"Signed divide (AX / src).","page":"https://instructionsets.com/x86/idiv/","api":"https://instructionsets.com/api/v1/x86/idiv.json"},{"mnemonic":"imul","slug":"imul","records":1,"summary":"Signed multiply.","page":"https://instructionsets.com/x86/imul/","api":"https://instructionsets.com/api/v1/x86/imul.json"},{"mnemonic":"in","slug":"in","records":2,"summary":"Reads data from an I/O port into AL/AX/EAX.","page":"https://instructionsets.com/x86/in/","api":"https://instructionsets.com/api/v1/x86/in.json"},{"mnemonic":"inc","slug":"inc","records":1,"summary":"Increments the operand by 1.","page":"https://instructionsets.com/x86/inc/","api":"https://instructionsets.com/api/v1/x86/inc.json"},{"mnemonic":"incsspq","slug":"incsspq","records":1,"summary":"Adjusts the shadow stack pointer.","page":"https://instructionsets.com/x86/incsspq/","api":"https://instructionsets.com/api/v1/x86/incsspq.json"},{"mnemonic":"ins","slug":"ins","records":1,"summary":"Reads string from I/O port to memory at [EDI].","page":"https://instructionsets.com/x86/ins/","api":"https://instructionsets.com/api/v1/x86/ins.json"},{"mnemonic":"insd","slug":"insd","records":1,"summary":"Reads doubleword from I/O port to memory at [EDI].","page":"https://instructionsets.com/x86/insd/","api":"https://instructionsets.com/api/v1/x86/insd.json"},{"mnemonic":"insertps","slug":"insertps","records":1,"summary":"Inserts a single float into a specific index of XMM.","page":"https://instructionsets.com/x86/insertps/","api":"https://instructionsets.com/api/v1/x86/insertps.json"},{"mnemonic":"insertq","slug":"insertq","records":1,"summary":"Inserts bit field into register (AMD SSE4a).","page":"https://instructionsets.com/x86/insertq/","api":"https://instructionsets.com/api/v1/x86/insertq.json"},{"mnemonic":"insw","slug":"insw","records":1,"summary":"Reads word from I/O port to memory at [EDI].","page":"https://instructionsets.com/x86/insw/","api":"https://instructionsets.com/api/v1/x86/insw.json"},{"mnemonic":"int","slug":"int","records":1,"summary":"Calls to interrupt procedure.","page":"https://instructionsets.com/x86/int/","api":"https://instructionsets.com/api/v1/x86/int.json"},{"mnemonic":"int1","slug":"int1","records":1,"summary":"Single byte opcode (0xF1) used for In-Circuit Emulation.","page":"https://instructionsets.com/x86/int1/","api":"https://instructionsets.com/api/v1/x86/int1.json"},{"mnemonic":"int3","slug":"int3","records":1,"summary":"Calls to interrupt vector 3 (Debugger breakpoint).","page":"https://instructionsets.com/x86/int3/","api":"https://instructionsets.com/api/v1/x86/int3.json"},{"mnemonic":"invd","slug":"invd","records":1,"summary":"Flushes internal caches without writing back data (Privileged).","page":"https://instructionsets.com/x86/invd/","api":"https://instructionsets.com/api/v1/x86/invd.json"},{"mnemonic":"invept","slug":"invept","records":1,"summary":"Invalidates Extended Page Table entries.","page":"https://instructionsets.com/x86/invept/","api":"https://instructionsets.com/api/v1/x86/invept.json"},{"mnemonic":"invlpg","slug":"invlpg","records":1,"summary":"Invalidates a specific TLB entry (Privileged).","page":"https://instructionsets.com/x86/invlpg/","api":"https://instructionsets.com/api/v1/x86/invlpg.json"},{"mnemonic":"invlpga","slug":"invlpga","records":1,"summary":"Invalidates TLB entry for specific ASID (AMD SVM).","page":"https://instructionsets.com/x86/invlpga/","api":"https://instructionsets.com/api/v1/x86/invlpga.json"},{"mnemonic":"invpcid","slug":"invpcid","records":1,"summary":"Invalidates TLB entries based on PCID.","page":"https://instructionsets.com/x86/invpcid/","api":"https://instructionsets.com/api/v1/x86/invpcid.json"},{"mnemonic":"invvpid","slug":"invvpid","records":1,"summary":"Invalidates TLB entries based on Virtual Processor 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>).","page":"https://instructionsets.com/x86/ja/","api":"https://instructionsets.com/api/v1/x86/ja.json"},{"mnemonic":"jb","slug":"jb","records":1,"summary":"Jump if CF=1 (Unsigned <).","page":"https://instructionsets.com/x86/jb/","api":"https://instructionsets.com/api/v1/x86/jb.json"},{"mnemonic":"je","slug":"je","records":1,"summary":"Jump if ZF=1 (Same as JZ).","page":"https://instructionsets.com/x86/je/","api":"https://instructionsets.com/api/v1/x86/je.json"},{"mnemonic":"jecxz","slug":"jecxz","records":1,"summary":"Jumps if ECX register is 0.","page":"https://instructionsets.com/x86/jecxz/","api":"https://instructionsets.com/api/v1/x86/jecxz.json"},{"mnemonic":"jg","slug":"jg","records":1,"summary":"Jump if ZF=0 and SF=OF (Signed >).","page":"https://instructionsets.com/x86/jg/","api":"https://instructionsets.com/api/v1/x86/jg.json"},{"mnemonic":"jl","slug":"jl","records":1,"summary":"Jump if SF!=OF (Signed <).","page":"https://instructionsets.com/x86/jl/","api":"https://instructionsets.com/api/v1/x86/jl.json"},{"mnemonic":"jmp","slug":"jmp","records":1,"summary":"Unconditional jump to target.","page":"https://instructionsets.com/x86/jmp/","api":"https://instructionsets.com/api/v1/x86/jmp.json"},{"mnemonic":"jne","slug":"jne","records":1,"summary":"Jump if ZF=0 (Same as JNZ).","page":"https://instructionsets.com/x86/jne/","api":"https://instructionsets.com/api/v1/x86/jne.json"},{"mnemonic":"jno","slug":"jno","records":1,"summary":"Jump near if overflow flag is 0.","page":"https://instructionsets.com/x86/jno/","api":"https://instructionsets.com/api/v1/x86/jno.json"},{"mnemonic":"jnp","slug":"jnp","records":1,"summary":"Jump near if parity flag is 0 (Odd parity).","page":"https://instructionsets.com/x86/jnp/","api":"https://instructionsets.com/api/v1/x86/jnp.json"},{"mnemonic":"jns","slug":"jns","records":1,"summary":"Jump near if sign flag is 0 (Positive).","page":"https://instructionsets.com/x86/jns/","api":"https://instructionsets.com/api/v1/x86/jns.json"},{"mnemonic":"jo","slug":"jo","records":1,"summary":"Jump near if overflow flag is 1.","page":"https://instructionsets.com/x86/jo/","api":"https://instructionsets.com/api/v1/x86/jo.json"},{"mnemonic":"jp","slug":"jp","records":1,"summary":"Jump near if parity flag is 1 (Even parity).","page":"https://instructionsets.com/x86/jp/","api":"https://instructionsets.com/api/v1/x86/jp.json"},{"mnemonic":"js","slug":"js","records":1,"summary":"Jump near if sign flag is 1 (Negative).","page":"https://instructionsets.com/x86/js/","api":"https://instructionsets.com/api/v1/x86/js.json"},{"mnemonic":"kaddb","slug":"kaddb","records":1,"summary":"Adds two 8-bit mask registers.","page":"https://instructionsets.com/x86/kaddb/","api":"https://instructionsets.com/api/v1/x86/kaddb.json"},{"mnemonic":"kaddw","slug":"kaddw","records":1,"summary":"Adds two 16-bit mask registers.","page":"https://instructionsets.com/x86/kaddw/","api":"https://instructionsets.com/api/v1/x86/kaddw.json"},{"mnemonic":"kandnw","slug":"kandnw","records":1,"summary":"Bitwise AND NOT of 16-bit masks.","page":"https://instructionsets.com/x86/kandnw/","api":"https://instructionsets.com/api/v1/x86/kandnw.json"},{"mnemonic":"kandq","slug":"kandq","records":1,"summary":"Bitwise AND of 64-bit mask registers.","page":"https://instructionsets.com/x86/kandq/","api":"https://instructionsets.com/api/v1/x86/kandq.json"},{"mnemonic":"kandw","slug":"kandw","records":1,"summary":"Bitwise AND of 16-bit masks.","page":"https://instructionsets.com/x86/kandw/","api":"https://instructionsets.com/api/v1/x86/kandw.json"},{"mnemonic":"kmovq","slug":"kmovq","records":1,"summary":"Moves 64-bit mask to/from k-register.","page":"https://instructionsets.com/x86/kmovq/","api":"https://instructionsets.com/api/v1/x86/kmovq.json"},{"mnemonic":"kmovw","slug":"kmovw","records":1,"summary":"Moves 16-bit mask to/from k-register.","page":"https://instructionsets.com/x86/kmovw/","api":"https://instructionsets.com/api/v1/x86/kmovw.json"},{"mnemonic":"knotb","slug":"knotb","records":1,"summary":"Bitwise NOT of 8-bit mask.","page":"https://instructionsets.com/x86/knotb/","api":"https://instructionsets.com/api/v1/x86/knotb.json"},{"mnemonic":"knotd","slug":"knotd","records":1,"summary":"Bitwise NOT of 32-bit mask.","page":"https://instructionsets.com/x86/knotd/","api":"https://instructionsets.com/api/v1/x86/knotd.json"},{"mnemonic":"knotq","slug":"knotq","records":1,"summary":"Bitwise NOT of 64-bit mask register.","page":"https://instructionsets.com/x86/knotq/","api":"https://instructionsets.com/api/v1/x86/knotq.json"},{"mnemonic":"knotw","slug":"knotw","records":1,"summary":"Bitwise NOT of 16-bit mask.","page":"https://instructionsets.com/x86/knotw/","api":"https://instructionsets.com/api/v1/x86/knotw.json"},{"mnemonic":"korb","slug":"korb","records":1,"summary":"Bitwise OR of 8-bit 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(ZF/CF).","page":"https://instructionsets.com/x86/kortestq/","api":"https://instructionsets.com/api/v1/x86/kortestq.json"},{"mnemonic":"kortestw","slug":"kortestw","records":1,"summary":"ORs two masks and sets EFLAGS (ZF, CF) based on result.","page":"https://instructionsets.com/x86/kortestw/","api":"https://instructionsets.com/api/v1/x86/kortestw.json"},{"mnemonic":"korw","slug":"korw","records":1,"summary":"Bitwise OR of 16-bit masks.","page":"https://instructionsets.com/x86/korw/","api":"https://instructionsets.com/api/v1/x86/korw.json"},{"mnemonic":"kshiftlb","slug":"kshiftlb","records":1,"summary":"Logically shifts 8-bit mask left.","page":"https://instructionsets.com/x86/kshiftlb/","api":"https://instructionsets.com/api/v1/x86/kshiftlb.json"},{"mnemonic":"kshiftld","slug":"kshiftld","records":1,"summary":"Logically shifts 32-bit mask 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(ZF/CF).","page":"https://instructionsets.com/x86/ktestd/","api":"https://instructionsets.com/api/v1/x86/ktestd.json"},{"mnemonic":"ktestq","slug":"ktestq","records":1,"summary":"ANDs 64-bit masks and sets EFLAGS (ZF/CF).","page":"https://instructionsets.com/x86/ktestq/","api":"https://instructionsets.com/api/v1/x86/ktestq.json"},{"mnemonic":"ktestw","slug":"ktestw","records":1,"summary":"ANDs 16-bit masks and sets EFLAGS (ZF/CF).","page":"https://instructionsets.com/x86/ktestw/","api":"https://instructionsets.com/api/v1/x86/ktestw.json"},{"mnemonic":"kunpckbw","slug":"kunpckbw","records":1,"summary":"Interleaves 8-bit masks into 16-bit mask.","page":"https://instructionsets.com/x86/kunpckbw/","api":"https://instructionsets.com/api/v1/x86/kunpckbw.json"},{"mnemonic":"kunpckdq","slug":"kunpckdq","records":1,"summary":"Interleaves 32-bit masks into 64-bit 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16-bit masks.","page":"https://instructionsets.com/x86/kxorw/","api":"https://instructionsets.com/api/v1/x86/kxorw.json"},{"mnemonic":"lahf","slug":"lahf","records":1,"summary":"Loads bits 0, 2, 4, 6, and 7 of EFLAGS into AH.","page":"https://instructionsets.com/x86/lahf/","api":"https://instructionsets.com/api/v1/x86/lahf.json"},{"mnemonic":"lar","slug":"lar","records":1,"summary":"Reads access rights from segment descriptor.","page":"https://instructionsets.com/x86/lar/","api":"https://instructionsets.com/api/v1/x86/lar.json"},{"mnemonic":"lddqu","slug":"lddqu","records":1,"summary":"Loads unaligned data avoiding split-line penalties.","page":"https://instructionsets.com/x86/lddqu/","api":"https://instructionsets.com/api/v1/x86/lddqu.json"},{"mnemonic":"ldmxcsr","slug":"ldmxcsr","records":1,"summary":"Loads the MXCSR control/status register from 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EBP).","page":"https://instructionsets.com/x86/leave/","api":"https://instructionsets.com/api/v1/x86/leave.json"},{"mnemonic":"les","slug":"les","records":1,"summary":"Loads pointer into ES and register.","page":"https://instructionsets.com/x86/les/","api":"https://instructionsets.com/api/v1/x86/les.json"},{"mnemonic":"lfence","slug":"lfence","records":1,"summary":"Serializes load operations (Wait for prior loads to complete).","page":"https://instructionsets.com/x86/lfence/","api":"https://instructionsets.com/api/v1/x86/lfence.json"},{"mnemonic":"lfs","slug":"lfs","records":1,"summary":"Loads pointer into FS and register.","page":"https://instructionsets.com/x86/lfs/","api":"https://instructionsets.com/api/v1/x86/lfs.json"},{"mnemonic":"lgdt","slug":"lgdt","records":1,"summary":"Loads the GDT register (Privileged).","page":"https://instructionsets.com/x86/lgdt/","api":"https://instructionsets.com/api/v1/x86/lgdt.json"},{"mnemonic":"lgs","slug":"lgs","records":1,"summary":"Loads pointer into GS and register.","page":"https://instructionsets.com/x86/lgs/","api":"https://instructionsets.com/api/v1/x86/lgs.json"},{"mnemonic":"lidt","slug":"lidt","records":1,"summary":"Loads the IDT register (Privileged).","page":"https://instructionsets.com/x86/lidt/","api":"https://instructionsets.com/api/v1/x86/lidt.json"},{"mnemonic":"lkgs","slug":"lkgs","records":1,"summary":"Loads the kernel GS base address (FRED support).","page":"https://instructionsets.com/x86/lkgs/","api":"https://instructionsets.com/api/v1/x86/lkgs.json"},{"mnemonic":"lldt","slug":"lldt","records":1,"summary":"Loads LDT segment selector (Privileged).","page":"https://instructionsets.com/x86/lldt/","api":"https://instructionsets.com/api/v1/x86/lldt.json"},{"mnemonic":"lmsw","slug":"lmsw","records":1,"summary":"Loads Machine Status Word (Legacy CR0 modification).","page":"https://instructionsets.com/x86/lmsw/","api":"https://instructionsets.com/api/v1/x86/lmsw.json"},{"mnemonic":"loadiwkey","slug":"loadiwkey","records":1,"summary":"Loads the Key Locker internal wrapping key.","page":"https://instructionsets.com/x86/loadiwkey/","api":"https://instructionsets.com/api/v1/x86/loadiwkey.json"},{"mnemonic":"lods","slug":"lods","records":1,"summary":"Loads byte/word/dword from [ESI] into AL/AX/EAX.","page":"https://instructionsets.com/x86/lods/","api":"https://instructionsets.com/api/v1/x86/lods.json"},{"mnemonic":"lodsd","slug":"lodsd","records":1,"summary":"Loads doubleword from [ESI] into EAX.","page":"https://instructionsets.com/x86/lodsd/","api":"https://instructionsets.com/api/v1/x86/lodsd.json"},{"mnemonic":"lodsq","slug":"lodsq","records":1,"summary":"Loads quadword from [RSI] into RAX.","page":"https://instructionsets.com/x86/lodsq/","api":"https://instructionsets.com/api/v1/x86/lodsq.json"},{"mnemonic":"lodsw","slug":"lodsw","records":1,"summary":"Loads word from [ESI] into AX.","page":"https://instructionsets.com/x86/lodsw/","api":"https://instructionsets.com/api/v1/x86/lodsw.json"},{"mnemonic":"loop","slug":"loop","records":1,"summary":"Decrements ECX/RCX and jumps if not zero.","page":"https://instructionsets.com/x86/loop/","api":"https://instructionsets.com/api/v1/x86/loop.json"},{"mnemonic":"loope","slug":"loope","records":1,"summary":"Decrements count; jumps if count!=0 and ZF=1.","page":"https://instructionsets.com/x86/loope/","api":"https://instructionsets.com/api/v1/x86/loope.json"},{"mnemonic":"loopne","slug":"loopne","records":1,"summary":"Decrements count; jumps if count!=0 and ZF=0.","page":"https://instructionsets.com/x86/loopne/","api":"https://instructionsets.com/api/v1/x86/loopne.json"},{"mnemonic":"lsl","slug":"lsl","records":1,"summary":"Reads segment limit from descriptor.","page":"https://instructionsets.com/x86/lsl/","api":"https://instructionsets.com/api/v1/x86/lsl.json"},{"mnemonic":"lss","slug":"lss","records":1,"summary":"Loads pointer into SS and register.","page":"https://instructionsets.com/x86/lss/","api":"https://instructionsets.com/api/v1/x86/lss.json"},{"mnemonic":"ltr","slug":"ltr","records":1,"summary":"Loads Task Register (Privileged).","page":"https://instructionsets.com/x86/ltr/","api":"https://instructionsets.com/api/v1/x86/ltr.json"},{"mnemonic":"lzcnt","slug":"lzcnt","records":1,"summary":"Counts number of leading zeros.","page":"https://instructionsets.com/x86/lzcnt/","api":"https://instructionsets.com/api/v1/x86/lzcnt.json"},{"mnemonic":"maskmovdqu","slug":"maskmovdqu","records":1,"summary":"Non-temporal store of selected bytes (masked).","page":"https://instructionsets.com/x86/maskmovdqu/","api":"https://instructionsets.com/api/v1/x86/maskmovdqu.json"},{"mnemonic":"maskmovq","slug":"maskmovq","records":1,"summary":"Non-temporal store of selected MMX bytes.","page":"https://instructionsets.com/x86/maskmovq/","api":"https://instructionsets.com/api/v1/x86/maskmovq.json"},{"mnemonic":"maxps","slug":"maxps","records":1,"summary":"Returns maximum of packed floats.","page":"https://instructionsets.com/x86/maxps/","api":"https://instructionsets.com/api/v1/x86/maxps.json"},{"mnemonic":"maxsd","slug":"maxsd","records":1,"summary":"Returns the maximum of two low double-precision values.","page":"https://instructionsets.com/x86/maxsd/","api":"https://instructionsets.com/api/v1/x86/maxsd.json"},{"mnemonic":"maxss","slug":"maxss","records":1,"summary":"Returns the maximum of two low single-precision values.","page":"https://instructionsets.com/x86/maxss/","api":"https://instructionsets.com/api/v1/x86/maxss.json"},{"mnemonic":"mfence","slug":"mfence","records":1,"summary":"Serializes all load and store operations.","page":"https://instructionsets.com/x86/mfence/","api":"https://instructionsets.com/api/v1/x86/mfence.json"},{"mnemonic":"minps","slug":"minps","records":1,"summary":"Returns minimum of packed floats.","page":"https://instructionsets.com/x86/minps/","api":"https://instructionsets.com/api/v1/x86/minps.json"},{"mnemonic":"minsd","slug":"minsd","records":1,"summary":"Returns the minimum of two low double-precision values.","page":"https://instructionsets.com/x86/minsd/","api":"https://instructionsets.com/api/v1/x86/minsd.json"},{"mnemonic":"minss","slug":"minss","records":1,"summary":"Returns the minimum of two low single-precision values.","page":"https://instructionsets.com/x86/minss/","api":"https://instructionsets.com/api/v1/x86/minss.json"},{"mnemonic":"monitor","slug":"monitor","records":1,"summary":"Sets up a linear address range to be monitored.","page":"https://instructionsets.com/x86/monitor/","api":"https://instructionsets.com/api/v1/x86/monitor.json"},{"mnemonic":"monitorx","slug":"monitorx","records":1,"summary":"Sets up a monitor address (AMD extension).","page":"https://instructionsets.com/x86/monitorx/","api":"https://instructionsets.com/api/v1/x86/monitorx.json"},{"mnemonic":"mov","slug":"mov","records":1,"summary":"Copies data from source to destination.","page":"https://instructionsets.com/x86/mov/","api":"https://instructionsets.com/api/v1/x86/mov.json"},{"mnemonic":"mov cr","slug":"mov_cr","records":1,"summary":"Moves data to/from Control Registers (CR0, CR3, etc.) (Privileged).","page":"https://instructionsets.com/x86/mov_cr/","api":"https://instructionsets.com/api/v1/x86/mov_cr.json"},{"mnemonic":"mov dr","slug":"mov_dr","records":1,"summary":"Moves data to/from Debug Registers (DR0-DR7) (Privileged).","page":"https://instructionsets.com/x86/mov_dr/","api":"https://instructionsets.com/api/v1/x86/mov_dr.json"},{"mnemonic":"movapd","slug":"movapd","records":1,"summary":"Moves 128-bit packed double data (Must be 16-byte aligned).","page":"https://instructionsets.com/x86/movapd/","api":"https://instructionsets.com/api/v1/x86/movapd.json"},{"mnemonic":"movaps","slug":"movaps","records":1,"summary":"Moves 128-bit packed float data (Must be 16-byte aligned).","page":"https://instructionsets.com/x86/movaps/","api":"https://instructionsets.com/api/v1/x86/movaps.json"},{"mnemonic":"movbe","slug":"movbe","records":1,"summary":"Moves data swapping bytes (Big Endian load/store).","page":"https://instructionsets.com/x86/movbe/","api":"https://instructionsets.com/api/v1/x86/movbe.json"},{"mnemonic":"movd","slug":"movd","records":1,"summary":"Moves 32 bits between GPR and XMM/MMX register.","page":"https://instructionsets.com/x86/movd/","api":"https://instructionsets.com/api/v1/x86/movd.json"},{"mnemonic":"movddup","slug":"movddup","records":1,"summary":"Loads 64-bit double and duplicates it to fill 128-bit register.","page":"https://instructionsets.com/x86/movddup/","api":"https://instructionsets.com/api/v1/x86/movddup.json"},{"mnemonic":"movdir64b","slug":"movdir64b","records":1,"summary":"Atomically moves 64-byte block avoiding cache pollution.","page":"https://instructionsets.com/x86/movdir64b/","api":"https://instructionsets.com/api/v1/x86/movdir64b.json"},{"mnemonic":"movdiri","slug":"movdiri","records":1,"summary":"Moves 32/64-bit data avoiding cache pollution (Direct IO).","page":"https://instructionsets.com/x86/movdiri/","api":"https://instructionsets.com/api/v1/x86/movdiri.json"},{"mnemonic":"movdqa","slug":"movdqa","records":1,"summary":"Moves 128-bit integer data (Aligned).","page":"https://instructionsets.com/x86/movdqa/","api":"https://instructionsets.com/api/v1/x86/movdqa.json"},{"mnemonic":"movdqu","slug":"movdqu","records":1,"summary":"Moves 128-bit integer data (Unaligned).","page":"https://instructionsets.com/x86/movdqu/","api":"https://instructionsets.com/api/v1/x86/movdqu.json"},{"mnemonic":"movmskpd","slug":"movmskpd","records":1,"summary":"Extracts sign bits from two doubles into low 2 bits of register.","page":"https://instructionsets.com/x86/movmskpd/","api":"https://instructionsets.com/api/v1/x86/movmskpd.json"},{"mnemonic":"movmskps","slug":"movmskps","records":1,"summary":"Extracts sign bits from four floats into low 4 bits of register.","page":"https://instructionsets.com/x86/movmskps/","api":"https://instructionsets.com/api/v1/x86/movmskps.json"},{"mnemonic":"movntdqa","slug":"movntdqa","records":1,"summary":"Efficiently loads 128-bits from WC memory (Streaming Load).","page":"https://instructionsets.com/x86/movntdqa/","api":"https://instructionsets.com/api/v1/x86/movntdqa.json"},{"mnemonic":"movnti","slug":"movnti","records":1,"summary":"Stores integer register to memory bypassing cache.","page":"https://instructionsets.com/x86/movnti/","api":"https://instructionsets.com/api/v1/x86/movnti.json"},{"mnemonic":"movntpd","slug":"movntpd","records":1,"summary":"Stores double vectors directly to RAM, bypassing cache.","page":"https://instructionsets.com/x86/movntpd/","api":"https://instructionsets.com/api/v1/x86/movntpd.json"},{"mnemonic":"movntps","slug":"movntps","records":1,"summary":"Stores float vectors directly to RAM, bypassing cache.","page":"https://instructionsets.com/x86/movntps/","api":"https://instructionsets.com/api/v1/x86/movntps.json"},{"mnemonic":"movntq","slug":"movntq","records":1,"summary":"Stores 64-bit MMX data bypassing cache.","page":"https://instructionsets.com/x86/movntq/","api":"https://instructionsets.com/api/v1/x86/movntq.json"},{"mnemonic":"movntsd","slug":"movntsd","records":1,"summary":"Stores scalar double bypassing cache (AMD SSE4a).","page":"https://instructionsets.com/x86/movntsd/","api":"https://instructionsets.com/api/v1/x86/movntsd.json"},{"mnemonic":"movntss","slug":"movntss","records":1,"summary":"Stores scalar float bypassing cache (AMD SSE4a).","page":"https://instructionsets.com/x86/movntss/","api":"https://instructionsets.com/api/v1/x86/movntss.json"},{"mnemonic":"movq","slug":"movq","records":2,"summary":"Moves 64-bit data between MMX registers/memory.","page":"https://instructionsets.com/x86/movq/","api":"https://instructionsets.com/api/v1/x86/movq.json"},{"mnemonic":"movsd","slug":"movsd","records":2,"summary":"Moves a single double (low 64 bits) between XMM/Memory.","page":"https://instructionsets.com/x86/movsd/","api":"https://instructionsets.com/api/v1/x86/movsd.json"},{"mnemonic":"movshdup","slug":"movshdup","records":1,"summary":"Duplicates high element of each qword pair.","page":"https://instructionsets.com/x86/movshdup/","api":"https://instructionsets.com/api/v1/x86/movshdup.json"},{"mnemonic":"movsldup","slug":"movsldup","records":1,"summary":"Duplicates low element of each qword pair.","page":"https://instructionsets.com/x86/movsldup/","api":"https://instructionsets.com/api/v1/x86/movsldup.json"},{"mnemonic":"movsq","slug":"movsq","records":1,"summary":"Moves quadword from [RSI] to [RDI].","page":"https://instructionsets.com/x86/movsq/","api":"https://instructionsets.com/api/v1/x86/movsq.json"},{"mnemonic":"movss","slug":"movss","records":1,"summary":"Moves a single float (low 32 bits) between XMM/Memory.","page":"https://instructionsets.com/x86/movss/","api":"https://instructionsets.com/api/v1/x86/movss.json"},{"mnemonic":"movsw","slug":"movsw","records":1,"summary":"Moves word from [ESI] to [EDI].","page":"https://instructionsets.com/x86/movsw/","api":"https://instructionsets.com/api/v1/x86/movsw.json"},{"mnemonic":"movsx","slug":"movsx","records":1,"summary":"Copies and sign-extends a smaller value to a larger register.","page":"https://instructionsets.com/x86/movsx/","api":"https://instructionsets.com/api/v1/x86/movsx.json"},{"mnemonic":"movsxd","slug":"movsxd","records":1,"summary":"Sign-extends 32-bit register to 64-bit.","page":"https://instructionsets.com/x86/movsxd/","api":"https://instructionsets.com/api/v1/x86/movsxd.json"},{"mnemonic":"movupd","slug":"movupd","records":1,"summary":"Moves 128-bit packed double data (Unaligned).","page":"https://instructionsets.com/x86/movupd/","api":"https://instructionsets.com/api/v1/x86/movupd.json"},{"mnemonic":"movups","slug":"movups","records":1,"summary":"Moves 128-bit packed float data (Unaligned).","page":"https://instructionsets.com/x86/movups/","api":"https://instructionsets.com/api/v1/x86/movups.json"},{"mnemonic":"movzx","slug":"movzx","records":1,"summary":"Copies and zero-extends a smaller value to a larger register.","page":"https://instructionsets.com/x86/movzx/","api":"https://instructionsets.com/api/v1/x86/movzx.json"},{"mnemonic":"mpsadbw","slug":"mpsadbw","records":1,"summary":"Computes multiple SADs of byte blocks.","page":"https://instructionsets.com/x86/mpsadbw/","api":"https://instructionsets.com/api/v1/x86/mpsadbw.json"},{"mnemonic":"mul","slug":"mul","records":1,"summary":"Unsigned multiply (AX = AL * src).","page":"https://instructionsets.com/x86/mul/","api":"https://instructionsets.com/api/v1/x86/mul.json"},{"mnemonic":"mulpd","slug":"mulpd","records":1,"summary":"Multiplies two 64-bit doubles.","page":"https://instructionsets.com/x86/mulpd/","api":"https://instructionsets.com/api/v1/x86/mulpd.json"},{"mnemonic":"mulps","slug":"mulps","records":1,"summary":"Multiplies four 32-bit floats.","page":"https://instructionsets.com/x86/mulps/","api":"https://instructionsets.com/api/v1/x86/mulps.json"},{"mnemonic":"mulsd","slug":"mulsd","records":1,"summary":"Multiplies the low double-precision floating-point value.","page":"https://instructionsets.com/x86/mulsd/","api":"https://instructionsets.com/api/v1/x86/mulsd.json"},{"mnemonic":"mulss","slug":"mulss","records":1,"summary":"Multiplies the low single-precision floating-point value.","page":"https://instructionsets.com/x86/mulss/","api":"https://instructionsets.com/api/v1/x86/mulss.json"},{"mnemonic":"mulx","slug":"mulx","records":1,"summary":"Unsigned multiply of RDX * Src. Result in Hi:Lo. No flags.","page":"https://instructionsets.com/x86/mulx/","api":"https://instructionsets.com/api/v1/x86/mulx.json"},{"mnemonic":"mwait","slug":"mwait","records":1,"summary":"Waits for a write to a monitored address.","page":"https://instructionsets.com/x86/mwait/","api":"https://instructionsets.com/api/v1/x86/mwait.json"},{"mnemonic":"mwaitx","slug":"mwaitx","records":1,"summary":"Waits for a write to monitored address (AMD extension).","page":"https://instructionsets.com/x86/mwaitx/","api":"https://instructionsets.com/api/v1/x86/mwaitx.json"},{"mnemonic":"neg","slug":"neg","records":1,"summary":"Negates value (0 - operand).","page":"https://instructionsets.com/x86/neg/","api":"https://instructionsets.com/api/v1/x86/neg.json"},{"mnemonic":"nop","slug":"nop","records":1,"summary":"Does nothing (alias for XCHG EAX, EAX).","page":"https://instructionsets.com/x86/nop/","api":"https://instructionsets.com/api/v1/x86/nop.json"},{"mnemonic":"not","slug":"not","records":1,"summary":"Reverses bits of operand.","page":"https://instructionsets.com/x86/not/","api":"https://instructionsets.com/api/v1/x86/not.json"},{"mnemonic":"or","slug":"or","records":1,"summary":"Performs bitwise OR.","page":"https://instructionsets.com/x86/or/","api":"https://instructionsets.com/api/v1/x86/or.json"},{"mnemonic":"orps","slug":"orps","records":1,"summary":"Bitwise OR of 128 bits.","page":"https://instructionsets.com/x86/orps/","api":"https://instructionsets.com/api/v1/x86/orps.json"},{"mnemonic":"out","slug":"out","records":2,"summary":"Writes data from AL/AX/EAX to an I/O port.","page":"https://instructionsets.com/x86/out/","api":"https://instructionsets.com/api/v1/x86/out.json"},{"mnemonic":"outs","slug":"outs","records":1,"summary":"Writes string from memory at [ESI] to I/O port.","page":"https://instructionsets.com/x86/outs/","api":"https://instructionsets.com/api/v1/x86/outs.json"},{"mnemonic":"outsd","slug":"outsd","records":1,"summary":"Writes doubleword from memory at [ESI] to I/O port.","page":"https://instructionsets.com/x86/outsd/","api":"https://instructionsets.com/api/v1/x86/outsd.json"},{"mnemonic":"outsw","slug":"outsw","records":1,"summary":"Writes word from memory at [ESI] to I/O port.","page":"https://instructionsets.com/x86/outsw/","api":"https://instructionsets.com/api/v1/x86/outsw.json"},{"mnemonic":"pabsb","slug":"pabsb","records":1,"summary":"Computes absolute value of bytes.","page":"https://instructionsets.com/x86/pabsb/","api":"https://instructionsets.com/api/v1/x86/pabsb.json"},{"mnemonic":"packssdw","slug":"packssdw","records":1,"summary":"Converts doublewords to words with saturation.","page":"https://instructionsets.com/x86/packssdw/","api":"https://instructionsets.com/api/v1/x86/packssdw.json"},{"mnemonic":"packsswb","slug":"packsswb","records":1,"summary":"Converts words to bytes with saturation.","page":"https://instructionsets.com/x86/packsswb/","api":"https://instructionsets.com/api/v1/x86/packsswb.json"},{"mnemonic":"packusdw","slug":"packusdw","records":1,"summary":"Converts signed dwords to unsigned words with saturation.","page":"https://instructionsets.com/x86/packusdw/","api":"https://instructionsets.com/api/v1/x86/packusdw.json"},{"mnemonic":"packuswb","slug":"packuswb","records":1,"summary":"Converts signed words to unsigned bytes with saturation.","page":"https://instructionsets.com/x86/packuswb/","api":"https://instructionsets.com/api/v1/x86/packuswb.json"},{"mnemonic":"paddb","slug":"paddb","records":1,"summary":"Adds 16 bytes (Wraparound).","page":"https://instructionsets.com/x86/paddb/","api":"https://instructionsets.com/api/v1/x86/paddb.json"},{"mnemonic":"paddd","slug":"paddd","records":1,"summary":"Adds 4 doublewords (Wraparound).","page":"https://instructionsets.com/x86/paddd/","api":"https://instructionsets.com/api/v1/x86/paddd.json"},{"mnemonic":"paddq","slug":"paddq","records":1,"summary":"Adds 2 quadwords (Wraparound).","page":"https://instructionsets.com/x86/paddq/","api":"https://instructionsets.com/api/v1/x86/paddq.json"},{"mnemonic":"paddsb","slug":"paddsb","records":2,"summary":"Adds 8 signed bytes with saturation (MMX).","page":"https://instructionsets.com/x86/paddsb/","api":"https://instructionsets.com/api/v1/x86/paddsb.json"},{"mnemonic":"paddsw","slug":"paddsw","records":2,"summary":"Adds 4 signed words with saturation (MMX).","page":"https://instructionsets.com/x86/paddsw/","api":"https://instructionsets.com/api/v1/x86/paddsw.json"},{"mnemonic":"paddusb","slug":"paddusb","records":2,"summary":"Adds 8 unsigned bytes with saturation (MMX).","page":"https://instructionsets.com/x86/paddusb/","api":"https://instructionsets.com/api/v1/x86/paddusb.json"},{"mnemonic":"paddusw","slug":"paddusw","records":2,"summary":"Adds 4 unsigned words with saturation (MMX).","page":"https://instructionsets.com/x86/paddusw/","api":"https://instructionsets.com/api/v1/x86/paddusw.json"},{"mnemonic":"paddw","slug":"paddw","records":1,"summary":"Adds 8 words (Wraparound).","page":"https://instructionsets.com/x86/paddw/","api":"https://instructionsets.com/api/v1/x86/paddw.json"},{"mnemonic":"palignr","slug":"palignr","records":1,"summary":"Concatenates dest and src, extracts 128 bits byte-aligned.","page":"https://instructionsets.com/x86/palignr/","api":"https://instructionsets.com/api/v1/x86/palignr.json"},{"mnemonic":"pand","slug":"pand","records":2,"summary":"Bitwise AND of 64-bit MMX registers.","page":"https://instructionsets.com/x86/pand/","api":"https://instructionsets.com/api/v1/x86/pand.json"},{"mnemonic":"pandn","slug":"pandn","records":1,"summary":"Bitwise AND NOT of 64-bit MMX registers.","page":"https://instructionsets.com/x86/pandn/","api":"https://instructionsets.com/api/v1/x86/pandn.json"},{"mnemonic":"pause","slug":"pause","records":1,"summary":"Improves performance of spin-wait loops (alias for REP NOP).","page":"https://instructionsets.com/x86/pause/","api":"https://instructionsets.com/api/v1/x86/pause.json"},{"mnemonic":"pavgb","slug":"pavgb","records":1,"summary":"Averages packed unsigned bytes (rounded up).","page":"https://instructionsets.com/x86/pavgb/","api":"https://instructionsets.com/api/v1/x86/pavgb.json"},{"mnemonic":"pavgw","slug":"pavgw","records":1,"summary":"Averages packed unsigned words (rounded up).","page":"https://instructionsets.com/x86/pavgw/","api":"https://instructionsets.com/api/v1/x86/pavgw.json"},{"mnemonic":"pblendvb","slug":"pblendvb","records":1,"summary":"Blends bytes based on variable mask in XMM0.","page":"https://instructionsets.com/x86/pblendvb/","api":"https://instructionsets.com/api/v1/x86/pblendvb.json"},{"mnemonic":"pblendw","slug":"pblendw","records":1,"summary":"Selects words from two sources based on immediate mask.","page":"https://instructionsets.com/x86/pblendw/","api":"https://instructionsets.com/api/v1/x86/pblendw.json"},{"mnemonic":"pclmulqdq","slug":"pclmulqdq","records":1,"summary":"Performs carry-less multiplication (Galois Field math for AES-GCM).","page":"https://instructionsets.com/x86/pclmulqdq/","api":"https://instructionsets.com/api/v1/x86/pclmulqdq.json"},{"mnemonic":"pcmpeqb","slug":"pcmpeqb","records":2,"summary":"Compares bytes for equality (MMX).","page":"https://instructionsets.com/x86/pcmpeqb/","api":"https://instructionsets.com/api/v1/x86/pcmpeqb.json"},{"mnemonic":"pcmpeqd","slug":"pcmpeqd","records":2,"summary":"Compares doublewords for equality (MMX).","page":"https://instructionsets.com/x86/pcmpeqd/","api":"https://instructionsets.com/api/v1/x86/pcmpeqd.json"},{"mnemonic":"pcmpeqq","slug":"pcmpeqq","records":1,"summary":"Checks if 64-bit integer elements are equal.","page":"https://instructionsets.com/x86/pcmpeqq/","api":"https://instructionsets.com/api/v1/x86/pcmpeqq.json"},{"mnemonic":"pcmpeqw","slug":"pcmpeqw","records":2,"summary":"Compares words for equality (MMX).","page":"https://instructionsets.com/x86/pcmpeqw/","api":"https://instructionsets.com/api/v1/x86/pcmpeqw.json"},{"mnemonic":"pcmpestri","slug":"pcmpestri","records":1,"summary":"Complex string search/compare; returns index in ECX.","page":"https://instructionsets.com/x86/pcmpestri/","api":"https://instructionsets.com/api/v1/x86/pcmpestri.json"},{"mnemonic":"pcmpestrm","slug":"pcmpestrm","records":1,"summary":"Complex string search/compare; returns mask in XMM0.","page":"https://instructionsets.com/x86/pcmpestrm/","api":"https://instructionsets.com/api/v1/x86/pcmpestrm.json"},{"mnemonic":"pcmpgtb","slug":"pcmpgtb","records":2,"summary":"Compares bytes for greater than (MMX).","page":"https://instructionsets.com/x86/pcmpgtb/","api":"https://instructionsets.com/api/v1/x86/pcmpgtb.json"},{"mnemonic":"pcmpgtd","slug":"pcmpgtd","records":2,"summary":"Compares doublewords for greater than (MMX).","page":"https://instructionsets.com/x86/pcmpgtd/","api":"https://instructionsets.com/api/v1/x86/pcmpgtd.json"},{"mnemonic":"pcmpgtq","slug":"pcmpgtq","records":1,"summary":"Compares quadwords for greater than (signed).","page":"https://instructionsets.com/x86/pcmpgtq/","api":"https://instructionsets.com/api/v1/x86/pcmpgtq.json"},{"mnemonic":"pcmpgtw","slug":"pcmpgtw","records":2,"summary":"Compares words for greater than (MMX).","page":"https://instructionsets.com/x86/pcmpgtw/","api":"https://instructionsets.com/api/v1/x86/pcmpgtw.json"},{"mnemonic":"pcmpistri","slug":"pcmpistri","records":1,"summary":"String search (null-terminated); returns index in ECX.","page":"https://instructionsets.com/x86/pcmpistri/","api":"https://instructionsets.com/api/v1/x86/pcmpistri.json"},{"mnemonic":"pconfig","slug":"pconfig","records":1,"summary":"Configures platform features like MKTME (Memory Encryption).","page":"https://instructionsets.com/x86/pconfig/","api":"https://instructionsets.com/api/v1/x86/pconfig.json"},{"mnemonic":"pdep","slug":"pdep","records":1,"summary":"Scatters bits from LSB of source to positions marked in mask.","page":"https://instructionsets.com/x86/pdep/","api":"https://instructionsets.com/api/v1/x86/pdep.json"},{"mnemonic":"pext","slug":"pext","records":1,"summary":"Extracts bits from source using mask and packs them to LSB.","page":"https://instructionsets.com/x86/pext/","api":"https://instructionsets.com/api/v1/x86/pext.json"},{"mnemonic":"pextrb","slug":"pextrb","records":1,"summary":"Extracts a byte from XMM to integer register.","page":"https://instructionsets.com/x86/pextrb/","api":"https://instructionsets.com/api/v1/x86/pextrb.json"},{"mnemonic":"pextrd","slug":"pextrd","records":1,"summary":"Extracts a doubleword from XMM to register.","page":"https://instructionsets.com/x86/pextrd/","api":"https://instructionsets.com/api/v1/x86/pextrd.json"},{"mnemonic":"pextrq","slug":"pextrq","records":1,"summary":"Extracts a quadword from XMM to register.","page":"https://instructionsets.com/x86/pextrq/","api":"https://instructionsets.com/api/v1/x86/pextrq.json"},{"mnemonic":"pextrw","slug":"pextrw","records":1,"summary":"Extracts a word from XMM to integer register.","page":"https://instructionsets.com/x86/pextrw/","api":"https://instructionsets.com/api/v1/x86/pextrw.json"},{"mnemonic":"pfadd","slug":"pfadd","records":1,"summary":"Adds two packed floats (3DNow!).","page":"https://instructionsets.com/x86/pfadd/","api":"https://instructionsets.com/api/v1/x86/pfadd.json"},{"mnemonic":"pfmul","slug":"pfmul","records":1,"summary":"Multiplies packed floats (3DNow!).","page":"https://instructionsets.com/x86/pfmul/","api":"https://instructionsets.com/api/v1/x86/pfmul.json"},{"mnemonic":"pfrcp","slug":"pfrcp","records":1,"summary":"Approximates reciprocal (3DNow!).","page":"https://instructionsets.com/x86/pfrcp/","api":"https://instructionsets.com/api/v1/x86/pfrcp.json"},{"mnemonic":"pfrsqrt","slug":"pfrsqrt","records":1,"summary":"Approximates reciprocal sqrt (3DNow!).","page":"https://instructionsets.com/x86/pfrsqrt/","api":"https://instructionsets.com/api/v1/x86/pfrsqrt.json"},{"mnemonic":"pfsub","slug":"pfsub","records":1,"summary":"Subtracts packed floats (3DNow!).","page":"https://instructionsets.com/x86/pfsub/","api":"https://instructionsets.com/api/v1/x86/pfsub.json"},{"mnemonic":"phaddw","slug":"phaddw","records":1,"summary":"Adds adjacent 16-bit integers horizontally.","page":"https://instructionsets.com/x86/phaddw/","api":"https://instructionsets.com/api/v1/x86/phaddw.json"},{"mnemonic":"phminposuw","slug":"phminposuw","records":1,"summary":"Finds minimum word and its index.","page":"https://instructionsets.com/x86/phminposuw/","api":"https://instructionsets.com/api/v1/x86/phminposuw.json"},{"mnemonic":"phsubd","slug":"phsubd","records":1,"summary":"Subtracts adjacent 32-bit integers horizontally.","page":"https://instructionsets.com/x86/phsubd/","api":"https://instructionsets.com/api/v1/x86/phsubd.json"},{"mnemonic":"phsubw","slug":"phsubw","records":1,"summary":"Subtracts adjacent 16-bit integers horizontally.","page":"https://instructionsets.com/x86/phsubw/","api":"https://instructionsets.com/api/v1/x86/phsubw.json"},{"mnemonic":"pinsrb","slug":"pinsrb","records":1,"summary":"Inserts a byte from integer register into XMM.","page":"https://instructionsets.com/x86/pinsrb/","api":"https://instructionsets.com/api/v1/x86/pinsrb.json"},{"mnemonic":"pinsrd","slug":"pinsrd","records":1,"summary":"Inserts a doubleword from register to XMM.","page":"https://instructionsets.com/x86/pinsrd/","api":"https://instructionsets.com/api/v1/x86/pinsrd.json"},{"mnemonic":"pinsrq","slug":"pinsrq","records":1,"summary":"Inserts a quadword from register to XMM.","page":"https://instructionsets.com/x86/pinsrq/","api":"https://instructionsets.com/api/v1/x86/pinsrq.json"},{"mnemonic":"pinsrw","slug":"pinsrw","records":1,"summary":"Inserts a word from integer register into XMM.","page":"https://instructionsets.com/x86/pinsrw/","api":"https://instructionsets.com/api/v1/x86/pinsrw.json"},{"mnemonic":"pmaddubsw","slug":"pmaddubsw","records":1,"summary":"Multiplies signed/unsigned bytes and adds pairs to words.","page":"https://instructionsets.com/x86/pmaddubsw/","api":"https://instructionsets.com/api/v1/x86/pmaddubsw.json"},{"mnemonic":"pmaddwd","slug":"pmaddwd","records":2,"summary":"Multiplies words and adds adjacent pairs (MMX).","page":"https://instructionsets.com/x86/pmaddwd/","api":"https://instructionsets.com/api/v1/x86/pmaddwd.json"},{"mnemonic":"pmaxsb","slug":"pmaxsb","records":1,"summary":"Returns maximum of signed bytes.","page":"https://instructionsets.com/x86/pmaxsb/","api":"https://instructionsets.com/api/v1/x86/pmaxsb.json"},{"mnemonic":"pmaxsd","slug":"pmaxsd","records":1,"summary":"Returns maximum of signed doublewords.","page":"https://instructionsets.com/x86/pmaxsd/","api":"https://instructionsets.com/api/v1/x86/pmaxsd.json"},{"mnemonic":"pmaxsw","slug":"pmaxsw","records":1,"summary":"Returns maximum of signed words.","page":"https://instructionsets.com/x86/pmaxsw/","api":"https://instructionsets.com/api/v1/x86/pmaxsw.json"},{"mnemonic":"pmaxub","slug":"pmaxub","records":1,"summary":"Returns maximum of unsigned bytes.","page":"https://instructionsets.com/x86/pmaxub/","api":"https://instructionsets.com/api/v1/x86/pmaxub.json"},{"mnemonic":"pmaxud","slug":"pmaxud","records":1,"summary":"Returns maximum of unsigned doublewords.","page":"https://instructionsets.com/x86/pmaxud/","api":"https://instructionsets.com/api/v1/x86/pmaxud.json"},{"mnemonic":"pmaxuw","slug":"pmaxuw","records":1,"summary":"Returns maximum of unsigned words.","page":"https://instructionsets.com/x86/pmaxuw/","api":"https://instructionsets.com/api/v1/x86/pmaxuw.json"},{"mnemonic":"pminsb","slug":"pminsb","records":1,"summary":"Returns minimum of signed bytes.","page":"https://instructionsets.com/x86/pminsb/","api":"https://instructionsets.com/api/v1/x86/pminsb.json"},{"mnemonic":"pminsd","slug":"pminsd","records":1,"summary":"Returns minimum of signed doublewords.","page":"https://instructionsets.com/x86/pminsd/","api":"https://instructionsets.com/api/v1/x86/pminsd.json"},{"mnemonic":"pminsw","slug":"pminsw","records":1,"summary":"Returns minimum of signed words.","page":"https://instructionsets.com/x86/pminsw/","api":"https://instructionsets.com/api/v1/x86/pminsw.json"},{"mnemonic":"pminub","slug":"pminub","records":1,"summary":"Returns minimum of unsigned bytes.","page":"https://instructionsets.com/x86/pminub/","api":"https://instructionsets.com/api/v1/x86/pminub.json"},{"mnemonic":"pminud","slug":"pminud","records":1,"summary":"Returns minimum of unsigned doublewords.","page":"https://instructionsets.com/x86/pminud/","api":"https://instructionsets.com/api/v1/x86/pminud.json"},{"mnemonic":"pminuw","slug":"pminuw","records":1,"summary":"Returns minimum of unsigned words.","page":"https://instructionsets.com/x86/pminuw/","api":"https://instructionsets.com/api/v1/x86/pminuw.json"},{"mnemonic":"pmovmskb","slug":"pmovmskb","records":1,"summary":"Creates a mask from the MSB of each byte in XMM.","page":"https://instructionsets.com/x86/pmovmskb/","api":"https://instructionsets.com/api/v1/x86/pmovmskb.json"},{"mnemonic":"pmovsxbq","slug":"pmovsxbq","records":1,"summary":"Sign extends 8-bit integers to 64-bit.","page":"https://instructionsets.com/x86/pmovsxbq/","api":"https://instructionsets.com/api/v1/x86/pmovsxbq.json"},{"mnemonic":"pmovsxbw","slug":"pmovsxbw","records":1,"summary":"Sign extends 8-bit integers to 16-bit.","page":"https://instructionsets.com/x86/pmovsxbw/","api":"https://instructionsets.com/api/v1/x86/pmovsxbw.json"},{"mnemonic":"pmovsxdq","slug":"pmovsxdq","records":1,"summary":"Sign extends 32-bit integers to 64-bit.","page":"https://instructionsets.com/x86/pmovsxdq/","api":"https://instructionsets.com/api/v1/x86/pmovsxdq.json"},{"mnemonic":"pmovsxwd","slug":"pmovsxwd","records":1,"summary":"Sign extends 16-bit integers to 32-bit.","page":"https://instructionsets.com/x86/pmovsxwd/","api":"https://instructionsets.com/api/v1/x86/pmovsxwd.json"},{"mnemonic":"pmovsxwq","slug":"pmovsxwq","records":1,"summary":"Sign extends 16-bit integers to 64-bit.","page":"https://instructionsets.com/x86/pmovsxwq/","api":"https://instructionsets.com/api/v1/x86/pmovsxwq.json"},{"mnemonic":"pmovzxbd","slug":"pmovzxbd","records":1,"summary":"Zero extends 8-bit integers to 32-bit.","page":"https://instructionsets.com/x86/pmovzxbd/","api":"https://instructionsets.com/api/v1/x86/pmovzxbd.json"},{"mnemonic":"pmovzxbq","slug":"pmovzxbq","records":1,"summary":"Zero extends 8-bit integers to 64-bit.","page":"https://instructionsets.com/x86/pmovzxbq/","api":"https://instructionsets.com/api/v1/x86/pmovzxbq.json"},{"mnemonic":"pmovzxbw","slug":"pmovzxbw","records":1,"summary":"Zero extends 8-bit integers to 16-bit.","page":"https://instructionsets.com/x86/pmovzxbw/","api":"https://instructionsets.com/api/v1/x86/pmovzxbw.json"},{"mnemonic":"pmovzxdq","slug":"pmovzxdq","records":1,"summary":"Zero extends 32-bit integers to 64-bit.","page":"https://instructionsets.com/x86/pmovzxdq/","api":"https://instructionsets.com/api/v1/x86/pmovzxdq.json"},{"mnemonic":"pmovzxwd","slug":"pmovzxwd","records":1,"summary":"Zero extends 16-bit integers to 32-bit.","page":"https://instructionsets.com/x86/pmovzxwd/","api":"https://instructionsets.com/api/v1/x86/pmovzxwd.json"},{"mnemonic":"pmovzxwq","slug":"pmovzxwq","records":1,"summary":"Zero extends 16-bit integers to 64-bit.","page":"https://instructionsets.com/x86/pmovzxwq/","api":"https://instructionsets.com/api/v1/x86/pmovzxwq.json"},{"mnemonic":"pmulhrsw","slug":"pmulhrsw","records":1,"summary":"Multiplies signed 16-bit words, rounds, and scales.","page":"https://instructionsets.com/x86/pmulhrsw/","api":"https://instructionsets.com/api/v1/x86/pmulhrsw.json"},{"mnemonic":"pmulhuw","slug":"pmulhuw","records":1,"summary":"Multiplies unsigned words, keeps high 16 bits.","page":"https://instructionsets.com/x86/pmulhuw/","api":"https://instructionsets.com/api/v1/x86/pmulhuw.json"},{"mnemonic":"pmulhw","slug":"pmulhw","records":2,"summary":"Multiplies 4 signed words and stores high 16 bits (MMX).","page":"https://instructionsets.com/x86/pmulhw/","api":"https://instructionsets.com/api/v1/x86/pmulhw.json"},{"mnemonic":"pmulld","slug":"pmulld","records":1,"summary":"Multiplies 32-bit integers, stores low 32-bit result.","page":"https://instructionsets.com/x86/pmulld/","api":"https://instructionsets.com/api/v1/x86/pmulld.json"},{"mnemonic":"pmullw","slug":"pmullw","records":2,"summary":"Multiplies 4 words and stores low 16 bits (MMX).","page":"https://instructionsets.com/x86/pmullw/","api":"https://instructionsets.com/api/v1/x86/pmullw.json"},{"mnemonic":"pmuludq","slug":"pmuludq","records":1,"summary":"Multiplies low 32-bits of each 64-bit chunk to 64-bit result.","page":"https://instructionsets.com/x86/pmuludq/","api":"https://instructionsets.com/api/v1/x86/pmuludq.json"},{"mnemonic":"pop","slug":"pop","records":1,"summary":"Loads operand from stack and increments SP.","page":"https://instructionsets.com/x86/pop/","api":"https://instructionsets.com/api/v1/x86/pop.json"},{"mnemonic":"popa","slug":"popa","records":1,"summary":"Pops into DI, SI, BP, SP, BX, DX, CX, AX (Invalid in 64-bit).","page":"https://instructionsets.com/x86/popa/","api":"https://instructionsets.com/api/v1/x86/popa.json"},{"mnemonic":"popcnt","slug":"popcnt","records":1,"summary":"Counts number of bits set to 1.","page":"https://instructionsets.com/x86/popcnt/","api":"https://instructionsets.com/api/v1/x86/popcnt.json"},{"mnemonic":"popf","slug":"popf","records":1,"summary":"Pops stack into EFLAGS.","page":"https://instructionsets.com/x86/popf/","api":"https://instructionsets.com/api/v1/x86/popf.json"},{"mnemonic":"por","slug":"por","records":2,"summary":"Bitwise OR of 64-bit MMX registers.","page":"https://instructionsets.com/x86/por/","api":"https://instructionsets.com/api/v1/x86/por.json"},{"mnemonic":"prefetchnta","slug":"prefetchnta","records":1,"summary":"Prefetches data to non-temporal cache structure (minimize pollution).","page":"https://instructionsets.com/x86/prefetchnta/","api":"https://instructionsets.com/api/v1/x86/prefetchnta.json"},{"mnemonic":"prefetcht0","slug":"prefetcht0","records":1,"summary":"Prefetches data to L1 cache.","page":"https://instructionsets.com/x86/prefetcht0/","api":"https://instructionsets.com/api/v1/x86/prefetcht0.json"},{"mnemonic":"prefetcht1","slug":"prefetcht1","records":1,"summary":"Hints to fetch data to L2 and L3 caches.","page":"https://instructionsets.com/x86/prefetcht1/","api":"https://instructionsets.com/api/v1/x86/prefetcht1.json"},{"mnemonic":"prefetcht2","slug":"prefetcht2","records":1,"summary":"Hints to fetch data to L3 cache only.","page":"https://instructionsets.com/x86/prefetcht2/","api":"https://instructionsets.com/api/v1/x86/prefetcht2.json"},{"mnemonic":"prefetchw","slug":"prefetchw","records":1,"summary":"Prefetches data with intent to write (RFO).","page":"https://instructionsets.com/x86/prefetchw/","api":"https://instructionsets.com/api/v1/x86/prefetchw.json"},{"mnemonic":"prefetchwt1","slug":"prefetchwt1","records":1,"summary":"Prefetches data to L2 (T1 hint) with intent to write.","page":"https://instructionsets.com/x86/prefetchwt1/","api":"https://instructionsets.com/api/v1/x86/prefetchwt1.json"},{"mnemonic":"psadbw","slug":"psadbw","records":1,"summary":"Computes absolute differences of bytes and sums them to words.","page":"https://instructionsets.com/x86/psadbw/","api":"https://instructionsets.com/api/v1/x86/psadbw.json"},{"mnemonic":"pshufb","slug":"pshufb","records":1,"summary":"Shuffles bytes according to indices in source operand.","page":"https://instructionsets.com/x86/pshufb/","api":"https://instructionsets.com/api/v1/x86/pshufb.json"},{"mnemonic":"pshufd","slug":"pshufd","records":1,"summary":"Shuffles 32-bit integers.","page":"https://instructionsets.com/x86/pshufd/","api":"https://instructionsets.com/api/v1/x86/pshufd.json"},{"mnemonic":"pshufhw","slug":"pshufhw","records":1,"summary":"Shuffles the high 4 words of XMM.","page":"https://instructionsets.com/x86/pshufhw/","api":"https://instructionsets.com/api/v1/x86/pshufhw.json"},{"mnemonic":"pshuflw","slug":"pshuflw","records":1,"summary":"Shuffles the low 4 words of XMM.","page":"https://instructionsets.com/x86/pshuflw/","api":"https://instructionsets.com/api/v1/x86/pshuflw.json"},{"mnemonic":"psignb","slug":"psignb","records":1,"summary":"Negates/Zeroes bytes in dest based on sign of src.","page":"https://instructionsets.com/x86/psignb/","api":"https://instructionsets.com/api/v1/x86/psignb.json"},{"mnemonic":"pslld","slug":"pslld","records":2,"summary":"Shifts doublewords left (MMX).","page":"https://instructionsets.com/x86/pslld/","api":"https://instructionsets.com/api/v1/x86/pslld.json"},{"mnemonic":"pslldq","slug":"pslldq","records":1,"summary":"Shifts the entire 128-bit register left by bytes.","page":"https://instructionsets.com/x86/pslldq/","api":"https://instructionsets.com/api/v1/x86/pslldq.json"},{"mnemonic":"psllq","slug":"psllq","records":1,"summary":"Shifts quadword left (MMX).","page":"https://instructionsets.com/x86/psllq/","api":"https://instructionsets.com/api/v1/x86/psllq.json"},{"mnemonic":"psllw","slug":"psllw","records":2,"summary":"Shifts words left (MMX).","page":"https://instructionsets.com/x86/psllw/","api":"https://instructionsets.com/api/v1/x86/psllw.json"},{"mnemonic":"psrad","slug":"psrad","records":2,"summary":"Shifts doublewords right arithmetic (MMX).","page":"https://instructionsets.com/x86/psrad/","api":"https://instructionsets.com/api/v1/x86/psrad.json"},{"mnemonic":"psraw","slug":"psraw","records":2,"summary":"Shifts words right arithmetic (MMX).","page":"https://instructionsets.com/x86/psraw/","api":"https://instructionsets.com/api/v1/x86/psraw.json"},{"mnemonic":"psrld","slug":"psrld","records":2,"summary":"Shifts doublewords right logical (MMX).","page":"https://instructionsets.com/x86/psrld/","api":"https://instructionsets.com/api/v1/x86/psrld.json"},{"mnemonic":"psrldq","slug":"psrldq","records":1,"summary":"Shifts the entire 128-bit register right by bytes.","page":"https://instructionsets.com/x86/psrldq/","api":"https://instructionsets.com/api/v1/x86/psrldq.json"},{"mnemonic":"psrlq","slug":"psrlq","records":1,"summary":"Shifts quadword right logical (MMX).","page":"https://instructionsets.com/x86/psrlq/","api":"https://instructionsets.com/api/v1/x86/psrlq.json"},{"mnemonic":"psrlw","slug":"psrlw","records":2,"summary":"Shifts words right logical (MMX).","page":"https://instructionsets.com/x86/psrlw/","api":"https://instructionsets.com/api/v1/x86/psrlw.json"},{"mnemonic":"psubb","slug":"psubb","records":1,"summary":"Subtracts 16 bytes.","page":"https://instructionsets.com/x86/psubb/","api":"https://instructionsets.com/api/v1/x86/psubb.json"},{"mnemonic":"psubd","slug":"psubd","records":1,"summary":"Subtracts 4 doublewords.","page":"https://instructionsets.com/x86/psubd/","api":"https://instructionsets.com/api/v1/x86/psubd.json"},{"mnemonic":"psubq","slug":"psubq","records":1,"summary":"Subtracts packed quadwords.","page":"https://instructionsets.com/x86/psubq/","api":"https://instructionsets.com/api/v1/x86/psubq.json"},{"mnemonic":"psubsb","slug":"psubsb","records":1,"summary":"Subtracts 8 signed bytes with saturation (MMX).","page":"https://instructionsets.com/x86/psubsb/","api":"https://instructionsets.com/api/v1/x86/psubsb.json"},{"mnemonic":"psubsw","slug":"psubsw","records":2,"summary":"Subtracts 4 signed words with saturation (MMX).","page":"https://instructionsets.com/x86/psubsw/","api":"https://instructionsets.com/api/v1/x86/psubsw.json"},{"mnemonic":"psubusb","slug":"psubusb","records":1,"summary":"Subtracts 8 unsigned bytes with saturation (MMX).","page":"https://instructionsets.com/x86/psubusb/","api":"https://instructionsets.com/api/v1/x86/psubusb.json"},{"mnemonic":"psubusw","slug":"psubusw","records":2,"summary":"Subtracts 4 unsigned words with saturation (MMX).","page":"https://instructionsets.com/x86/psubusw/","api":"https://instructionsets.com/api/v1/x86/psubusw.json"},{"mnemonic":"psubw","slug":"psubw","records":1,"summary":"Subtracts 8 words.","page":"https://instructionsets.com/x86/psubw/","api":"https://instructionsets.com/api/v1/x86/psubw.json"},{"mnemonic":"ptest","slug":"ptest","records":1,"summary":"Bitwise compare of 128-bit value (AND) setting flags.","page":"https://instructionsets.com/x86/ptest/","api":"https://instructionsets.com/api/v1/x86/ptest.json"},{"mnemonic":"ptwrite","slug":"ptwrite","records":1,"summary":"Writes data to the Intel Processor Trace stream.","page":"https://instructionsets.com/x86/ptwrite/","api":"https://instructionsets.com/api/v1/x86/ptwrite.json"},{"mnemonic":"punpckhbw","slug":"punpckhbw","records":1,"summary":"Interleaves high bytes from two sources.","page":"https://instructionsets.com/x86/punpckhbw/","api":"https://instructionsets.com/api/v1/x86/punpckhbw.json"},{"mnemonic":"punpckhdq","slug":"punpckhdq","records":1,"summary":"Interleaves high doublewords.","page":"https://instructionsets.com/x86/punpckhdq/","api":"https://instructionsets.com/api/v1/x86/punpckhdq.json"},{"mnemonic":"punpckhqdq","slug":"punpckhqdq","records":1,"summary":"Interleaves high quadwords.","page":"https://instructionsets.com/x86/punpckhqdq/","api":"https://instructionsets.com/api/v1/x86/punpckhqdq.json"},{"mnemonic":"punpckhwd","slug":"punpckhwd","records":1,"summary":"Interleaves high words.","page":"https://instructionsets.com/x86/punpckhwd/","api":"https://instructionsets.com/api/v1/x86/punpckhwd.json"},{"mnemonic":"punpcklbw","slug":"punpcklbw","records":1,"summary":"Interleaves low bytes from two sources.","page":"https://instructionsets.com/x86/punpcklbw/","api":"https://instructionsets.com/api/v1/x86/punpcklbw.json"},{"mnemonic":"punpckldq","slug":"punpckldq","records":1,"summary":"Interleaves low doublewords.","page":"https://instructionsets.com/x86/punpckldq/","api":"https://instructionsets.com/api/v1/x86/punpckldq.json"},{"mnemonic":"punpcklqdq","slug":"punpcklqdq","records":1,"summary":"Interleaves low quadwords.","page":"https://instructionsets.com/x86/punpcklqdq/","api":"https://instructionsets.com/api/v1/x86/punpcklqdq.json"},{"mnemonic":"punpcklwd","slug":"punpcklwd","records":1,"summary":"Interleaves low words.","page":"https://instructionsets.com/x86/punpcklwd/","api":"https://instructionsets.com/api/v1/x86/punpcklwd.json"},{"mnemonic":"push","slug":"push","records":1,"summary":"Decrements SP and stores operand on stack.","page":"https://instructionsets.com/x86/push/","api":"https://instructionsets.com/api/v1/x86/push.json"},{"mnemonic":"pusha","slug":"pusha","records":1,"summary":"Pushes AX, CX, DX, BX, SP, BP, SI, DI (Invalid in 64-bit).","page":"https://instructionsets.com/x86/pusha/","api":"https://instructionsets.com/api/v1/x86/pusha.json"},{"mnemonic":"pushf","slug":"pushf","records":1,"summary":"Pushes EFLAGS onto stack.","page":"https://instructionsets.com/x86/pushf/","api":"https://instructionsets.com/api/v1/x86/pushf.json"},{"mnemonic":"pxor","slug":"pxor","records":2,"summary":"Bitwise XOR of 64-bit MMX registers.","page":"https://instructionsets.com/x86/pxor/","api":"https://instructionsets.com/api/v1/x86/pxor.json"},{"mnemonic":"rcl","slug":"rcl","records":1,"summary":"Rotates bits left through Carry Flag.","page":"https://instructionsets.com/x86/rcl/","api":"https://instructionsets.com/api/v1/x86/rcl.json"},{"mnemonic":"rcpps","slug":"rcpps","records":1,"summary":"Approximate reciprocal (1/x) of four 32-bit floats.","page":"https://instructionsets.com/x86/rcpps/","api":"https://instructionsets.com/api/v1/x86/rcpps.json"},{"mnemonic":"rcpss","slug":"rcpss","records":1,"summary":"Computes approximate reciprocal (1/x) of low float.","page":"https://instructionsets.com/x86/rcpss/","api":"https://instructionsets.com/api/v1/x86/rcpss.json"},{"mnemonic":"rcr","slug":"rcr","records":1,"summary":"Rotates bits right through Carry Flag.","page":"https://instructionsets.com/x86/rcr/","api":"https://instructionsets.com/api/v1/x86/rcr.json"},{"mnemonic":"rdfsbase","slug":"rdfsbase","records":1,"summary":"Reads the FS base address into a register.","page":"https://instructionsets.com/x86/rdfsbase/","api":"https://instructionsets.com/api/v1/x86/rdfsbase.json"},{"mnemonic":"rdgsbase","slug":"rdgsbase","records":1,"summary":"Reads the GS base address into a register.","page":"https://instructionsets.com/x86/rdgsbase/","api":"https://instructionsets.com/api/v1/x86/rdgsbase.json"},{"mnemonic":"rdmsr","slug":"rdmsr","records":1,"summary":"Reads MSR specified by ECX into EDX:EAX (Privileged).","page":"https://instructionsets.com/x86/rdmsr/","api":"https://instructionsets.com/api/v1/x86/rdmsr.json"},{"mnemonic":"rdpid","slug":"rdpid","records":1,"summary":"Reads the processor ID (TSC_AUX) into register.","page":"https://instructionsets.com/x86/rdpid/","api":"https://instructionsets.com/api/v1/x86/rdpid.json"},{"mnemonic":"rdpkru","slug":"rdpkru","records":1,"summary":"Reads PKRU register into EAX (User-mode pages).","page":"https://instructionsets.com/x86/rdpkru/","api":"https://instructionsets.com/api/v1/x86/rdpkru.json"},{"mnemonic":"rdpmc","slug":"rdpmc","records":1,"summary":"Reads performance counter specified by ECX into EDX:EAX.","page":"https://instructionsets.com/x86/rdpmc/","api":"https://instructionsets.com/api/v1/x86/rdpmc.json"},{"mnemonic":"rdrand","slug":"rdrand","records":1,"summary":"Retrieves a hardware-generated random number.","page":"https://instructionsets.com/x86/rdrand/","api":"https://instructionsets.com/api/v1/x86/rdrand.json"},{"mnemonic":"rdseed","slug":"rdseed","records":1,"summary":"Retrieves a random seed from hardware entropy source.","page":"https://instructionsets.com/x86/rdseed/","api":"https://instructionsets.com/api/v1/x86/rdseed.json"},{"mnemonic":"rdsspq","slug":"rdsspq","records":1,"summary":"Reads the current shadow stack pointer into a register.","page":"https://instructionsets.com/x86/rdsspq/","api":"https://instructionsets.com/api/v1/x86/rdsspq.json"},{"mnemonic":"rdtsc","slug":"rdtsc","records":1,"summary":"Reads the time-stamp counter into EDX:EAX.","page":"https://instructionsets.com/x86/rdtsc/","api":"https://instructionsets.com/api/v1/x86/rdtsc.json"},{"mnemonic":"rdtscp","slug":"rdtscp","records":1,"summary":"Reads TSC into EDX:EAX and Processor ID into ECX.","page":"https://instructionsets.com/x86/rdtscp/","api":"https://instructionsets.com/api/v1/x86/rdtscp.json"},{"mnemonic":"rep movs","slug":"rep_movs","records":1,"summary":"Moves ECX bytes/words from [ESI] to [EDI].","page":"https://instructionsets.com/x86/rep_movs/","api":"https://instructionsets.com/api/v1/x86/rep_movs.json"},{"mnemonic":"rep stos","slug":"rep_stos","records":1,"summary":"Fills [EDI] with AL/AX/EAX for ECX repeats.","page":"https://instructionsets.com/x86/rep_stos/","api":"https://instructionsets.com/api/v1/x86/rep_stos.json"},{"mnemonic":"repe cmps","slug":"repe_cmps","records":1,"summary":"Compares [ESI] and [EDI] until mismatch or ECX=0.","page":"https://instructionsets.com/x86/repe_cmps/","api":"https://instructionsets.com/api/v1/x86/repe_cmps.json"},{"mnemonic":"repne scas","slug":"repne_scas","records":1,"summary":"Scans [EDI] for AL/AX/EAX until match or ECX=0.","page":"https://instructionsets.com/x86/repne_scas/","api":"https://instructionsets.com/api/v1/x86/repne_scas.json"},{"mnemonic":"ret","slug":"ret","records":1,"summary":"Pop EIP/RIP and resume execution.","page":"https://instructionsets.com/x86/ret/","api":"https://instructionsets.com/api/v1/x86/ret.json"},{"mnemonic":"rol","slug":"rol","records":1,"summary":"Rotates bits left.","page":"https://instructionsets.com/x86/rol/","api":"https://instructionsets.com/api/v1/x86/rol.json"},{"mnemonic":"ror","slug":"ror","records":1,"summary":"Rotates bits right.","page":"https://instructionsets.com/x86/ror/","api":"https://instructionsets.com/api/v1/x86/ror.json"},{"mnemonic":"rorx","slug":"rorx","records":1,"summary":"Rotate right with immediate. No flags update.","page":"https://instructionsets.com/x86/rorx/","api":"https://instructionsets.com/api/v1/x86/rorx.json"},{"mnemonic":"roundpd","slug":"roundpd","records":1,"summary":"Rounds all packed doubles according to immediate mode.","page":"https://instructionsets.com/x86/roundpd/","api":"https://instructionsets.com/api/v1/x86/roundpd.json"},{"mnemonic":"roundps","slug":"roundps","records":1,"summary":"Rounds all packed floats according to immediate mode.","page":"https://instructionsets.com/x86/roundps/","api":"https://instructionsets.com/api/v1/x86/roundps.json"},{"mnemonic":"roundsd","slug":"roundsd","records":1,"summary":"Rounds low double according to immediate mode.","page":"https://instructionsets.com/x86/roundsd/","api":"https://instructionsets.com/api/v1/x86/roundsd.json"},{"mnemonic":"roundss","slug":"roundss","records":1,"summary":"Rounds low float according to immediate mode.","page":"https://instructionsets.com/x86/roundss/","api":"https://instructionsets.com/api/v1/x86/roundss.json"},{"mnemonic":"rsm","slug":"rsm","records":1,"summary":"Exits SMM and returns to previous state (Privileged).","page":"https://instructionsets.com/x86/rsm/","api":"https://instructionsets.com/api/v1/x86/rsm.json"},{"mnemonic":"rsqrtps","slug":"rsqrtps","records":1,"summary":"Approximate reciprocal sqrt (1/sqrt(x)) of four 32-bit floats.","page":"https://instructionsets.com/x86/rsqrtps/","api":"https://instructionsets.com/api/v1/x86/rsqrtps.json"},{"mnemonic":"rsqrtss","slug":"rsqrtss","records":1,"summary":"Computes approximate reciprocal sqrt (1/sqrt(x)) of low float.","page":"https://instructionsets.com/x86/rsqrtss/","api":"https://instructionsets.com/api/v1/x86/rsqrtss.json"},{"mnemonic":"rstorssp","slug":"rstorssp","records":1,"summary":"Restores SSP from memory token.","page":"https://instructionsets.com/x86/rstorssp/","api":"https://instructionsets.com/api/v1/x86/rstorssp.json"},{"mnemonic":"sahf","slug":"sahf","records":1,"summary":"Loads SF, ZF, AF, PF, and CF from AH.","page":"https://instructionsets.com/x86/sahf/","api":"https://instructionsets.com/api/v1/x86/sahf.json"},{"mnemonic":"sal","slug":"sal","records":1,"summary":"Shifts bits left (Alias for SHL).","page":"https://instructionsets.com/x86/sal/","api":"https://instructionsets.com/api/v1/x86/sal.json"},{"mnemonic":"sar","slug":"sar","records":1,"summary":"Shifts bits right, preserving sign bit.","page":"https://instructionsets.com/x86/sar/","api":"https://instructionsets.com/api/v1/x86/sar.json"},{"mnemonic":"sarx","slug":"sarx","records":1,"summary":"Arithmetic right shift, count in register. No flags update.","page":"https://instructionsets.com/x86/sarx/","api":"https://instructionsets.com/api/v1/x86/sarx.json"},{"mnemonic":"saveprevssp","slug":"saveprevssp","records":1,"summary":"Saves the previous SSP to the shadow stack token.","page":"https://instructionsets.com/x86/saveprevssp/","api":"https://instructionsets.com/api/v1/x86/saveprevssp.json"},{"mnemonic":"sbb","slug":"sbb","records":1,"summary":"Subtracts operands and the Carry Flag (CF).","page":"https://instructionsets.com/x86/sbb/","api":"https://instructionsets.com/api/v1/x86/sbb.json"},{"mnemonic":"scas","slug":"scas","records":1,"summary":"Compares AL/AX/EAX with memory at [EDI].","page":"https://instructionsets.com/x86/scas/","api":"https://instructionsets.com/api/v1/x86/scas.json"},{"mnemonic":"scasd","slug":"scasd","records":1,"summary":"Compares EAX with memory at [EDI].","page":"https://instructionsets.com/x86/scasd/","api":"https://instructionsets.com/api/v1/x86/scasd.json"},{"mnemonic":"scasq","slug":"scasq","records":1,"summary":"Compares RAX with memory at [RDI].","page":"https://instructionsets.com/x86/scasq/","api":"https://instructionsets.com/api/v1/x86/scasq.json"},{"mnemonic":"scasw","slug":"scasw","records":1,"summary":"Compares AX with memory at [EDI].","page":"https://instructionsets.com/x86/scasw/","api":"https://instructionsets.com/api/v1/x86/scasw.json"},{"mnemonic":"senduipi","slug":"senduipi","records":1,"summary":"Sends a User IPI to another processor.","page":"https://instructionsets.com/x86/senduipi/","api":"https://instructionsets.com/api/v1/x86/senduipi.json"},{"mnemonic":"serialize","slug":"serialize","records":1,"summary":"Forces serialization of instruction fetch/execution.","page":"https://instructionsets.com/x86/serialize/","api":"https://instructionsets.com/api/v1/x86/serialize.json"},{"mnemonic":"seta","slug":"seta","records":1,"summary":"Sets byte to 1 if CF=0 and ZF=0.","page":"https://instructionsets.com/x86/seta/","api":"https://instructionsets.com/api/v1/x86/seta.json"},{"mnemonic":"setae","slug":"setae","records":1,"summary":"Sets byte to 1 if CF=0.","page":"https://instructionsets.com/x86/setae/","api":"https://instructionsets.com/api/v1/x86/setae.json"},{"mnemonic":"setb","slug":"setb","records":1,"summary":"Sets byte to 1 if CF=1.","page":"https://instructionsets.com/x86/setb/","api":"https://instructionsets.com/api/v1/x86/setb.json"},{"mnemonic":"setbe","slug":"setbe","records":1,"summary":"Sets byte to 1 if CF=1 or ZF=1.","page":"https://instructionsets.com/x86/setbe/","api":"https://instructionsets.com/api/v1/x86/setbe.json"},{"mnemonic":"setcc","slug":"setcc","records":1,"summary":"Sets byte to 1 if condition met, else 0 (e.g., SETE, SETZ).","page":"https://instructionsets.com/x86/setcc/","api":"https://instructionsets.com/api/v1/x86/setcc.json"},{"mnemonic":"setg","slug":"setg","records":1,"summary":"Sets byte to 1 if ZF=0 and SF=OF.","page":"https://instructionsets.com/x86/setg/","api":"https://instructionsets.com/api/v1/x86/setg.json"},{"mnemonic":"setge","slug":"setge","records":1,"summary":"Sets byte to 1 if SF=OF.","page":"https://instructionsets.com/x86/setge/","api":"https://instructionsets.com/api/v1/x86/setge.json"},{"mnemonic":"setl","slug":"setl","records":1,"summary":"Sets byte to 1 if SF!=OF.","page":"https://instructionsets.com/x86/setl/","api":"https://instructionsets.com/api/v1/x86/setl.json"},{"mnemonic":"setle","slug":"setle","records":1,"summary":"Sets byte to 1 if ZF=1 or SF!=OF.","page":"https://instructionsets.com/x86/setle/","api":"https://instructionsets.com/api/v1/x86/setle.json"},{"mnemonic":"setno","slug":"setno","records":1,"summary":"Sets byte to 1 if OF=0.","page":"https://instructionsets.com/x86/setno/","api":"https://instructionsets.com/api/v1/x86/setno.json"},{"mnemonic":"setnp","slug":"setnp","records":1,"summary":"Sets byte to 1 if PF=0 (Odd Parity).","page":"https://instructionsets.com/x86/setnp/","api":"https://instructionsets.com/api/v1/x86/setnp.json"},{"mnemonic":"setns","slug":"setns","records":1,"summary":"Sets byte to 1 if SF=0 (Positive).","page":"https://instructionsets.com/x86/setns/","api":"https://instructionsets.com/api/v1/x86/setns.json"},{"mnemonic":"setnz","slug":"setnz","records":1,"summary":"Sets byte to 1 if ZF=0.","page":"https://instructionsets.com/x86/setnz/","api":"https://instructionsets.com/api/v1/x86/setnz.json"},{"mnemonic":"seto","slug":"seto","records":1,"summary":"Sets byte to 1 if OF=1.","page":"https://instructionsets.com/x86/seto/","api":"https://instructionsets.com/api/v1/x86/seto.json"},{"mnemonic":"setp","slug":"setp","records":1,"summary":"Sets byte to 1 if PF=1 (Even Parity).","page":"https://instructionsets.com/x86/setp/","api":"https://instructionsets.com/api/v1/x86/setp.json"},{"mnemonic":"sets","slug":"sets","records":1,"summary":"Sets byte to 1 if SF=1 (Negative).","page":"https://instructionsets.com/x86/sets/","api":"https://instructionsets.com/api/v1/x86/sets.json"},{"mnemonic":"setz","slug":"setz","records":1,"summary":"Sets byte to 1 if ZF=1.","page":"https://instructionsets.com/x86/setz/","api":"https://instructionsets.com/api/v1/x86/setz.json"},{"mnemonic":"sfence","slug":"sfence","records":1,"summary":"Serializes store operations (Wait for prior stores to complete).","page":"https://instructionsets.com/x86/sfence/","api":"https://instructionsets.com/api/v1/x86/sfence.json"},{"mnemonic":"sgdt","slug":"sgdt","records":1,"summary":"Stores GDT limit and base address to memory.","page":"https://instructionsets.com/x86/sgdt/","api":"https://instructionsets.com/api/v1/x86/sgdt.json"},{"mnemonic":"sha1msg1","slug":"sha1msg1","records":1,"summary":"Performs intermediate calculation for SHA1 message schedule.","page":"https://instructionsets.com/x86/sha1msg1/","api":"https://instructionsets.com/api/v1/x86/sha1msg1.json"},{"mnemonic":"sha1msg2","slug":"sha1msg2","records":1,"summary":"Performs final calculation for SHA1 message schedule.","page":"https://instructionsets.com/x86/sha1msg2/","api":"https://instructionsets.com/api/v1/x86/sha1msg2.json"},{"mnemonic":"sha1nexte","slug":"sha1nexte","records":1,"summary":"Calculates SHA1 state variable E.","page":"https://instructionsets.com/x86/sha1nexte/","api":"https://instructionsets.com/api/v1/x86/sha1nexte.json"},{"mnemonic":"sha1rnds4","slug":"sha1rnds4","records":1,"summary":"Performs 4 rounds of SHA1 operation.","page":"https://instructionsets.com/x86/sha1rnds4/","api":"https://instructionsets.com/api/v1/x86/sha1rnds4.json"},{"mnemonic":"sha256msg1","slug":"sha256msg1","records":1,"summary":"Performs intermediate calculation for SHA256 message schedule.","page":"https://instructionsets.com/x86/sha256msg1/","api":"https://instructionsets.com/api/v1/x86/sha256msg1.json"},{"mnemonic":"sha256msg2","slug":"sha256msg2","records":1,"summary":"Performs final calculation for SHA256 message schedule.","page":"https://instructionsets.com/x86/sha256msg2/","api":"https://instructionsets.com/api/v1/x86/sha256msg2.json"},{"mnemonic":"sha256rnds2","slug":"sha256rnds2","records":1,"summary":"Performs 2 rounds of SHA256 operation.","page":"https://instructionsets.com/x86/sha256rnds2/","api":"https://instructionsets.com/api/v1/x86/sha256rnds2.json"},{"mnemonic":"shl","slug":"shl","records":1,"summary":"Shifts bits left (same as SAL).","page":"https://instructionsets.com/x86/shl/","api":"https://instructionsets.com/api/v1/x86/shl.json"},{"mnemonic":"shld","slug":"shld","records":1,"summary":"Shifts dest left, filling with bits from src.","page":"https://instructionsets.com/x86/shld/","api":"https://instructionsets.com/api/v1/x86/shld.json"},{"mnemonic":"shlx","slug":"shlx","records":1,"summary":"Logical left shift, count in register. No flags update.","page":"https://instructionsets.com/x86/shlx/","api":"https://instructionsets.com/api/v1/x86/shlx.json"},{"mnemonic":"shr","slug":"shr","records":1,"summary":"Shifts bits right, filling with zeros.","page":"https://instructionsets.com/x86/shr/","api":"https://instructionsets.com/api/v1/x86/shr.json"},{"mnemonic":"shrd","slug":"shrd","records":1,"summary":"Shifts dest right, filling with bits from src.","page":"https://instructionsets.com/x86/shrd/","api":"https://instructionsets.com/api/v1/x86/shrd.json"},{"mnemonic":"shrx","slug":"shrx","records":1,"summary":"Logical right shift, count in register. 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vector.","page":"https://instructionsets.com/x86/vpermb/","api":"https://instructionsets.com/api/v1/x86/vpermb.json"},{"mnemonic":"vpermd","slug":"vpermd","records":1,"summary":"Full permutation of 8 integers using indices from a register.","page":"https://instructionsets.com/x86/vpermd/","api":"https://instructionsets.com/api/v1/x86/vpermd.json"},{"mnemonic":"vpermi2b","slug":"vpermi2b","records":1,"summary":"Shuffles bytes from two ZMM registers into destination.","page":"https://instructionsets.com/x86/vpermi2b/","api":"https://instructionsets.com/api/v1/x86/vpermi2b.json"},{"mnemonic":"vpermi2d","slug":"vpermi2d","records":1,"summary":"Shuffles doublewords from two ZMM registers into destination.","page":"https://instructionsets.com/x86/vpermi2d/","api":"https://instructionsets.com/api/v1/x86/vpermi2d.json"},{"mnemonic":"vpermi2q","slug":"vpermi2q","records":1,"summary":"Shuffles quadwords from two ZMM registers into destination.","page":"https://instructionsets.com/x86/vpermi2q/","api":"https://instructionsets.com/api/v1/x86/vpermi2q.json"},{"mnemonic":"vpermilpd","slug":"vpermilpd","records":1,"summary":"Shuffles doubles within 128-bit lanes (AVX).","page":"https://instructionsets.com/x86/vpermilpd/","api":"https://instructionsets.com/api/v1/x86/vpermilpd.json"},{"mnemonic":"vpermilps","slug":"vpermilps","records":1,"summary":"Shuffles floats within 128-bit lanes (AVX).","page":"https://instructionsets.com/x86/vpermilps/","api":"https://instructionsets.com/api/v1/x86/vpermilps.json"},{"mnemonic":"vpermps","slug":"vpermps","records":1,"summary":"Full permutation of 8 floats using indices.","page":"https://instructionsets.com/x86/vpermps/","api":"https://instructionsets.com/api/v1/x86/vpermps.json"},{"mnemonic":"vpermq","slug":"vpermq","records":1,"summary":"Shuffles quadwords within 256-bit lanes using immediate.","page":"https://instructionsets.com/x86/vpermq/","api":"https://instructionsets.com/api/v1/x86/vpermq.json"},{"mnemonic":"vpermt2b","slug":"vpermt2b","records":1,"summary":"Shuffles bytes from two sources, overwriting index.","page":"https://instructionsets.com/x86/vpermt2b/","api":"https://instructionsets.com/api/v1/x86/vpermt2b.json"},{"mnemonic":"vpermt2d","slug":"vpermt2d","records":1,"summary":"Shuffles 2 sources, overwriting the index register.","page":"https://instructionsets.com/x86/vpermt2d/","api":"https://instructionsets.com/api/v1/x86/vpermt2d.json"},{"mnemonic":"vpermt2q","slug":"vpermt2q","records":1,"summary":"Shuffles 2 sources, overwriting the index register (Quadword).","page":"https://instructionsets.com/x86/vpermt2q/","api":"https://instructionsets.com/api/v1/x86/vpermt2q.json"},{"mnemonic":"vpermw","slug":"vpermw","records":1,"summary":"Full permutation of 32 words using indices.","page":"https://instructionsets.com/x86/vpermw/","api":"https://instructionsets.com/api/v1/x86/vpermw.json"},{"mnemonic":"vpexpandb","slug":"vpexpandb","records":1,"summary":"Expands bytes from memory into sparse locations in ZMM.","page":"https://instructionsets.com/x86/vpexpandb/","api":"https://instructionsets.com/api/v1/x86/vpexpandb.json"},{"mnemonic":"vpexpandw","slug":"vpexpandw","records":1,"summary":"Expands words from memory into sparse locations in ZMM.","page":"https://instructionsets.com/x86/vpexpandw/","api":"https://instructionsets.com/api/v1/x86/vpexpandw.json"},{"mnemonic":"vpgatherdd","slug":"vpgatherdd","records":1,"summary":"Gathers 32-bit integers using 32-bit indices.","page":"https://instructionsets.com/x86/vpgatherdd/","api":"https://instructionsets.com/api/v1/x86/vpgatherdd.json"},{"mnemonic":"vpgatherdq","slug":"vpgatherdq","records":1,"summary":"Gathers 64-bit integers using 32-bit indices.","page":"https://instructionsets.com/x86/vpgatherdq/","api":"https://instructionsets.com/api/v1/x86/vpgatherdq.json"},{"mnemonic":"vpgatherqd","slug":"vpgatherqd","records":1,"summary":"Gathers 32-bit integers using 64-bit indices.","page":"https://instructionsets.com/x86/vpgatherqd/","api":"https://instructionsets.com/api/v1/x86/vpgatherqd.json"},{"mnemonic":"vpgatherqq","slug":"vpgatherqq","records":1,"summary":"Gathers 64-bit integers using 64-bit indices.","page":"https://instructionsets.com/x86/vpgatherqq/","api":"https://instructionsets.com/api/v1/x86/vpgatherqq.json"},{"mnemonic":"vphaddbd","slug":"vphaddbd","records":1,"summary":"Adds adjacent bytes to doublewords.","page":"https://instructionsets.com/x86/vphaddbd/","api":"https://instructionsets.com/api/v1/x86/vphaddbd.json"},{"mnemonic":"vphaddbq","slug":"vphaddbq","records":1,"summary":"Adds adjacent bytes to quadwords.","page":"https://instructionsets.com/x86/vphaddbq/","api":"https://instructionsets.com/api/v1/x86/vphaddbq.json"},{"mnemonic":"vphaddbw","slug":"vphaddbw","records":1,"summary":"Adds adjacent bytes to words.","page":"https://instructionsets.com/x86/vphaddbw/","api":"https://instructionsets.com/api/v1/x86/vphaddbw.json"},{"mnemonic":"vphadddq","slug":"vphadddq","records":1,"summary":"Adds adjacent doublewords to quadwords.","page":"https://instructionsets.com/x86/vphadddq/","api":"https://instructionsets.com/api/v1/x86/vphadddq.json"},{"mnemonic":"vphaddwd","slug":"vphaddwd","records":1,"summary":"Adds adjacent words to doublewords.","page":"https://instructionsets.com/x86/vphaddwd/","api":"https://instructionsets.com/api/v1/x86/vphaddwd.json"},{"mnemonic":"vphaddwq","slug":"vphaddwq","records":1,"summary":"Adds adjacent words to quadwords.","page":"https://instructionsets.com/x86/vphaddwq/","api":"https://instructionsets.com/api/v1/x86/vphaddwq.json"},{"mnemonic":"vplzcntd","slug":"vplzcntd","records":1,"summary":"Counts leading zeros for each doubleword element.","page":"https://instructionsets.com/x86/vplzcntd/","api":"https://instructionsets.com/api/v1/x86/vplzcntd.json"},{"mnemonic":"vplzcntq","slug":"vplzcntq","records":1,"summary":"Counts leading zeros for each quadword element.","page":"https://instructionsets.com/x86/vplzcntq/","api":"https://instructionsets.com/api/v1/x86/vplzcntq.json"},{"mnemonic":"vpmacssww","slug":"vpmacssww","records":1,"summary":"Multiply-accumulate signed words with saturation.","page":"https://instructionsets.com/x86/vpmacssww/","api":"https://instructionsets.com/api/v1/x86/vpmacssww.json"},{"mnemonic":"vpmacsww","slug":"vpmacsww","records":1,"summary":"Multiply-accumulate signed words.","page":"https://instructionsets.com/x86/vpmacsww/","api":"https://instructionsets.com/api/v1/x86/vpmacsww.json"},{"mnemonic":"vpmadd52huq","slug":"vpmadd52huq","records":1,"summary":"Fused multiply-add for 52-bit integers (High 52 bits).","page":"https://instructionsets.com/x86/vpmadd52huq/","api":"https://instructionsets.com/api/v1/x86/vpmadd52huq.json"},{"mnemonic":"vpmadd52luq","slug":"vpmadd52luq","records":1,"summary":"Fused multiply-add for 52-bit integers (Low 52 bits).","page":"https://instructionsets.com/x86/vpmadd52luq/","api":"https://instructionsets.com/api/v1/x86/vpmadd52luq.json"},{"mnemonic":"vpmaxsq","slug":"vpmaxsq","records":1,"summary":"Returns maximum of signed 64-bit integers.","page":"https://instructionsets.com/x86/vpmaxsq/","api":"https://instructionsets.com/api/v1/x86/vpmaxsq.json"},{"mnemonic":"vpmaxuq","slug":"vpmaxuq","records":1,"summary":"Returns maximum of unsigned 64-bit integers.","page":"https://instructionsets.com/x86/vpmaxuq/","api":"https://instructionsets.com/api/v1/x86/vpmaxuq.json"},{"mnemonic":"vpminsq","slug":"vpminsq","records":1,"summary":"Returns minimum of signed 64-bit integers.","page":"https://instructionsets.com/x86/vpminsq/","api":"https://instructionsets.com/api/v1/x86/vpminsq.json"},{"mnemonic":"vpminuq","slug":"vpminuq","records":1,"summary":"Returns minimum of unsigned 64-bit integers.","page":"https://instructionsets.com/x86/vpminuq/","api":"https://instructionsets.com/api/v1/x86/vpminuq.json"},{"mnemonic":"vpmovb2m","slug":"vpmovb2m","records":1,"summary":"Moves byte integer mask from ZMM to k-register.","page":"https://instructionsets.com/x86/vpmovb2m/","api":"https://instructionsets.com/api/v1/x86/vpmovb2m.json"},{"mnemonic":"vpmovd2m","slug":"vpmovd2m","records":1,"summary":"Moves doubleword integer mask from ZMM to k-register.","page":"https://instructionsets.com/x86/vpmovd2m/","api":"https://instructionsets.com/api/v1/x86/vpmovd2m.json"},{"mnemonic":"vpmovdb","slug":"vpmovdb","records":1,"summary":"Down-converts 32-bit integers to 8-bit.","page":"https://instructionsets.com/x86/vpmovdb/","api":"https://instructionsets.com/api/v1/x86/vpmovdb.json"},{"mnemonic":"vpmovm2b","slug":"vpmovm2b","records":1,"summary":"Expands k-register bits to byte elements in ZMM.","page":"https://instructionsets.com/x86/vpmovm2b/","api":"https://instructionsets.com/api/v1/x86/vpmovm2b.json"},{"mnemonic":"vpmovm2d","slug":"vpmovm2d","records":1,"summary":"Expands k-register bits to doubleword elements in ZMM.","page":"https://instructionsets.com/x86/vpmovm2d/","api":"https://instructionsets.com/api/v1/x86/vpmovm2d.json"},{"mnemonic":"vpmovm2q","slug":"vpmovm2q","records":1,"summary":"Expands k-register bits to quadword elements in ZMM.","page":"https://instructionsets.com/x86/vpmovm2q/","api":"https://instructionsets.com/api/v1/x86/vpmovm2q.json"},{"mnemonic":"vpmovm2w","slug":"vpmovm2w","records":1,"summary":"Expands k-register bits to word elements in ZMM.","page":"https://instructionsets.com/x86/vpmovm2w/","api":"https://instructionsets.com/api/v1/x86/vpmovm2w.json"},{"mnemonic":"vpmovq2m","slug":"vpmovq2m","records":1,"summary":"Moves quadword integer mask from ZMM to k-register.","page":"https://instructionsets.com/x86/vpmovq2m/","api":"https://instructionsets.com/api/v1/x86/vpmovq2m.json"},{"mnemonic":"vpmovsqb","slug":"vpmovsqb","records":1,"summary":"Down-converts 64-bit integers to 8-bit signed saturate.","page":"https://instructionsets.com/x86/vpmovsqb/","api":"https://instructionsets.com/api/v1/x86/vpmovsqb.json"},{"mnemonic":"vpmovswb","slug":"vpmovswb","records":1,"summary":"Down-converts 16-bit integers to 8-bit signed saturate.","page":"https://instructionsets.com/x86/vpmovswb/","api":"https://instructionsets.com/api/v1/x86/vpmovswb.json"},{"mnemonic":"vpmovusdb","slug":"vpmovusdb","records":1,"summary":"Down-converts 32-bit to 8-bit with unsigned saturation.","page":"https://instructionsets.com/x86/vpmovusdb/","api":"https://instructionsets.com/api/v1/x86/vpmovusdb.json"},{"mnemonic":"vpmovusqb","slug":"vpmovusqb","records":1,"summary":"Down-converts 64-bit integers to 8-bit unsigned saturate.","page":"https://instructionsets.com/x86/vpmovusqb/","api":"https://instructionsets.com/api/v1/x86/vpmovusqb.json"},{"mnemonic":"vpmovuswb","slug":"vpmovuswb","records":1,"summary":"Down-converts 16-bit integers to 8-bit unsigned saturate.","page":"https://instructionsets.com/x86/vpmovuswb/","api":"https://instructionsets.com/api/v1/x86/vpmovuswb.json"},{"mnemonic":"vpmovw2m","slug":"vpmovw2m","records":1,"summary":"Moves word integer mask from ZMM to k-register.","page":"https://instructionsets.com/x86/vpmovw2m/","api":"https://instructionsets.com/api/v1/x86/vpmovw2m.json"},{"mnemonic":"vpmulld","slug":"vpmulld","records":1,"summary":"Multiplies 8 integers (256-bit).","page":"https://instructionsets.com/x86/vpmulld/","api":"https://instructionsets.com/api/v1/x86/vpmulld.json"},{"mnemonic":"vpmullq","slug":"vpmullq","records":1,"summary":"Multiplies 64-bit integers and keeps low 64-bit result.","page":"https://instructionsets.com/x86/vpmullq/","api":"https://instructionsets.com/api/v1/x86/vpmullq.json"},{"mnemonic":"vpmultishiftqb","slug":"vpmultishiftqb","records":1,"summary":"Selects bytes from each 64-bit element based on shift control.","page":"https://instructionsets.com/x86/vpmultishiftqb/","api":"https://instructionsets.com/api/v1/x86/vpmultishiftqb.json"},{"mnemonic":"vpopcntb","slug":"vpopcntb","records":1,"summary":"Counts set bits in each byte.","page":"https://instructionsets.com/x86/vpopcntb/","api":"https://instructionsets.com/api/v1/x86/vpopcntb.json"},{"mnemonic":"vpopcntd","slug":"vpopcntd","records":1,"summary":"Counts set bits in each doubleword element.","page":"https://instructionsets.com/x86/vpopcntd/","api":"https://instructionsets.com/api/v1/x86/vpopcntd.json"},{"mnemonic":"vpopcntq","slug":"vpopcntq","records":1,"summary":"Counts set bits in each quadword element.","page":"https://instructionsets.com/x86/vpopcntq/","api":"https://instructionsets.com/api/v1/x86/vpopcntq.json"},{"mnemonic":"vpopcntw","slug":"vpopcntw","records":1,"summary":"Counts set bits in each word element.","page":"https://instructionsets.com/x86/vpopcntw/","api":"https://instructionsets.com/api/v1/x86/vpopcntw.json"},{"mnemonic":"vprolq","slug":"vprolq","records":1,"summary":"Rotates 64-bit integers left.","page":"https://instructionsets.com/x86/vprolq/","api":"https://instructionsets.com/api/v1/x86/vprolq.json"},{"mnemonic":"vprolvd","slug":"vprolvd","records":1,"summary":"Rotates doublewords left by amounts in second vector.","page":"https://instructionsets.com/x86/vprolvd/","api":"https://instructionsets.com/api/v1/x86/vprolvd.json"},{"mnemonic":"vprolvq","slug":"vprolvq","records":1,"summary":"Rotates quadwords left by amounts in second vector.","page":"https://instructionsets.com/x86/vprolvq/","api":"https://instructionsets.com/api/v1/x86/vprolvq.json"},{"mnemonic":"vprorq","slug":"vprorq","records":1,"summary":"Rotates 64-bit integers right.","page":"https://instructionsets.com/x86/vprorq/","api":"https://instructionsets.com/api/v1/x86/vprorq.json"},{"mnemonic":"vprorvd","slug":"vprorvd","records":1,"summary":"Rotates doublewords right by amounts in second vector.","page":"https://instructionsets.com/x86/vprorvd/","api":"https://instructionsets.com/api/v1/x86/vprorvd.json"},{"mnemonic":"vprorvq","slug":"vprorvq","records":1,"summary":"Rotates quadwords right by amounts in second vector.","page":"https://instructionsets.com/x86/vprorvq/","api":"https://instructionsets.com/api/v1/x86/vprorvq.json"},{"mnemonic":"vprotb","slug":"vprotb","records":1,"summary":"Rotates bytes in XMM register.","page":"https://instructionsets.com/x86/vprotb/","api":"https://instructionsets.com/api/v1/x86/vprotb.json"},{"mnemonic":"vprotd","slug":"vprotd","records":1,"summary":"Rotates doublewords in XMM register.","page":"https://instructionsets.com/x86/vprotd/","api":"https://instructionsets.com/api/v1/x86/vprotd.json"},{"mnemonic":"vprotq","slug":"vprotq","records":1,"summary":"Rotates quadwords in XMM register.","page":"https://instructionsets.com/x86/vprotq/","api":"https://instructionsets.com/api/v1/x86/vprotq.json"},{"mnemonic":"vprotw","slug":"vprotw","records":1,"summary":"Rotates words in XMM register.","page":"https://instructionsets.com/x86/vprotw/","api":"https://instructionsets.com/api/v1/x86/vprotw.json"},{"mnemonic":"vpshab","slug":"vpshab","records":1,"summary":"Shifts bytes arithmetically.","page":"https://instructionsets.com/x86/vpshab/","api":"https://instructionsets.com/api/v1/x86/vpshab.json"},{"mnemonic":"vpshad","slug":"vpshad","records":1,"summary":"Shifts doublewords arithmetically.","page":"https://instructionsets.com/x86/vpshad/","api":"https://instructionsets.com/api/v1/x86/vpshad.json"},{"mnemonic":"vpshaq","slug":"vpshaq","records":1,"summary":"Shifts quadwords arithmetically.","page":"https://instructionsets.com/x86/vpshaq/","api":"https://instructionsets.com/api/v1/x86/vpshaq.json"},{"mnemonic":"vpshaw","slug":"vpshaw","records":1,"summary":"Shifts words arithmetically.","page":"https://instructionsets.com/x86/vpshaw/","api":"https://instructionsets.com/api/v1/x86/vpshaw.json"},{"mnemonic":"vpshldd","slug":"vpshldd","records":1,"summary":"Funnel shift left of doublewords.","page":"https://instructionsets.com/x86/vpshldd/","api":"https://instructionsets.com/api/v1/x86/vpshldd.json"},{"mnemonic":"vpshldq","slug":"vpshldq","records":1,"summary":"Funnel shift left of quadwords.","page":"https://instructionsets.com/x86/vpshldq/","api":"https://instructionsets.com/api/v1/x86/vpshldq.json"},{"mnemonic":"vpshldw","slug":"vpshldw","records":1,"summary":"Funnel shift left of words.","page":"https://instructionsets.com/x86/vpshldw/","api":"https://instructionsets.com/api/v1/x86/vpshldw.json"},{"mnemonic":"vpshrdd","slug":"vpshrdd","records":1,"summary":"Funnel shift right of doublewords.","page":"https://instructionsets.com/x86/vpshrdd/","api":"https://instructionsets.com/api/v1/x86/vpshrdd.json"},{"mnemonic":"vpshrdq","slug":"vpshrdq","records":1,"summary":"Funnel shift right of quadwords.","page":"https://instructionsets.com/x86/vpshrdq/","api":"https://instructionsets.com/api/v1/x86/vpshrdq.json"},{"mnemonic":"vpshrdw","slug":"vpshrdw","records":1,"summary":"Funnel shift right of words.","page":"https://instructionsets.com/x86/vpshrdw/","api":"https://instructionsets.com/api/v1/x86/vpshrdw.json"},{"mnemonic":"vpshufb","slug":"vpshufb","records":1,"summary":"Shuffles 32 bytes based on indices.","page":"https://instructionsets.com/x86/vpshufb/","api":"https://instructionsets.com/api/v1/x86/vpshufb.json"},{"mnemonic":"vpshufbitqmb","slug":"vpshufbitqmb","records":1,"summary":"Extracts bits from bytes and packs into a mask register.","page":"https://instructionsets.com/x86/vpshufbitqmb/","api":"https://instructionsets.com/api/v1/x86/vpshufbitqmb.json"},{"mnemonic":"vpsllvd","slug":"vpsllvd","records":1,"summary":"Shifts doublewords left by individual counts.","page":"https://instructionsets.com/x86/vpsllvd/","api":"https://instructionsets.com/api/v1/x86/vpsllvd.json"},{"mnemonic":"vpsllvq","slug":"vpsllvq","records":1,"summary":"Shifts quadwords left by individual counts.","page":"https://instructionsets.com/x86/vpsllvq/","api":"https://instructionsets.com/api/v1/x86/vpsllvq.json"},{"mnemonic":"vpsravd","slug":"vpsravd","records":1,"summary":"Shifts doublewords right arithmetic by individual counts.","page":"https://instructionsets.com/x86/vpsravd/","api":"https://instructionsets.com/api/v1/x86/vpsravd.json"},{"mnemonic":"vpsravq","slug":"vpsravq","records":1,"summary":"Shifts quadwords right arithmetic by individual counts.","page":"https://instructionsets.com/x86/vpsravq/","api":"https://instructionsets.com/api/v1/x86/vpsravq.json"},{"mnemonic":"vpsrlvd","slug":"vpsrlvd","records":1,"summary":"Shifts doublewords right logical by individual counts.","page":"https://instructionsets.com/x86/vpsrlvd/","api":"https://instructionsets.com/api/v1/x86/vpsrlvd.json"},{"mnemonic":"vpsrlvq","slug":"vpsrlvq","records":1,"summary":"Shifts quadwords right logical by individual counts.","page":"https://instructionsets.com/x86/vpsrlvq/","api":"https://instructionsets.com/api/v1/x86/vpsrlvq.json"},{"mnemonic":"vpsubd","slug":"vpsubd","records":1,"summary":"Subtracts 8 integers (256-bit).","page":"https://instructionsets.com/x86/vpsubd/","api":"https://instructionsets.com/api/v1/x86/vpsubd.json"},{"mnemonic":"vpternlogd","slug":"vpternlogd","records":1,"summary":"Performs one of 256 logical operations on 3 inputs.","page":"https://instructionsets.com/x86/vpternlogd/","api":"https://instructionsets.com/api/v1/x86/vpternlogd.json"},{"mnemonic":"vpternlogq","slug":"vpternlogq","records":1,"summary":"Performs one of 256 logical operations on 3 quadwords.","page":"https://instructionsets.com/x86/vpternlogq/","api":"https://instructionsets.com/api/v1/x86/vpternlogq.json"},{"mnemonic":"vptestmb","slug":"vptestmb","records":1,"summary":"Tests byte integers and sets k-register mask.","page":"https://instructionsets.com/x86/vptestmb/","api":"https://instructionsets.com/api/v1/x86/vptestmb.json"},{"mnemonic":"vptestmd","slug":"vptestmd","records":1,"summary":"Tests doubleword integers and sets k-register mask.","page":"https://instructionsets.com/x86/vptestmd/","api":"https://instructionsets.com/api/v1/x86/vptestmd.json"},{"mnemonic":"vptestmq","slug":"vptestmq","records":1,"summary":"Tests quadword integers and sets k-register mask.","page":"https://instructionsets.com/x86/vptestmq/","api":"https://instructionsets.com/api/v1/x86/vptestmq.json"},{"mnemonic":"vptestmw","slug":"vptestmw","records":1,"summary":"Tests word integers and sets k-register mask.","page":"https://instructionsets.com/x86/vptestmw/","api":"https://instructionsets.com/api/v1/x86/vptestmw.json"},{"mnemonic":"vrangeps","slug":"vrangeps","records":1,"summary":"Calculates range (min/max/abs) of float values.","page":"https://instructionsets.com/x86/vrangeps/","api":"https://instructionsets.com/api/v1/x86/vrangeps.json"},{"mnemonic":"vrangess","slug":"vrangess","records":1,"summary":"Calculates range (min/max/abs) of low float.","page":"https://instructionsets.com/x86/vrangess/","api":"https://instructionsets.com/api/v1/x86/vrangess.json"},{"mnemonic":"vrcp14ps","slug":"vrcp14ps","records":1,"summary":"Approximate 1/x with 2^-14 error.","page":"https://instructionsets.com/x86/vrcp14ps/","api":"https://instructionsets.com/api/v1/x86/vrcp14ps.json"},{"mnemonic":"vreduceps","slug":"vreduceps","records":1,"summary":"Performs reduction on floats (e.g. range reduction for trig).","page":"https://instructionsets.com/x86/vreduceps/","api":"https://instructionsets.com/api/v1/x86/vreduceps.json"},{"mnemonic":"vreducess","slug":"vreducess","records":1,"summary":"Performs reduction on low float.","page":"https://instructionsets.com/x86/vreducess/","api":"https://instructionsets.com/api/v1/x86/vreducess.json"},{"mnemonic":"vrndscalepd","slug":"vrndscalepd","records":1,"summary":"Rounds doubles to integer values using imm8 control.","page":"https://instructionsets.com/x86/vrndscalepd/","api":"https://instructionsets.com/api/v1/x86/vrndscalepd.json"},{"mnemonic":"vrsqrt14ps","slug":"vrsqrt14ps","records":1,"summary":"Approximate 1/sqrt(x) with 2^-14 error.","page":"https://instructionsets.com/x86/vrsqrt14ps/","api":"https://instructionsets.com/api/v1/x86/vrsqrt14ps.json"},{"mnemonic":"vscalefpd","slug":"vscalefpd","records":1,"summary":"Scales doubles by exponents (x * 2^n).","page":"https://instructionsets.com/x86/vscalefpd/","api":"https://instructionsets.com/api/v1/x86/vscalefpd.json"},{"mnemonic":"vscatterdpd","slug":"vscatterdpd","records":1,"summary":"Stores doubles to non-contiguous memory locations.","page":"https://instructionsets.com/x86/vscatterdpd/","api":"https://instructionsets.com/api/v1/x86/vscatterdpd.json"},{"mnemonic":"vscatterdps","slug":"vscatterdps","records":1,"summary":"Stores floats to non-contiguous memory locations.","page":"https://instructionsets.com/x86/vscatterdps/","api":"https://instructionsets.com/api/v1/x86/vscatterdps.json"},{"mnemonic":"vscatterpf0dpd","slug":"vscatterpf0dpd","records":1,"summary":"Prefetches lines for scatter write (L1, Double).","page":"https://instructionsets.com/x86/vscatterpf0dpd/","api":"https://instructionsets.com/api/v1/x86/vscatterpf0dpd.json"},{"mnemonic":"vscatterpf0dps","slug":"vscatterpf0dps","records":1,"summary":"Prefetches cache lines for scatter write (L1).","page":"https://instructionsets.com/x86/vscatterpf0dps/","api":"https://instructionsets.com/api/v1/x86/vscatterpf0dps.json"},{"mnemonic":"vscatterpf0qpd","slug":"vscatterpf0qpd","records":1,"summary":"Prefetches lines for scatter write (L1, Double, 64-bit idx).","page":"https://instructionsets.com/x86/vscatterpf0qpd/","api":"https://instructionsets.com/api/v1/x86/vscatterpf0qpd.json"},{"mnemonic":"vscatterpf0qps","slug":"vscatterpf0qps","records":1,"summary":"Prefetches lines for scatter write (L1, 64-bit idx).","page":"https://instructionsets.com/x86/vscatterpf0qps/","api":"https://instructionsets.com/api/v1/x86/vscatterpf0qps.json"},{"mnemonic":"vscatterqpd","slug":"vscatterqpd","records":1,"summary":"Stores doubles using 64-bit indices.","page":"https://instructionsets.com/x86/vscatterqpd/","api":"https://instructionsets.com/api/v1/x86/vscatterqpd.json"},{"mnemonic":"vscatterqps","slug":"vscatterqps","records":1,"summary":"Stores floats using 64-bit indices.","page":"https://instructionsets.com/x86/vscatterqps/","api":"https://instructionsets.com/api/v1/x86/vscatterqps.json"},{"mnemonic":"vsha512msg1","slug":"vsha512msg1","records":1,"summary":"SHA512 intermediate calculation (AVX512).","page":"https://instructionsets.com/x86/vsha512msg1/","api":"https://instructionsets.com/api/v1/x86/vsha512msg1.json"},{"mnemonic":"vsha512msg2","slug":"vsha512msg2","records":1,"summary":"SHA512 final calculation (AVX512).","page":"https://instructionsets.com/x86/vsha512msg2/","api":"https://instructionsets.com/api/v1/x86/vsha512msg2.json"},{"mnemonic":"vsha512rnds2","slug":"vsha512rnds2","records":1,"summary":"SHA512 2 rounds calculation (AVX512).","page":"https://instructionsets.com/x86/vsha512rnds2/","api":"https://instructionsets.com/api/v1/x86/vsha512rnds2.json"},{"mnemonic":"vshuff32x4","slug":"vshuff32x4","records":1,"summary":"Shuffles 128-bit blocks of single-precision floats.","page":"https://instructionsets.com/x86/vshuff32x4/","api":"https://instructionsets.com/api/v1/x86/vshuff32x4.json"},{"mnemonic":"vsm3msg1","slug":"vsm3msg1","records":1,"summary":"SM3 crypto message schedule part 1.","page":"https://instructionsets.com/x86/vsm3msg1/","api":"https://instructionsets.com/api/v1/x86/vsm3msg1.json"},{"mnemonic":"vsm3rnds2","slug":"vsm3rnds2","records":1,"summary":"SM3 crypto 2 rounds.","page":"https://instructionsets.com/x86/vsm3rnds2/","api":"https://instructionsets.com/api/v1/x86/vsm3rnds2.json"},{"mnemonic":"vsm4key4","slug":"vsm4key4","records":1,"summary":"SM4 key generation.","page":"https://instructionsets.com/x86/vsm4key4/","api":"https://instructionsets.com/api/v1/x86/vsm4key4.json"},{"mnemonic":"vsm4rnds4","slug":"vsm4rnds4","records":1,"summary":"Performs four rounds of SM4 encryption.","page":"https://instructionsets.com/x86/vsm4rnds4/","api":"https://instructionsets.com/api/v1/x86/vsm4rnds4.json"},{"mnemonic":"vsqrtph","slug":"vsqrtph","records":1,"summary":"Square root of half-precision values.","page":"https://instructionsets.com/x86/vsqrtph/","api":"https://instructionsets.com/api/v1/x86/vsqrtph.json"},{"mnemonic":"vsqrtsh","slug":"vsqrtsh","records":1,"summary":"Square root of low FP16 value.","page":"https://instructionsets.com/x86/vsqrtsh/","api":"https://instructionsets.com/api/v1/x86/vsqrtsh.json"},{"mnemonic":"vsubph","slug":"vsubph","records":1,"summary":"Subtracts half-precision floating-point values.","page":"https://instructionsets.com/x86/vsubph/","api":"https://instructionsets.com/api/v1/x86/vsubph.json"},{"mnemonic":"vsubsh","slug":"vsubsh","records":1,"summary":"Subtracts low FP16 value.","page":"https://instructionsets.com/x86/vsubsh/","api":"https://instructionsets.com/api/v1/x86/vsubsh.json"},{"mnemonic":"vtestpd","slug":"vtestpd","records":1,"summary":"Sets ZF/CF based on sign bit comparisons of doubles.","page":"https://instructionsets.com/x86/vtestpd/","api":"https://instructionsets.com/api/v1/x86/vtestpd.json"},{"mnemonic":"vtestps","slug":"vtestps","records":1,"summary":"Sets ZF/CF based on sign bit comparisons of floats.","page":"https://instructionsets.com/x86/vtestps/","api":"https://instructionsets.com/api/v1/x86/vtestps.json"},{"mnemonic":"vzeroall","slug":"vzeroall","records":1,"summary":"Clears all YMM registers.","page":"https://instructionsets.com/x86/vzeroall/","api":"https://instructionsets.com/api/v1/x86/vzeroall.json"},{"mnemonic":"vzeroupper","slug":"vzeroupper","records":1,"summary":"Clears bits 128-255 of all YMM registers (Avoids AVX-SSE transition penalty).","page":"https://instructionsets.com/x86/vzeroupper/","api":"https://instructionsets.com/api/v1/x86/vzeroupper.json"},{"mnemonic":"wait","slug":"wait","records":1,"summary":"Wait for FPU (same as FWAIT).","page":"https://instructionsets.com/x86/wait/","api":"https://instructionsets.com/api/v1/x86/wait.json"},{"mnemonic":"wbinvd","slug":"wbinvd","records":1,"summary":"Writes back modified data and invalidates caches (Privileged).","page":"https://instructionsets.com/x86/wbinvd/","api":"https://instructionsets.com/api/v1/x86/wbinvd.json"},{"mnemonic":"wbnoinvd","slug":"wbnoinvd","records":1,"summary":"Writes back modified lines but keeps them valid in cache.","page":"https://instructionsets.com/x86/wbnoinvd/","api":"https://instructionsets.com/api/v1/x86/wbnoinvd.json"},{"mnemonic":"wrfsbase","slug":"wrfsbase","records":1,"summary":"Writes a register to the FS base address.","page":"https://instructionsets.com/x86/wrfsbase/","api":"https://instructionsets.com/api/v1/x86/wrfsbase.json"},{"mnemonic":"wrgsbase","slug":"wrgsbase","records":1,"summary":"Writes a register to the GS base address.","page":"https://instructionsets.com/x86/wrgsbase/","api":"https://instructionsets.com/api/v1/x86/wrgsbase.json"},{"mnemonic":"wrmsr","slug":"wrmsr","records":1,"summary":"Writes EDX:EAX to MSR specified by ECX (Privileged).","page":"https://instructionsets.com/x86/wrmsr/","api":"https://instructionsets.com/api/v1/x86/wrmsr.json"},{"mnemonic":"wrpkru","slug":"wrpkru","records":1,"summary":"Writes EAX/EDX to PKRU register.","page":"https://instructionsets.com/x86/wrpkru/","api":"https://instructionsets.com/api/v1/x86/wrpkru.json"},{"mnemonic":"xabort","slug":"xabort","records":1,"summary":"Forces an RTM abort.","page":"https://instructionsets.com/x86/xabort/","api":"https://instructionsets.com/api/v1/x86/xabort.json"},{"mnemonic":"xadd","slug":"xadd","records":1,"summary":"Exchanges dest and src, then loads sum into dest.","page":"https://instructionsets.com/x86/xadd/","api":"https://instructionsets.com/api/v1/x86/xadd.json"},{"mnemonic":"xbegin","slug":"xbegin","records":1,"summary":"Specifies start of Restricted Transactional Memory region.","page":"https://instructionsets.com/x86/xbegin/","api":"https://instructionsets.com/api/v1/x86/xbegin.json"},{"mnemonic":"xchg","slug":"xchg","records":1,"summary":"Exchanges content of two operands.","page":"https://instructionsets.com/x86/xchg/","api":"https://instructionsets.com/api/v1/x86/xchg.json"},{"mnemonic":"xend","slug":"xend","records":1,"summary":"Specifies end of RTM region.","page":"https://instructionsets.com/x86/xend/","api":"https://instructionsets.com/api/v1/x86/xend.json"},{"mnemonic":"xgetbv","slug":"xgetbv","records":1,"summary":"Reads the state of XCR0 (feature mask) into EDX:EAX.","page":"https://instructionsets.com/x86/xgetbv/","api":"https://instructionsets.com/api/v1/x86/xgetbv.json"},{"mnemonic":"xlat","slug":"xlat","records":1,"summary":"Replaces AL with byte from table at [EBX+AL].","page":"https://instructionsets.com/x86/xlat/","api":"https://instructionsets.com/api/v1/x86/xlat.json"},{"mnemonic":"xor","slug":"xor","records":1,"summary":"Performs bitwise XOR.","page":"https://instructionsets.com/x86/xor/","api":"https://instructionsets.com/api/v1/x86/xor.json"},{"mnemonic":"xorps","slug":"xorps","records":1,"summary":"Bitwise XOR of 128 bits (Used to clear registers).","page":"https://instructionsets.com/x86/xorps/","api":"https://instructionsets.com/api/v1/x86/xorps.json"},{"mnemonic":"xrstor","slug":"xrstor","records":1,"summary":"Restores specified state components from memory.","page":"https://instructionsets.com/x86/xrstor/","api":"https://instructionsets.com/api/v1/x86/xrstor.json"},{"mnemonic":"xrstors","slug":"xrstors","records":1,"summary":"Restores supervisor state components from memory (Compact).","page":"https://instructionsets.com/x86/xrstors/","api":"https://instructionsets.com/api/v1/x86/xrstors.json"},{"mnemonic":"xsave","slug":"xsave","records":1,"summary":"Saves specified state components (AVX, SSE, etc.) to memory.","page":"https://instructionsets.com/x86/xsave/","api":"https://instructionsets.com/api/v1/x86/xsave.json"},{"mnemonic":"xsavec","slug":"xsavec","records":1,"summary":"Saves state components using compaction.","page":"https://instructionsets.com/x86/xsavec/","api":"https://instructionsets.com/api/v1/x86/xsavec.json"},{"mnemonic":"xsaveopt","slug":"xsaveopt","records":1,"summary":"Saves state components (optimized for Modified state).","page":"https://instructionsets.com/x86/xsaveopt/","api":"https://instructionsets.com/api/v1/x86/xsaveopt.json"},{"mnemonic":"xsaves","slug":"xsaves","records":1,"summary":"Saves supervisor state components to memory (Compact).","page":"https://instructionsets.com/x86/xsaves/","api":"https://instructionsets.com/api/v1/x86/xsaves.json"},{"mnemonic":"xsetbv","slug":"xsetbv","records":1,"summary":"Writes EDX:EAX to XCR0 (Enables/disables AVX/SSE states).","page":"https://instructionsets.com/x86/xsetbv/","api":"https://instructionsets.com/api/v1/x86/xsetbv.json"},{"mnemonic":"xsusldtrk","slug":"xsusldtrk","records":1,"summary":"Suspends tracking of load addresses in a TSX suspend-tracking region (resumed with XRESLDTRK).","page":"https://instructionsets.com/x86/xsusldtrk/","api":"https://instructionsets.com/api/v1/x86/xsusldtrk.json"},{"mnemonic":"xtest","slug":"xtest","records":1,"summary":"Sets ZF if processor is in transactional region.","page":"https://instructionsets.com/x86/xtest/","api":"https://instructionsets.com/api/v1/x86/xtest.json"}]}