{"api_version":"1","snapshot":"2026-10-08","licence":"CC0-1.0","architecture":"RISC-V","records":547,"mnemonics":[{"mnemonic":"ADD","slug":"add","records":1,"summary":"Adds the contents of two registers.","page":"https://instructionsets.com/risc-v/add/","api":"https://instructionsets.com/api/v1/risc-v/add.json"},{"mnemonic":"ADD.UW","slug":"add_uw","records":1,"summary":"Zero-extends the lower 32 bits of rs1 and adds it to rs2. Useful for 64-bit address calculations with 32-bit unsigned indices.","page":"https://instructionsets.com/risc-v/add_uw/","api":"https://instructionsets.com/api/v1/risc-v/add_uw.json"},{"mnemonic":"ADDI","slug":"addi","records":1,"summary":"Adds a register and a sign-extended 12-bit immediate value.","page":"https://instructionsets.com/risc-v/addi/","api":"https://instructionsets.com/api/v1/risc-v/addi.json"},{"mnemonic":"ADDIW","slug":"addiw","records":1,"summary":"Adds a 12-bit immediate to a register (32-bit arithmetic) and sign-extends to 64 bits.","page":"https://instructionsets.com/risc-v/addiw/","api":"https://instructionsets.com/api/v1/risc-v/addiw.json"},{"mnemonic":"ADDW","slug":"addw","records":1,"summary":"Adds two 32-bit registers and sign-extends the result to 64 bits.","page":"https://instructionsets.com/risc-v/addw/","api":"https://instructionsets.com/api/v1/risc-v/addw.json"},{"mnemonic":"AES64DS","slug":"aes64ds","records":1,"summary":"Performs one round of AES-128 decryption key schedule generation.","page":"https://instructionsets.com/risc-v/aes64ds/","api":"https://instructionsets.com/api/v1/risc-v/aes64ds.json"},{"mnemonic":"AES64ES","slug":"aes64es","records":1,"summary":"Performs one round of AES-128 encryption key schedule generation.","page":"https://instructionsets.com/risc-v/aes64es/","api":"https://instructionsets.com/api/v1/risc-v/aes64es.json"},{"mnemonic":"AES64IM","slug":"aes64im","records":1,"summary":"Performs the Inverse MixColumns transformation for AES decryption (RV64).","page":"https://instructionsets.com/risc-v/aes64im/","api":"https://instructionsets.com/api/v1/risc-v/aes64im.json"},{"mnemonic":"AES64KS1I","slug":"aes64ks1i","records":1,"summary":"Performs the first part of the AES-128/192/256 key schedule generation (RV64).","page":"https://instructionsets.com/risc-v/aes64ks1i/","api":"https://instructionsets.com/api/v1/risc-v/aes64ks1i.json"},{"mnemonic":"AES64KS2","slug":"aes64ks2","records":1,"summary":"Performs the second part of the AES-192/256 key schedule generation (RV64).","page":"https://instructionsets.com/risc-v/aes64ks2/","api":"https://instructionsets.com/api/v1/risc-v/aes64ks2.json"},{"mnemonic":"AMOADD.D","slug":"amoadd_d","records":1,"summary":"Atomically adds a value to a 64-bit doubleword in memory.","page":"https://instructionsets.com/risc-v/amoadd_d/","api":"https://instructionsets.com/api/v1/risc-v/amoadd_d.json"},{"mnemonic":"AMOADD.W","slug":"amoadd_w","records":1,"summary":"Atomically adds a value to a word in memory.","page":"https://instructionsets.com/risc-v/amoadd_w/","api":"https://instructionsets.com/api/v1/risc-v/amoadd_w.json"},{"mnemonic":"AMOAND.D","slug":"amoand_d","records":1,"summary":"Atomically performs bitwise AND on a 64-bit doubleword in memory.","page":"https://instructionsets.com/risc-v/amoand_d/","api":"https://instructionsets.com/api/v1/risc-v/amoand_d.json"},{"mnemonic":"AMOAND.W","slug":"amoand_w","records":1,"summary":"Atomically performs bitwise AND on a word in memory.","page":"https://instructionsets.com/risc-v/amoand_w/","api":"https://instructionsets.com/api/v1/risc-v/amoand_w.json"},{"mnemonic":"AMOCAS.D","slug":"amocas_d","records":1,"summary":"Atomically compares 64-bit memory at rs1 with rd; if equal, writes rs2 to memory.","page":"https://instructionsets.com/risc-v/amocas_d/","api":"https://instructionsets.com/api/v1/risc-v/amocas_d.json"},{"mnemonic":"AMOCAS.W","slug":"amocas_w","records":1,"summary":"Atomically compares memory at rs1 with rd; if equal, writes rs2 to memory. Returns original value in rd.","page":"https://instructionsets.com/risc-v/amocas_w/","api":"https://instructionsets.com/api/v1/risc-v/amocas_w.json"},{"mnemonic":"AMOMAX.D","slug":"amomax_d","records":1,"summary":"Atomically updates memory with the maximum of the memory value and register value (64-bit Signed).","page":"https://instructionsets.com/risc-v/amomax_d/","api":"https://instructionsets.com/api/v1/risc-v/amomax_d.json"},{"mnemonic":"AMOMAX.W","slug":"amomax_w","records":1,"summary":"Atomically updates memory with the maximum of the memory value and register value (Signed).","page":"https://instructionsets.com/risc-v/amomax_w/","api":"https://instructionsets.com/api/v1/risc-v/amomax_w.json"},{"mnemonic":"AMOMAXU.D","slug":"amomaxu_d","records":1,"summary":"Atomically updates memory with the maximum of the memory value and register value (Unsigned 64-bit).","page":"https://instructionsets.com/risc-v/amomaxu_d/","api":"https://instructionsets.com/api/v1/risc-v/amomaxu_d.json"},{"mnemonic":"AMOMAXU.W","slug":"amomaxu_w","records":1,"summary":"Atomically updates memory with the maximum of the memory value and register value (Unsigned).","page":"https://instructionsets.com/risc-v/amomaxu_w/","api":"https://instructionsets.com/api/v1/risc-v/amomaxu_w.json"},{"mnemonic":"AMOMIN.D","slug":"amomin_d","records":1,"summary":"Atomically updates memory with the minimum of the memory value and register value (64-bit Signed).","page":"https://instructionsets.com/risc-v/amomin_d/","api":"https://instructionsets.com/api/v1/risc-v/amomin_d.json"},{"mnemonic":"AMOMIN.W","slug":"amomin_w","records":1,"summary":"Atomically updates memory with the minimum of the memory value and register value (Signed).","page":"https://instructionsets.com/risc-v/amomin_w/","api":"https://instructionsets.com/api/v1/risc-v/amomin_w.json"},{"mnemonic":"AMOMINU.D","slug":"amominu_d","records":1,"summary":"Atomically updates memory with the minimum of the memory value and register value (Unsigned 64-bit).","page":"https://instructionsets.com/risc-v/amominu_d/","api":"https://instructionsets.com/api/v1/risc-v/amominu_d.json"},{"mnemonic":"AMOMINU.W","slug":"amominu_w","records":1,"summary":"Atomically updates memory with the minimum of the memory value and register value (Unsigned).","page":"https://instructionsets.com/risc-v/amominu_w/","api":"https://instructionsets.com/api/v1/risc-v/amominu_w.json"},{"mnemonic":"AMOOR.D","slug":"amoor_d","records":1,"summary":"Atomically performs bitwise OR on a 64-bit doubleword in memory.","page":"https://instructionsets.com/risc-v/amoor_d/","api":"https://instructionsets.com/api/v1/risc-v/amoor_d.json"},{"mnemonic":"AMOOR.W","slug":"amoor_w","records":1,"summary":"Atomically performs bitwise OR on a word in memory.","page":"https://instructionsets.com/risc-v/amoor_w/","api":"https://instructionsets.com/api/v1/risc-v/amoor_w.json"},{"mnemonic":"AMOSWAP.D","slug":"amoswap_d","records":1,"summary":"Atomically swaps a 64-bit value in memory with a register.","page":"https://instructionsets.com/risc-v/amoswap_d/","api":"https://instructionsets.com/api/v1/risc-v/amoswap_d.json"},{"mnemonic":"AMOSWAP.W","slug":"amoswap_w","records":1,"summary":"Atomically swaps a value in memory with a register.","page":"https://instructionsets.com/risc-v/amoswap_w/","api":"https://instructionsets.com/api/v1/risc-v/amoswap_w.json"},{"mnemonic":"AMOXOR.D","slug":"amoxor_d","records":1,"summary":"Atomically performs bitwise XOR on a 64-bit doubleword in memory.","page":"https://instructionsets.com/risc-v/amoxor_d/","api":"https://instructionsets.com/api/v1/risc-v/amoxor_d.json"},{"mnemonic":"AMOXOR.W","slug":"amoxor_w","records":1,"summary":"Atomically performs bitwise XOR on a word in memory.","page":"https://instructionsets.com/risc-v/amoxor_w/","api":"https://instructionsets.com/api/v1/risc-v/amoxor_w.json"},{"mnemonic":"AND","slug":"and","records":1,"summary":"Performs a bitwise logical AND operation between two registers.","page":"https://instructionsets.com/risc-v/and/","api":"https://instructionsets.com/api/v1/risc-v/and.json"},{"mnemonic":"ANDI","slug":"andi","records":1,"summary":"Performs a bitwise logical AND between a register and a sign-extended 12-bit immediate.","page":"https://instructionsets.com/risc-v/andi/","api":"https://instructionsets.com/api/v1/risc-v/andi.json"},{"mnemonic":"ANDN","slug":"andn","records":1,"summary":"Performs bitwise AND with the bitwise negation of rs2 (rs1 & ~rs2).","page":"https://instructionsets.com/risc-v/andn/","api":"https://instructionsets.com/api/v1/risc-v/andn.json"},{"mnemonic":"AUIPC","slug":"auipc","records":1,"summary":"Adds a 20-bit upper immediate to the Program Counter, used for PC-relative addressing.","page":"https://instructionsets.com/risc-v/auipc/","api":"https://instructionsets.com/api/v1/risc-v/auipc.json"},{"mnemonic":"BCLR","slug":"bclr","records":1,"summary":"Clears a single bit in rs1 at the index specified by rs2.","page":"https://instructionsets.com/risc-v/bclr/","api":"https://instructionsets.com/api/v1/risc-v/bclr.json"},{"mnemonic":"BCLRI","slug":"bclri","records":1,"summary":"Clears a single bit in rs1 at the index specified by an immediate.","page":"https://instructionsets.com/risc-v/bclri/","api":"https://instructionsets.com/api/v1/risc-v/bclri.json"},{"mnemonic":"BEQ","slug":"beq","records":1,"summary":"Take the branch if registers rs1 and rs2 are equal.","page":"https://instructionsets.com/risc-v/beq/","api":"https://instructionsets.com/api/v1/risc-v/beq.json"},{"mnemonic":"BEQZ","slug":"beqz","records":1,"summary":"Branches if the register is zero.","page":"https://instructionsets.com/risc-v/beqz/","api":"https://instructionsets.com/api/v1/risc-v/beqz.json"},{"mnemonic":"BEXT","slug":"bext","records":1,"summary":"Extracts the value of a single bit (0 or 1) at the index specified by rs2. The result is placed in the LSB of rd.","page":"https://instructionsets.com/risc-v/bext/","api":"https://instructionsets.com/api/v1/risc-v/bext.json"},{"mnemonic":"BEXTI","slug":"bexti","records":1,"summary":"Extracts the value of a single bit (0 or 1) at the index specified by an immediate.","page":"https://instructionsets.com/risc-v/bexti/","api":"https://instructionsets.com/api/v1/risc-v/bexti.json"},{"mnemonic":"BGE","slug":"bge","records":1,"summary":"Take the branch if rs1 is greater than or equal to rs2 (signed).","page":"https://instructionsets.com/risc-v/bge/","api":"https://instructionsets.com/api/v1/risc-v/bge.json"},{"mnemonic":"BGEU","slug":"bgeu","records":1,"summary":"Take the branch if rs1 is greater than or equal to rs2 (unsigned comparison).","page":"https://instructionsets.com/risc-v/bgeu/","api":"https://instructionsets.com/api/v1/risc-v/bgeu.json"},{"mnemonic":"BINV","slug":"binv","records":1,"summary":"Inverts (toggles) a single bit in rs1 at the index specified by rs2.","page":"https://instructionsets.com/risc-v/binv/","api":"https://instructionsets.com/api/v1/risc-v/binv.json"},{"mnemonic":"BINVI","slug":"binvi","records":1,"summary":"Inverts (toggles) a single bit in rs1 at the index specified by an immediate.","page":"https://instructionsets.com/risc-v/binvi/","api":"https://instructionsets.com/api/v1/risc-v/binvi.json"},{"mnemonic":"BLT","slug":"blt","records":1,"summary":"Take the branch if rs1 is less than rs2 (signed).","page":"https://instructionsets.com/risc-v/blt/","api":"https://instructionsets.com/api/v1/risc-v/blt.json"},{"mnemonic":"BLTU","slug":"bltu","records":1,"summary":"Take the branch if rs1 is less than rs2 (unsigned comparison).","page":"https://instructionsets.com/risc-v/bltu/","api":"https://instructionsets.com/api/v1/risc-v/bltu.json"},{"mnemonic":"BNE","slug":"bne","records":1,"summary":"Take the branch if registers rs1 and rs2 are not equal.","page":"https://instructionsets.com/risc-v/bne/","api":"https://instructionsets.com/api/v1/risc-v/bne.json"},{"mnemonic":"BNEZ","slug":"bnez","records":1,"summary":"Branches if the register is not zero.","page":"https://instructionsets.com/risc-v/bnez/","api":"https://instructionsets.com/api/v1/risc-v/bnez.json"},{"mnemonic":"BSET","slug":"bset","records":1,"summary":"Sets a single bit in rs1 at the index specified by rs2.","page":"https://instructionsets.com/risc-v/bset/","api":"https://instructionsets.com/api/v1/risc-v/bset.json"},{"mnemonic":"BSETI","slug":"bseti","records":1,"summary":"Sets a single bit in rs1 at the index specified by an immediate.","page":"https://instructionsets.com/risc-v/bseti/","api":"https://instructionsets.com/api/v1/risc-v/bseti.json"},{"mnemonic":"C.ADD","slug":"c_add","records":1,"summary":"Adds two registers.","page":"https://instructionsets.com/risc-v/c_add/","api":"https://instructionsets.com/api/v1/risc-v/c_add.json"},{"mnemonic":"C.ADDI","slug":"c_addi","records":1,"summary":"Adds a non-zero immediate to a register.","page":"https://instructionsets.com/risc-v/c_addi/","api":"https://instructionsets.com/api/v1/risc-v/c_addi.json"},{"mnemonic":"C.ADDI16SP","slug":"c_addi16sp","records":1,"summary":"Adds a signed non-zero immediate to the stack pointer (x2).","page":"https://instructionsets.com/risc-v/c_addi16sp/","api":"https://instructionsets.com/api/v1/risc-v/c_addi16sp.json"},{"mnemonic":"C.ADDI4SPN","slug":"c_addi4spn","records":1,"summary":"Adds a zero-extended non-zero immediate to the stack pointer (x2) and stores the result in a register.","page":"https://instructionsets.com/risc-v/c_addi4spn/","api":"https://instructionsets.com/api/v1/risc-v/c_addi4spn.json"},{"mnemonic":"C.ADDIW","slug":"c_addiw","records":1,"summary":"Adds a signed immediate to a register (32-bit result sign-extended, RV64).","page":"https://instructionsets.com/risc-v/c_addiw/","api":"https://instructionsets.com/api/v1/risc-v/c_addiw.json"},{"mnemonic":"C.ADDW","slug":"c_addw","records":1,"summary":"Adds two registers (32-bit result sign-extended, RV64).","page":"https://instructionsets.com/risc-v/c_addw/","api":"https://instructionsets.com/api/v1/risc-v/c_addw.json"},{"mnemonic":"C.AND","slug":"c_and","records":1,"summary":"Bitwise AND of two registers.","page":"https://instructionsets.com/risc-v/c_and/","api":"https://instructionsets.com/api/v1/risc-v/c_and.json"},{"mnemonic":"C.ANDI","slug":"c_andi","records":1,"summary":"Computes bitwise AND with a signed immediate.","page":"https://instructionsets.com/risc-v/c_andi/","api":"https://instructionsets.com/api/v1/risc-v/c_andi.json"},{"mnemonic":"C.BEQZ","slug":"c_beqz","records":1,"summary":"Branches if the register is zero.","page":"https://instructionsets.com/risc-v/c_beqz/","api":"https://instructionsets.com/api/v1/risc-v/c_beqz.json"},{"mnemonic":"C.BNEZ","slug":"c_bnez","records":1,"summary":"Branches if the register is not zero.","page":"https://instructionsets.com/risc-v/c_bnez/","api":"https://instructionsets.com/api/v1/risc-v/c_bnez.json"},{"mnemonic":"C.EBREAK","slug":"c_ebreak","records":1,"summary":"Triggers a debugger breakpoint.","page":"https://instructionsets.com/risc-v/c_ebreak/","api":"https://instructionsets.com/api/v1/risc-v/c_ebreak.json"},{"mnemonic":"C.FLD","slug":"c_fld","records":1,"summary":"Loads a double-precision float from memory (Compressed).","page":"https://instructionsets.com/risc-v/c_fld/","api":"https://instructionsets.com/api/v1/risc-v/c_fld.json"},{"mnemonic":"C.FLDSP","slug":"c_fldsp","records":1,"summary":"Loads a double-precision float from the stack pointer.","page":"https://instructionsets.com/risc-v/c_fldsp/","api":"https://instructionsets.com/api/v1/risc-v/c_fldsp.json"},{"mnemonic":"C.FLW","slug":"c_flw","records":1,"summary":"Loads a single-precision float from memory (Compressed).","page":"https://instructionsets.com/risc-v/c_flw/","api":"https://instructionsets.com/api/v1/risc-v/c_flw.json"},{"mnemonic":"C.FLWSP","slug":"c_flwsp","records":1,"summary":"Loads a single-precision float from the stack pointer.","page":"https://instructionsets.com/risc-v/c_flwsp/","api":"https://instructionsets.com/api/v1/risc-v/c_flwsp.json"},{"mnemonic":"C.FSD","slug":"c_fsd","records":1,"summary":"Stores a double-precision float to memory (Compressed).","page":"https://instructionsets.com/risc-v/c_fsd/","api":"https://instructionsets.com/api/v1/risc-v/c_fsd.json"},{"mnemonic":"C.FSDSP","slug":"c_fsdsp","records":1,"summary":"Stores a double-precision float to the stack pointer.","page":"https://instructionsets.com/risc-v/c_fsdsp/","api":"https://instructionsets.com/api/v1/risc-v/c_fsdsp.json"},{"mnemonic":"C.FSW","slug":"c_fsw","records":1,"summary":"Stores a single-precision float to memory (Compressed).","page":"https://instructionsets.com/risc-v/c_fsw/","api":"https://instructionsets.com/api/v1/risc-v/c_fsw.json"},{"mnemonic":"C.FSWSP","slug":"c_fswsp","records":1,"summary":"Stores a single-precision float to the stack pointer.","page":"https://instructionsets.com/risc-v/c_fswsp/","api":"https://instructionsets.com/api/v1/risc-v/c_fswsp.json"},{"mnemonic":"C.J","slug":"c_j","records":1,"summary":"Unconditional PC-relative jump.","page":"https://instructionsets.com/risc-v/c_j/","api":"https://instructionsets.com/api/v1/risc-v/c_j.json"},{"mnemonic":"C.JAL","slug":"c_jal","records":1,"summary":"Performs a PC-relative jump and stores return address in x1 (ra). RV32 only.","page":"https://instructionsets.com/risc-v/c_jal/","api":"https://instructionsets.com/api/v1/risc-v/c_jal.json"},{"mnemonic":"C.JALR","slug":"c_jalr","records":1,"summary":"Jumps to register address and links (saves PC+2 to ra).","page":"https://instructionsets.com/risc-v/c_jalr/","api":"https://instructionsets.com/api/v1/risc-v/c_jalr.json"},{"mnemonic":"C.JR","slug":"c_jr","records":1,"summary":"Unconditionally jumps to address in register.","page":"https://instructionsets.com/risc-v/c_jr/","api":"https://instructionsets.com/api/v1/risc-v/c_jr.json"},{"mnemonic":"C.LD","slug":"c_ld","records":1,"summary":"Loads a 64-bit value from memory (Compressed, RV64).","page":"https://instructionsets.com/risc-v/c_ld/","api":"https://instructionsets.com/api/v1/risc-v/c_ld.json"},{"mnemonic":"C.LDSP","slug":"c_ldsp","records":1,"summary":"Loads a 64-bit value from the stack pointer (RV64).","page":"https://instructionsets.com/risc-v/c_ldsp/","api":"https://instructionsets.com/api/v1/risc-v/c_ldsp.json"},{"mnemonic":"C.LI","slug":"c_li","records":1,"summary":"Loads a 6-bit signed immediate into a register.","page":"https://instructionsets.com/risc-v/c_li/","api":"https://instructionsets.com/api/v1/risc-v/c_li.json"},{"mnemonic":"C.LUI","slug":"c_lui","records":1,"summary":"Loads a non-zero 6-bit immediate into bits 17-12 of the destination register, clears lower 12 bits, sign-extends bit 17.","page":"https://instructionsets.com/risc-v/c_lui/","api":"https://instructionsets.com/api/v1/risc-v/c_lui.json"},{"mnemonic":"C.LW","slug":"c_lw","records":1,"summary":"Loads a 32-bit word from memory using a compressed encoding.","page":"https://instructionsets.com/risc-v/c_lw/","api":"https://instructionsets.com/api/v1/risc-v/c_lw.json"},{"mnemonic":"C.LWSP","slug":"c_lwsp","records":1,"summary":"Loads a word from the stack pointer (x2).","page":"https://instructionsets.com/risc-v/c_lwsp/","api":"https://instructionsets.com/api/v1/risc-v/c_lwsp.json"},{"mnemonic":"C.MUL","slug":"c_mul","records":1,"summary":"Performs 32-bit multiplication (rd = rd * rs2) in 16-bit encoding.","page":"https://instructionsets.com/risc-v/c_mul/","api":"https://instructionsets.com/api/v1/risc-v/c_mul.json"},{"mnemonic":"C.MV","slug":"c_mv","records":1,"summary":"Copies register rs2 to rd.","page":"https://instructionsets.com/risc-v/c_mv/","api":"https://instructionsets.com/api/v1/risc-v/c_mv.json"},{"mnemonic":"C.NOP","slug":"c_nop","records":1,"summary":"Performs no operation (Compressed encoding).","page":"https://instructionsets.com/risc-v/c_nop/","api":"https://instructionsets.com/api/v1/risc-v/c_nop.json"},{"mnemonic":"C.NOT","slug":"c_not","records":1,"summary":"Computes bitwise logical negation.","page":"https://instructionsets.com/risc-v/c_not/","api":"https://instructionsets.com/api/v1/risc-v/c_not.json"},{"mnemonic":"C.OR","slug":"c_or","records":1,"summary":"Bitwise OR of two registers.","page":"https://instructionsets.com/risc-v/c_or/","api":"https://instructionsets.com/api/v1/risc-v/c_or.json"},{"mnemonic":"C.SD","slug":"c_sd","records":1,"summary":"Stores a 64-bit value to memory (Compressed, RV64).","page":"https://instructionsets.com/risc-v/c_sd/","api":"https://instructionsets.com/api/v1/risc-v/c_sd.json"},{"mnemonic":"C.SDSP","slug":"c_sdsp","records":1,"summary":"Stores a 64-bit value to the stack pointer (RV64).","page":"https://instructionsets.com/risc-v/c_sdsp/","api":"https://instructionsets.com/api/v1/risc-v/c_sdsp.json"},{"mnemonic":"C.SEXT.B","slug":"c_sext_b","records":1,"summary":"Sign extends the lowest byte of rd' to XLEN.","page":"https://instructionsets.com/risc-v/c_sext_b/","api":"https://instructionsets.com/api/v1/risc-v/c_sext_b.json"},{"mnemonic":"C.SLLI","slug":"c_slli","records":1,"summary":"Logically shifts a register left by immediate.","page":"https://instructionsets.com/risc-v/c_slli/","api":"https://instructionsets.com/api/v1/risc-v/c_slli.json"},{"mnemonic":"C.SRAI","slug":"c_srai","records":1,"summary":"Arithmetically shifts a register right by immediate.","page":"https://instructionsets.com/risc-v/c_srai/","api":"https://instructionsets.com/api/v1/risc-v/c_srai.json"},{"mnemonic":"C.SRLI","slug":"c_srli","records":1,"summary":"Logically shifts a register right by immediate.","page":"https://instructionsets.com/risc-v/c_srli/","api":"https://instructionsets.com/api/v1/risc-v/c_srli.json"},{"mnemonic":"C.SUB","slug":"c_sub","records":1,"summary":"Subtracts two registers.","page":"https://instructionsets.com/risc-v/c_sub/","api":"https://instructionsets.com/api/v1/risc-v/c_sub.json"},{"mnemonic":"C.SUBW","slug":"c_subw","records":1,"summary":"Subtracts two registers (32-bit result sign-extended, RV64).","page":"https://instructionsets.com/risc-v/c_subw/","api":"https://instructionsets.com/api/v1/risc-v/c_subw.json"},{"mnemonic":"C.SW","slug":"c_sw","records":1,"summary":"Stores a 32-bit word to memory using a compressed encoding.","page":"https://instructionsets.com/risc-v/c_sw/","api":"https://instructionsets.com/api/v1/risc-v/c_sw.json"},{"mnemonic":"C.SWSP","slug":"c_swsp","records":1,"summary":"Stores a word to the stack pointer (x2).","page":"https://instructionsets.com/risc-v/c_swsp/","api":"https://instructionsets.com/api/v1/risc-v/c_swsp.json"},{"mnemonic":"C.XOR","slug":"c_xor","records":1,"summary":"Bitwise XOR of two registers.","page":"https://instructionsets.com/risc-v/c_xor/","api":"https://instructionsets.com/api/v1/risc-v/c_xor.json"},{"mnemonic":"C.ZEXT.B","slug":"c_zext_b","records":1,"summary":"Zero extends the lowest byte of rd' to XLEN.","page":"https://instructionsets.com/risc-v/c_zext_b/","api":"https://instructionsets.com/api/v1/risc-v/c_zext_b.json"},{"mnemonic":"CALL","slug":"call","records":1,"summary":"Calls a function by jumping to an address and saving the return address.","page":"https://instructionsets.com/risc-v/call/","api":"https://instructionsets.com/api/v1/risc-v/call.json"},{"mnemonic":"CBO.CLEAN","slug":"cbo_clean","records":1,"summary":"Performs a clean operation on the cache block containing the effective address.","page":"https://instructionsets.com/risc-v/cbo_clean/","api":"https://instructionsets.com/api/v1/risc-v/cbo_clean.json"},{"mnemonic":"CBO.FLUSH","slug":"cbo_flush","records":1,"summary":"Performs a flush (clean + invalidate) operation on the cache block.","page":"https://instructionsets.com/risc-v/cbo_flush/","api":"https://instructionsets.com/api/v1/risc-v/cbo_flush.json"},{"mnemonic":"CBO.INVAL","slug":"cbo_inval","records":1,"summary":"Performs an invalidate operation on the cache block.","page":"https://instructionsets.com/risc-v/cbo_inval/","api":"https://instructionsets.com/api/v1/risc-v/cbo_inval.json"},{"mnemonic":"CBO.ZERO","slug":"cbo_zero","records":1,"summary":"Zeros a cache block corresponding to the address in rs1.","page":"https://instructionsets.com/risc-v/cbo_zero/","api":"https://instructionsets.com/api/v1/risc-v/cbo_zero.json"},{"mnemonic":"CLMUL","slug":"clmul","records":1,"summary":"Performs carry-less multiplication of the lower bits of rs1 and rs2. Used for CRC and GCM (crypto).","page":"https://instructionsets.com/risc-v/clmul/","api":"https://instructionsets.com/api/v1/risc-v/clmul.json"},{"mnemonic":"CLZ","slug":"clz","records":1,"summary":"Counts the number of 0 bits at the MSB end of the register.","page":"https://instructionsets.com/risc-v/clz/","api":"https://instructionsets.com/api/v1/risc-v/clz.json"},{"mnemonic":"CM.POP","slug":"cm_pop","records":1,"summary":"Pops multiple registers from the stack and restores sp.","page":"https://instructionsets.com/risc-v/cm_pop/","api":"https://instructionsets.com/api/v1/risc-v/cm_pop.json"},{"mnemonic":"CM.PUSH","slug":"cm_push","records":1,"summary":"Pushes multiple registers (ra, s0-s11) to the stack and adjusts sp. Critical for small code size.","page":"https://instructionsets.com/risc-v/cm_push/","api":"https://instructionsets.com/api/v1/risc-v/cm_push.json"},{"mnemonic":"CPOP","slug":"cpop","records":1,"summary":"Counts the number of set bits (1s) in the register.","page":"https://instructionsets.com/risc-v/cpop/","api":"https://instructionsets.com/api/v1/risc-v/cpop.json"},{"mnemonic":"CSRC","slug":"csrc","records":1,"summary":"Clears bits in a CSR (bitwise AND NOT).","page":"https://instructionsets.com/risc-v/csrc/","api":"https://instructionsets.com/api/v1/risc-v/csrc.json"},{"mnemonic":"CSRR","slug":"csrr","records":1,"summary":"Reads the value of a CSR into a register.","page":"https://instructionsets.com/risc-v/csrr/","api":"https://instructionsets.com/api/v1/risc-v/csrr.json"},{"mnemonic":"CSRRC","slug":"csrrc","records":1,"summary":"Reads the old value of the CSR, then clears bits in the CSR based on the mask in rs1.","page":"https://instructionsets.com/risc-v/csrrc/","api":"https://instructionsets.com/api/v1/risc-v/csrrc.json"},{"mnemonic":"CSRRCI","slug":"csrrci","records":1,"summary":"Clears bits in a CSR using a 5-bit unsigned immediate.","page":"https://instructionsets.com/risc-v/csrrci/","api":"https://instructionsets.com/api/v1/risc-v/csrrci.json"},{"mnemonic":"CSRRS","slug":"csrrs","records":1,"summary":"Reads the value of the CSR into rd, then bitwise ORs the value in rs1 into the CSR (setting bits).","page":"https://instructionsets.com/risc-v/csrrs/","api":"https://instructionsets.com/api/v1/risc-v/csrrs.json"},{"mnemonic":"CSRRSI","slug":"csrrsi","records":1,"summary":"Sets bits in a CSR using a 5-bit unsigned immediate.","page":"https://instructionsets.com/risc-v/csrrsi/","api":"https://instructionsets.com/api/v1/risc-v/csrrsi.json"},{"mnemonic":"CSRRW","slug":"csrrw","records":1,"summary":"Atomically swaps values in the CSRs. Reads the old value of the CSR into rd, then writes rs1 to the CSR.","page":"https://instructionsets.com/risc-v/csrrw/","api":"https://instructionsets.com/api/v1/risc-v/csrrw.json"},{"mnemonic":"CSRRWI","slug":"csrrwi","records":1,"summary":"Updates a CSR using a 5-bit unsigned immediate (zimm) instead of a register.","page":"https://instructionsets.com/risc-v/csrrwi/","api":"https://instructionsets.com/api/v1/risc-v/csrrwi.json"},{"mnemonic":"CSRS","slug":"csrs","records":1,"summary":"Sets bits in a CSR (bitwise OR).","page":"https://instructionsets.com/risc-v/csrs/","api":"https://instructionsets.com/api/v1/risc-v/csrs.json"},{"mnemonic":"CSRW","slug":"csrw","records":1,"summary":"Writes a register value to a CSR.","page":"https://instructionsets.com/risc-v/csrw/","api":"https://instructionsets.com/api/v1/risc-v/csrw.json"},{"mnemonic":"CTZ","slug":"ctz","records":1,"summary":"Counts the number of 0 bits at the LSB end of the register.","page":"https://instructionsets.com/risc-v/ctz/","api":"https://instructionsets.com/api/v1/risc-v/ctz.json"},{"mnemonic":"CZERO.EQZ","slug":"czero_eqz","records":1,"summary":"Moves rs1 to rd if rs2 is non-zero, otherwise sets rd to zero.","page":"https://instructionsets.com/risc-v/czero_eqz/","api":"https://instructionsets.com/api/v1/risc-v/czero_eqz.json"},{"mnemonic":"CZERO.NEZ","slug":"czero_nez","records":1,"summary":"Moves rs1 to rd if rs2 is zero, otherwise sets rd to zero.","page":"https://instructionsets.com/risc-v/czero_nez/","api":"https://instructionsets.com/api/v1/risc-v/czero_nez.json"},{"mnemonic":"DIV","slug":"div","records":1,"summary":"Performs signed integer division.","page":"https://instructionsets.com/risc-v/div/","api":"https://instructionsets.com/api/v1/risc-v/div.json"},{"mnemonic":"DIVU","slug":"divu","records":1,"summary":"Performs unsigned integer division.","page":"https://instructionsets.com/risc-v/divu/","api":"https://instructionsets.com/api/v1/risc-v/divu.json"},{"mnemonic":"DIVUW","slug":"divuw","records":1,"summary":"Performs 32-bit unsigned division of rs1 by rs2, sign-extending the result.","page":"https://instructionsets.com/risc-v/divuw/","api":"https://instructionsets.com/api/v1/risc-v/divuw.json"},{"mnemonic":"DIVW","slug":"divw","records":1,"summary":"Performs 32-bit signed division of rs1 by rs2, sign-extending the result.","page":"https://instructionsets.com/risc-v/divw/","api":"https://instructionsets.com/api/v1/risc-v/divw.json"},{"mnemonic":"DRET","slug":"dret","records":1,"summary":"Returns from Debug Mode to the mode defined in the 'dcsr' register.","page":"https://instructionsets.com/risc-v/dret/","api":"https://instructionsets.com/api/v1/risc-v/dret.json"},{"mnemonic":"EBREAK","slug":"ebreak","records":1,"summary":"Used by debuggers to cause control to be transferred back to a debugging environment.","page":"https://instructionsets.com/risc-v/ebreak/","api":"https://instructionsets.com/api/v1/risc-v/ebreak.json"},{"mnemonic":"ECALL","slug":"ecall","records":1,"summary":"Generates an environment call exception (system call).","page":"https://instructionsets.com/risc-v/ecall/","api":"https://instructionsets.com/api/v1/risc-v/ecall.json"},{"mnemonic":"FADD.D","slug":"fadd_d","records":1,"summary":"Performs double-precision floating-point addition.","page":"https://instructionsets.com/risc-v/fadd_d/","api":"https://instructionsets.com/api/v1/risc-v/fadd_d.json"},{"mnemonic":"FADD.H","slug":"fadd_h","records":1,"summary":"Performs 16-bit floating-point addition.","page":"https://instructionsets.com/risc-v/fadd_h/","api":"https://instructionsets.com/api/v1/risc-v/fadd_h.json"},{"mnemonic":"FADD.S","slug":"fadd_s","records":1,"summary":"Performs single-precision floating-point addition.","page":"https://instructionsets.com/risc-v/fadd_s/","api":"https://instructionsets.com/api/v1/risc-v/fadd_s.json"},{"mnemonic":"FCLASS.D","slug":"fclass_d","records":1,"summary":"Examines a double-precision register and generates a classification bitmask.","page":"https://instructionsets.com/risc-v/fclass_d/","api":"https://instructionsets.com/api/v1/risc-v/fclass_d.json"},{"mnemonic":"FCLASS.H","slug":"fclass_h","records":1,"summary":"Examines a 16-bit floating-point number and generates a classification bitmask.","page":"https://instructionsets.com/risc-v/fclass_h/","api":"https://instructionsets.com/api/v1/risc-v/fclass_h.json"},{"mnemonic":"FCLASS.S","slug":"fclass_s","records":1,"summary":"Examines the value in a float register and generates a 10-bit bitmask indicating its class (NaN, Inf, Zero, Normal, etc.).","page":"https://instructionsets.com/risc-v/fclass_s/","api":"https://instructionsets.com/api/v1/risc-v/fclass_s.json"},{"mnemonic":"FCVT.D.L","slug":"fcvt_d_l","records":1,"summary":"Converts a 64-bit signed integer to a double-precision float.","page":"https://instructionsets.com/risc-v/fcvt_d_l/","api":"https://instructionsets.com/api/v1/risc-v/fcvt_d_l.json"},{"mnemonic":"FCVT.D.LU","slug":"fcvt_d_lu","records":1,"summary":"Converts a 64-bit unsigned integer to a double-precision float.","page":"https://instructionsets.com/risc-v/fcvt_d_lu/","api":"https://instructionsets.com/api/v1/risc-v/fcvt_d_lu.json"},{"mnemonic":"FCVT.D.S","slug":"fcvt_d_s","records":1,"summary":"Converts a single-precision float to a double-precision float.","page":"https://instructionsets.com/risc-v/fcvt_d_s/","api":"https://instructionsets.com/api/v1/risc-v/fcvt_d_s.json"},{"mnemonic":"FCVT.D.W","slug":"fcvt_d_w","records":1,"summary":"Converts a 32-bit signed integer to a double-precision float.","page":"https://instructionsets.com/risc-v/fcvt_d_w/","api":"https://instructionsets.com/api/v1/risc-v/fcvt_d_w.json"},{"mnemonic":"FCVT.D.WU","slug":"fcvt_d_wu","records":1,"summary":"Converts a 32-bit unsigned integer to a double-precision float.","page":"https://instructionsets.com/risc-v/fcvt_d_wu/","api":"https://instructionsets.com/api/v1/risc-v/fcvt_d_wu.json"},{"mnemonic":"FCVT.H.S","slug":"fcvt_h_s","records":1,"summary":"Converts a 32-bit single-precision float to a 16-bit half-precision float.","page":"https://instructionsets.com/risc-v/fcvt_h_s/","api":"https://instructionsets.com/api/v1/risc-v/fcvt_h_s.json"},{"mnemonic":"FCVT.H.W","slug":"fcvt_h_w","records":1,"summary":"Converts a 32-bit signed integer to a 16-bit floating-point number.","page":"https://instructionsets.com/risc-v/fcvt_h_w/","api":"https://instructionsets.com/api/v1/risc-v/fcvt_h_w.json"},{"mnemonic":"FCVT.H.WU","slug":"fcvt_h_wu","records":1,"summary":"Converts a 32-bit unsigned integer to a 16-bit floating-point number.","page":"https://instructionsets.com/risc-v/fcvt_h_wu/","api":"https://instructionsets.com/api/v1/risc-v/fcvt_h_wu.json"},{"mnemonic":"FCVT.L.D","slug":"fcvt_l_d","records":1,"summary":"Converts a double-precision float to a 64-bit signed integer.","page":"https://instructionsets.com/risc-v/fcvt_l_d/","api":"https://instructionsets.com/api/v1/risc-v/fcvt_l_d.json"},{"mnemonic":"FCVT.L.S","slug":"fcvt_l_s","records":1,"summary":"Converts a single-precision float to a 64-bit signed integer.","page":"https://instructionsets.com/risc-v/fcvt_l_s/","api":"https://instructionsets.com/api/v1/risc-v/fcvt_l_s.json"},{"mnemonic":"FCVT.LU.D","slug":"fcvt_lu_d","records":1,"summary":"Converts a double-precision float to a 64-bit unsigned integer.","page":"https://instructionsets.com/risc-v/fcvt_lu_d/","api":"https://instructionsets.com/api/v1/risc-v/fcvt_lu_d.json"},{"mnemonic":"FCVT.LU.S","slug":"fcvt_lu_s","records":1,"summary":"Converts a single-precision float to a 64-bit unsigned integer.","page":"https://instructionsets.com/risc-v/fcvt_lu_s/","api":"https://instructionsets.com/api/v1/risc-v/fcvt_lu_s.json"},{"mnemonic":"FCVT.S.D","slug":"fcvt_s_d","records":1,"summary":"Converts a double-precision float to a single-precision float.","page":"https://instructionsets.com/risc-v/fcvt_s_d/","api":"https://instructionsets.com/api/v1/risc-v/fcvt_s_d.json"},{"mnemonic":"FCVT.S.H","slug":"fcvt_s_h","records":1,"summary":"Converts a 16-bit half-precision float to a 32-bit single-precision float.","page":"https://instructionsets.com/risc-v/fcvt_s_h/","api":"https://instructionsets.com/api/v1/risc-v/fcvt_s_h.json"},{"mnemonic":"FCVT.S.L","slug":"fcvt_s_l","records":1,"summary":"Converts a 64-bit signed integer (Long) to a single-precision float.","page":"https://instructionsets.com/risc-v/fcvt_s_l/","api":"https://instructionsets.com/api/v1/risc-v/fcvt_s_l.json"},{"mnemonic":"FCVT.S.LU","slug":"fcvt_s_lu","records":1,"summary":"Converts a 64-bit unsigned integer to a single-precision float.","page":"https://instructionsets.com/risc-v/fcvt_s_lu/","api":"https://instructionsets.com/api/v1/risc-v/fcvt_s_lu.json"},{"mnemonic":"FCVT.S.W","slug":"fcvt_s_w","records":1,"summary":"Converts a signed 32-bit integer to a single-precision floating-point number.","page":"https://instructionsets.com/risc-v/fcvt_s_w/","api":"https://instructionsets.com/api/v1/risc-v/fcvt_s_w.json"},{"mnemonic":"FCVT.S.WU","slug":"fcvt_s_wu","records":1,"summary":"Converts a 32-bit unsigned integer to a single-precision float.","page":"https://instructionsets.com/risc-v/fcvt_s_wu/","api":"https://instructionsets.com/api/v1/risc-v/fcvt_s_wu.json"},{"mnemonic":"FCVT.W.D","slug":"fcvt_w_d","records":1,"summary":"Converts a double-precision float to a 32-bit signed integer.","page":"https://instructionsets.com/risc-v/fcvt_w_d/","api":"https://instructionsets.com/api/v1/risc-v/fcvt_w_d.json"},{"mnemonic":"FCVT.W.H","slug":"fcvt_w_h","records":1,"summary":"Converts a 16-bit floating-point number to a 32-bit signed integer.","page":"https://instructionsets.com/risc-v/fcvt_w_h/","api":"https://instructionsets.com/api/v1/risc-v/fcvt_w_h.json"},{"mnemonic":"FCVT.W.S","slug":"fcvt_w_s","records":1,"summary":"Converts a single-precision floating-point number to a signed 32-bit integer.","page":"https://instructionsets.com/risc-v/fcvt_w_s/","api":"https://instructionsets.com/api/v1/risc-v/fcvt_w_s.json"},{"mnemonic":"FCVT.WU.D","slug":"fcvt_wu_d","records":1,"summary":"Converts a double-precision float to a 32-bit unsigned integer.","page":"https://instructionsets.com/risc-v/fcvt_wu_d/","api":"https://instructionsets.com/api/v1/risc-v/fcvt_wu_d.json"},{"mnemonic":"FCVT.WU.H","slug":"fcvt_wu_h","records":1,"summary":"Converts a 16-bit floating-point number to a 32-bit unsigned integer.","page":"https://instructionsets.com/risc-v/fcvt_wu_h/","api":"https://instructionsets.com/api/v1/risc-v/fcvt_wu_h.json"},{"mnemonic":"FCVT.WU.S","slug":"fcvt_wu_s","records":1,"summary":"Converts a single-precision float to a 32-bit unsigned integer.","page":"https://instructionsets.com/risc-v/fcvt_wu_s/","api":"https://instructionsets.com/api/v1/risc-v/fcvt_wu_s.json"},{"mnemonic":"FDIV.D","slug":"fdiv_d","records":1,"summary":"Performs double-precision floating-point division.","page":"https://instructionsets.com/risc-v/fdiv_d/","api":"https://instructionsets.com/api/v1/risc-v/fdiv_d.json"},{"mnemonic":"FDIV.H","slug":"fdiv_h","records":1,"summary":"Performs 16-bit floating-point division.","page":"https://instructionsets.com/risc-v/fdiv_h/","api":"https://instructionsets.com/api/v1/risc-v/fdiv_h.json"},{"mnemonic":"FDIV.S","slug":"fdiv_s","records":1,"summary":"Performs single-precision floating-point division.","page":"https://instructionsets.com/risc-v/fdiv_s/","api":"https://instructionsets.com/api/v1/risc-v/fdiv_s.json"},{"mnemonic":"FENCE","slug":"fence","records":1,"summary":"Orders device I/O and memory accesses.","page":"https://instructionsets.com/risc-v/fence/","api":"https://instructionsets.com/api/v1/risc-v/fence.json"},{"mnemonic":"FENCE.I","slug":"fence_i","records":1,"summary":"Synchronizes the instruction cache with the data cache (used after self-modifying code).","page":"https://instructionsets.com/risc-v/fence_i/","api":"https://instructionsets.com/api/v1/risc-v/fence_i.json"},{"mnemonic":"FEQ.D","slug":"feq_d","records":1,"summary":"Sets integer rd to 1 if double rs1 equals double rs2, else 0.","page":"https://instructionsets.com/risc-v/feq_d/","api":"https://instructionsets.com/api/v1/risc-v/feq_d.json"},{"mnemonic":"FEQ.H","slug":"feq_h","records":1,"summary":"Sets integer rd to 1 if half-precision rs1 equals rs2, else 0.","page":"https://instructionsets.com/risc-v/feq_h/","api":"https://instructionsets.com/api/v1/risc-v/feq_h.json"},{"mnemonic":"FEQ.S","slug":"feq_s","records":1,"summary":"Sets integer rd to 1 if float rs1 equals float rs2, else 0.","page":"https://instructionsets.com/risc-v/feq_s/","api":"https://instructionsets.com/api/v1/risc-v/feq_s.json"},{"mnemonic":"FLD","slug":"fld","records":1,"summary":"Loads a 64-bit double-precision floating-point value from memory.","page":"https://instructionsets.com/risc-v/fld/","api":"https://instructionsets.com/api/v1/risc-v/fld.json"},{"mnemonic":"FLE.D","slug":"fle_d","records":1,"summary":"Sets integer rd to 1 if double rs1 is less than or equal to double rs2, else 0.","page":"https://instructionsets.com/risc-v/fle_d/","api":"https://instructionsets.com/api/v1/risc-v/fle_d.json"},{"mnemonic":"FLE.H","slug":"fle_h","records":1,"summary":"Sets integer rd to 1 if half-precision rs1 is less than or equal to rs2, else 0.","page":"https://instructionsets.com/risc-v/fle_h/","api":"https://instructionsets.com/api/v1/risc-v/fle_h.json"},{"mnemonic":"FLE.S","slug":"fle_s","records":1,"summary":"Sets integer rd to 1 if float rs1 is less than or equal to float rs2, else 0.","page":"https://instructionsets.com/risc-v/fle_s/","api":"https://instructionsets.com/api/v1/risc-v/fle_s.json"},{"mnemonic":"FLH","slug":"flh","records":1,"summary":"Loads a 16-bit half-precision float from memory.","page":"https://instructionsets.com/risc-v/flh/","api":"https://instructionsets.com/api/v1/risc-v/flh.json"},{"mnemonic":"FLI.D","slug":"fli_d","records":1,"summary":"Loads a common double-precision constant into a register.","page":"https://instructionsets.com/risc-v/fli_d/","api":"https://instructionsets.com/api/v1/risc-v/fli_d.json"},{"mnemonic":"FLI.H","slug":"fli_h","records":1,"summary":"Loads a common half-precision constant into a register.","page":"https://instructionsets.com/risc-v/fli_h/","api":"https://instructionsets.com/api/v1/risc-v/fli_h.json"},{"mnemonic":"FLI.S","slug":"fli_s","records":1,"summary":"Loads a common floating-point constant (e.g., 1.0, 0.5, PI) into a register from a small table.","page":"https://instructionsets.com/risc-v/fli_s/","api":"https://instructionsets.com/api/v1/risc-v/fli_s.json"},{"mnemonic":"FLT.D","slug":"flt_d","records":1,"summary":"Sets integer rd to 1 if double rs1 is less than double rs2, else 0.","page":"https://instructionsets.com/risc-v/flt_d/","api":"https://instructionsets.com/api/v1/risc-v/flt_d.json"},{"mnemonic":"FLT.H","slug":"flt_h","records":1,"summary":"Sets integer rd to 1 if half-precision rs1 is less than rs2, else 0.","page":"https://instructionsets.com/risc-v/flt_h/","api":"https://instructionsets.com/api/v1/risc-v/flt_h.json"},{"mnemonic":"FLT.S","slug":"flt_s","records":1,"summary":"Sets integer rd to 1 if float rs1 is less than float rs2, else 0.","page":"https://instructionsets.com/risc-v/flt_s/","api":"https://instructionsets.com/api/v1/risc-v/flt_s.json"},{"mnemonic":"FLW","slug":"flw","records":1,"summary":"Loads a single-precision floating-point value from memory.","page":"https://instructionsets.com/risc-v/flw/","api":"https://instructionsets.com/api/v1/risc-v/flw.json"},{"mnemonic":"FMADD.D","slug":"fmadd_d","records":1,"summary":"Computes (rs1 * rs2) + rs3 with a single rounding (64-bit).","page":"https://instructionsets.com/risc-v/fmadd_d/","api":"https://instructionsets.com/api/v1/risc-v/fmadd_d.json"},{"mnemonic":"FMADD.H","slug":"fmadd_h","records":1,"summary":"Computes (rs1 * rs2) + rs3 with single rounding (16-bit).","page":"https://instructionsets.com/risc-v/fmadd_h/","api":"https://instructionsets.com/api/v1/risc-v/fmadd_h.json"},{"mnemonic":"FMADD.S","slug":"fmadd_s","records":1,"summary":"Computes (rs1 * rs2) + rs3 with a single rounding.","page":"https://instructionsets.com/risc-v/fmadd_s/","api":"https://instructionsets.com/api/v1/risc-v/fmadd_s.json"},{"mnemonic":"FMAX.D","slug":"fmax_d","records":1,"summary":"Writes the larger of two double-precision floating-point values to rd.","page":"https://instructionsets.com/risc-v/fmax_d/","api":"https://instructionsets.com/api/v1/risc-v/fmax_d.json"},{"mnemonic":"FMAX.H","slug":"fmax_h","records":1,"summary":"Writes the larger of two 16-bit floating-point values to rd.","page":"https://instructionsets.com/risc-v/fmax_h/","api":"https://instructionsets.com/api/v1/risc-v/fmax_h.json"},{"mnemonic":"FMAX.S","slug":"fmax_s","records":1,"summary":"Writes the larger of two single-precision floating-point values to rd.","page":"https://instructionsets.com/risc-v/fmax_s/","api":"https://instructionsets.com/api/v1/risc-v/fmax_s.json"},{"mnemonic":"FMAXM.S","slug":"fmaxm_s","records":1,"summary":"Maximum of two floats, treating +0.0 as larger than -0.0.","page":"https://instructionsets.com/risc-v/fmaxm_s/","api":"https://instructionsets.com/api/v1/risc-v/fmaxm_s.json"},{"mnemonic":"FMIN.D","slug":"fmin_d","records":1,"summary":"Writes the smaller of two double-precision floating-point values to rd.","page":"https://instructionsets.com/risc-v/fmin_d/","api":"https://instructionsets.com/api/v1/risc-v/fmin_d.json"},{"mnemonic":"FMIN.H","slug":"fmin_h","records":1,"summary":"Writes the smaller of two 16-bit floating-point values to rd.","page":"https://instructionsets.com/risc-v/fmin_h/","api":"https://instructionsets.com/api/v1/risc-v/fmin_h.json"},{"mnemonic":"FMIN.S","slug":"fmin_s","records":1,"summary":"Writes the smaller of two single-precision floating-point values to rd.","page":"https://instructionsets.com/risc-v/fmin_s/","api":"https://instructionsets.com/api/v1/risc-v/fmin_s.json"},{"mnemonic":"FMINM.S","slug":"fminm_s","records":1,"summary":"Minimum of two floats, treating -0.0 as smaller than +0.0 (canonicalize NaNs).","page":"https://instructionsets.com/risc-v/fminm_s/","api":"https://instructionsets.com/api/v1/risc-v/fminm_s.json"},{"mnemonic":"FMSUB.D","slug":"fmsub_d","records":1,"summary":"Computes (rs1 * rs2) - rs3 with a single rounding (Double).","page":"https://instructionsets.com/risc-v/fmsub_d/","api":"https://instructionsets.com/api/v1/risc-v/fmsub_d.json"},{"mnemonic":"FMSUB.H","slug":"fmsub_h","records":1,"summary":"Computes (rs1 * rs2) - rs3 with single rounding (16-bit).","page":"https://instructionsets.com/risc-v/fmsub_h/","api":"https://instructionsets.com/api/v1/risc-v/fmsub_h.json"},{"mnemonic":"FMSUB.S","slug":"fmsub_s","records":1,"summary":"Computes (rs1 * rs2) - rs3 with a single rounding.","page":"https://instructionsets.com/risc-v/fmsub_s/","api":"https://instructionsets.com/api/v1/risc-v/fmsub_s.json"},{"mnemonic":"FMUL.D","slug":"fmul_d","records":1,"summary":"Performs double-precision floating-point multiplication.","page":"https://instructionsets.com/risc-v/fmul_d/","api":"https://instructionsets.com/api/v1/risc-v/fmul_d.json"},{"mnemonic":"FMUL.H","slug":"fmul_h","records":1,"summary":"Performs 16-bit floating-point multiplication.","page":"https://instructionsets.com/risc-v/fmul_h/","api":"https://instructionsets.com/api/v1/risc-v/fmul_h.json"},{"mnemonic":"FMUL.S","slug":"fmul_s","records":1,"summary":"Performs single-precision floating-point multiplication.","page":"https://instructionsets.com/risc-v/fmul_s/","api":"https://instructionsets.com/api/v1/risc-v/fmul_s.json"},{"mnemonic":"FMV.D.X","slug":"fmv_d_x","records":1,"summary":"Moves the bit pattern of a 64-bit integer register to a floating-point register (RV64).","page":"https://instructionsets.com/risc-v/fmv_d_x/","api":"https://instructionsets.com/api/v1/risc-v/fmv_d_x.json"},{"mnemonic":"FMV.W.X","slug":"fmv_w_x","records":1,"summary":"Moves the bit pattern of an integer register to a floating-point register.","page":"https://instructionsets.com/risc-v/fmv_w_x/","api":"https://instructionsets.com/api/v1/risc-v/fmv_w_x.json"},{"mnemonic":"FMV.X.D","slug":"fmv_x_d","records":1,"summary":"Moves the bit pattern of a 64-bit floating-point register to an integer register (RV64).","page":"https://instructionsets.com/risc-v/fmv_x_d/","api":"https://instructionsets.com/api/v1/risc-v/fmv_x_d.json"},{"mnemonic":"FMV.X.W","slug":"fmv_x_w","records":1,"summary":"Moves the bit pattern of a floating-point register to an integer register.","page":"https://instructionsets.com/risc-v/fmv_x_w/","api":"https://instructionsets.com/api/v1/risc-v/fmv_x_w.json"},{"mnemonic":"FNMADD.D","slug":"fnmadd_d","records":1,"summary":"Computes -(rs1 * rs2) - rs3 with a single rounding (Double).","page":"https://instructionsets.com/risc-v/fnmadd_d/","api":"https://instructionsets.com/api/v1/risc-v/fnmadd_d.json"},{"mnemonic":"FNMADD.H","slug":"fnmadd_h","records":1,"summary":"Computes -(rs1 * rs2) - rs3 with single rounding (16-bit).","page":"https://instructionsets.com/risc-v/fnmadd_h/","api":"https://instructionsets.com/api/v1/risc-v/fnmadd_h.json"},{"mnemonic":"FNMADD.S","slug":"fnmadd_s","records":1,"summary":"Computes -(rs1 * rs2) - rs3 with a single rounding.","page":"https://instructionsets.com/risc-v/fnmadd_s/","api":"https://instructionsets.com/api/v1/risc-v/fnmadd_s.json"},{"mnemonic":"FNMSUB.D","slug":"fnmsub_d","records":1,"summary":"Computes -(rs1 * rs2) + rs3 with a single rounding (Double).","page":"https://instructionsets.com/risc-v/fnmsub_d/","api":"https://instructionsets.com/api/v1/risc-v/fnmsub_d.json"},{"mnemonic":"FNMSUB.H","slug":"fnmsub_h","records":1,"summary":"Computes -(rs1 * rs2) + rs3 with single rounding (16-bit).","page":"https://instructionsets.com/risc-v/fnmsub_h/","api":"https://instructionsets.com/api/v1/risc-v/fnmsub_h.json"},{"mnemonic":"FNMSUB.S","slug":"fnmsub_s","records":1,"summary":"Computes -(rs1 * rs2) + rs3 with a single rounding.","page":"https://instructionsets.com/risc-v/fnmsub_s/","api":"https://instructionsets.com/api/v1/risc-v/fnmsub_s.json"},{"mnemonic":"FROUND.S","slug":"fround_s","records":1,"summary":"Rounds a float to the nearest integer value (returned as a float).","page":"https://instructionsets.com/risc-v/fround_s/","api":"https://instructionsets.com/api/v1/risc-v/fround_s.json"},{"mnemonic":"FSD","slug":"fsd","records":1,"summary":"Stores a 64-bit double-precision floating-point value to memory.","page":"https://instructionsets.com/risc-v/fsd/","api":"https://instructionsets.com/api/v1/risc-v/fsd.json"},{"mnemonic":"FSGNJ.D","slug":"fsgnj_d","records":1,"summary":"Injects the sign of rs2 into rs1 (Double Precision).","page":"https://instructionsets.com/risc-v/fsgnj_d/","api":"https://instructionsets.com/api/v1/risc-v/fsgnj_d.json"},{"mnemonic":"FSGNJ.H","slug":"fsgnj_h","records":1,"summary":"Injects the sign of rs2 into rs1 (16-bit).","page":"https://instructionsets.com/risc-v/fsgnj_h/","api":"https://instructionsets.com/api/v1/risc-v/fsgnj_h.json"},{"mnemonic":"FSGNJ.S","slug":"fsgnj_s","records":1,"summary":"Injects the sign of rs2 into rs1. Used to copy values or manipulate signs.","page":"https://instructionsets.com/risc-v/fsgnj_s/","api":"https://instructionsets.com/api/v1/risc-v/fsgnj_s.json"},{"mnemonic":"FSGNJN.D","slug":"fsgnjn_d","records":1,"summary":"Injects the *negated* sign of rs2 into rs1 (Double Precision).","page":"https://instructionsets.com/risc-v/fsgnjn_d/","api":"https://instructionsets.com/api/v1/risc-v/fsgnjn_d.json"},{"mnemonic":"FSGNJN.H","slug":"fsgnjn_h","records":1,"summary":"Injects the negated sign of rs2 into rs1 (16-bit).","page":"https://instructionsets.com/risc-v/fsgnjn_h/","api":"https://instructionsets.com/api/v1/risc-v/fsgnjn_h.json"},{"mnemonic":"FSGNJN.S","slug":"fsgnjn_s","records":1,"summary":"Injects the *negated* sign of rs2 into rs1. Used for negation and absolute value.","page":"https://instructionsets.com/risc-v/fsgnjn_s/","api":"https://instructionsets.com/api/v1/risc-v/fsgnjn_s.json"},{"mnemonic":"FSGNJX.D","slug":"fsgnjx_d","records":1,"summary":"Injects the XOR of signs of rs1 and rs2 (Double Precision).","page":"https://instructionsets.com/risc-v/fsgnjx_d/","api":"https://instructionsets.com/api/v1/risc-v/fsgnjx_d.json"},{"mnemonic":"FSGNJX.H","slug":"fsgnjx_h","records":1,"summary":"Injects the XOR of signs of rs1 and rs2 (16-bit).","page":"https://instructionsets.com/risc-v/fsgnjx_h/","api":"https://instructionsets.com/api/v1/risc-v/fsgnjx_h.json"},{"mnemonic":"FSGNJX.S","slug":"fsgnjx_s","records":1,"summary":"Injects the XOR of signs of rs1 and rs2. Used to copy sign.","page":"https://instructionsets.com/risc-v/fsgnjx_s/","api":"https://instructionsets.com/api/v1/risc-v/fsgnjx_s.json"},{"mnemonic":"FSH","slug":"fsh","records":1,"summary":"Stores a 16-bit half-precision float to memory.","page":"https://instructionsets.com/risc-v/fsh/","api":"https://instructionsets.com/api/v1/risc-v/fsh.json"},{"mnemonic":"FSQRT.D","slug":"fsqrt_d","records":1,"summary":"Computes the square root of a double-precision floating-point number.","page":"https://instructionsets.com/risc-v/fsqrt_d/","api":"https://instructionsets.com/api/v1/risc-v/fsqrt_d.json"},{"mnemonic":"FSQRT.H","slug":"fsqrt_h","records":1,"summary":"Computes the square root of a 16-bit floating-point number.","page":"https://instructionsets.com/risc-v/fsqrt_h/","api":"https://instructionsets.com/api/v1/risc-v/fsqrt_h.json"},{"mnemonic":"FSQRT.S","slug":"fsqrt_s","records":1,"summary":"Computes the square root of a single-precision floating-point number.","page":"https://instructionsets.com/risc-v/fsqrt_s/","api":"https://instructionsets.com/api/v1/risc-v/fsqrt_s.json"},{"mnemonic":"FSUB.D","slug":"fsub_d","records":1,"summary":"Performs double-precision floating-point subtraction.","page":"https://instructionsets.com/risc-v/fsub_d/","api":"https://instructionsets.com/api/v1/risc-v/fsub_d.json"},{"mnemonic":"FSUB.H","slug":"fsub_h","records":1,"summary":"Performs 16-bit floating-point subtraction.","page":"https://instructionsets.com/risc-v/fsub_h/","api":"https://instructionsets.com/api/v1/risc-v/fsub_h.json"},{"mnemonic":"FSUB.S","slug":"fsub_s","records":1,"summary":"Performs single-precision floating-point subtraction.","page":"https://instructionsets.com/risc-v/fsub_s/","api":"https://instructionsets.com/api/v1/risc-v/fsub_s.json"},{"mnemonic":"FSW","slug":"fsw","records":1,"summary":"Stores a single-precision floating-point value to memory.","page":"https://instructionsets.com/risc-v/fsw/","api":"https://instructionsets.com/api/v1/risc-v/fsw.json"},{"mnemonic":"HFENCE.GVMA","slug":"hfence_gvma","records":1,"summary":"Synchronizes updates to guest physical address translation data structures.","page":"https://instructionsets.com/risc-v/hfence_gvma/","api":"https://instructionsets.com/api/v1/risc-v/hfence_gvma.json"},{"mnemonic":"HFENCE.VVMA","slug":"hfence_vvma","records":1,"summary":"Synchronizes updates to VS-stage address translation data structures.","page":"https://instructionsets.com/risc-v/hfence_vvma/","api":"https://instructionsets.com/api/v1/risc-v/hfence_vvma.json"},{"mnemonic":"HLV.B","slug":"hlv_b","records":1,"summary":"Loads a byte from Guest Physical Memory (VS-stage translation only).","page":"https://instructionsets.com/risc-v/hlv_b/","api":"https://instructionsets.com/api/v1/risc-v/hlv_b.json"},{"mnemonic":"HLV.D","slug":"hlv_d","records":1,"summary":"Loads a doubleword from guest physical memory.","page":"https://instructionsets.com/risc-v/hlv_d/","api":"https://instructionsets.com/api/v1/risc-v/hlv_d.json"},{"mnemonic":"HLV.W","slug":"hlv_w","records":1,"summary":"Loads a word from Guest Physical Memory (VS-stage translation only).","page":"https://instructionsets.com/risc-v/hlv_w/","api":"https://instructionsets.com/api/v1/risc-v/hlv_w.json"},{"mnemonic":"HLV.WU","slug":"hlv_wu","records":1,"summary":"Loads a word from guest physical memory (unsigned).","page":"https://instructionsets.com/risc-v/hlv_wu/","api":"https://instructionsets.com/api/v1/risc-v/hlv_wu.json"},{"mnemonic":"HSV.B","slug":"hsv_b","records":1,"summary":"Stores a byte to Guest Physical Memory.","page":"https://instructionsets.com/risc-v/hsv_b/","api":"https://instructionsets.com/api/v1/risc-v/hsv_b.json"},{"mnemonic":"HSV.D","slug":"hsv_d","records":1,"summary":"Stores a doubleword to guest physical memory.","page":"https://instructionsets.com/risc-v/hsv_d/","api":"https://instructionsets.com/api/v1/risc-v/hsv_d.json"},{"mnemonic":"HSV.W","slug":"hsv_w","records":1,"summary":"Stores a word to Guest Physical Memory.","page":"https://instructionsets.com/risc-v/hsv_w/","api":"https://instructionsets.com/api/v1/risc-v/hsv_w.json"},{"mnemonic":"J","slug":"j","records":1,"summary":"Unconditionally jumps to a target offset.","page":"https://instructionsets.com/risc-v/j/","api":"https://instructionsets.com/api/v1/risc-v/j.json"},{"mnemonic":"JAL","slug":"jal","records":1,"summary":"Jumps to an offset relative to PC and saves the return address (PC+4) to rd.","page":"https://instructionsets.com/risc-v/jal/","api":"https://instructionsets.com/api/v1/risc-v/jal.json"},{"mnemonic":"JALR","slug":"jalr","records":1,"summary":"Jumps to address in rs1 + offset, saving return address to rd.","page":"https://instructionsets.com/risc-v/jalr/","api":"https://instructionsets.com/api/v1/risc-v/jalr.json"},{"mnemonic":"JR","slug":"jr","records":1,"summary":"Unconditionally jumps to an address held in a register.","page":"https://instructionsets.com/risc-v/jr/","api":"https://instructionsets.com/api/v1/risc-v/jr.json"},{"mnemonic":"LB","slug":"lb","records":1,"summary":"Loads an 8-bit byte from memory and sign-extends it to the register width.","page":"https://instructionsets.com/risc-v/lb/","api":"https://instructionsets.com/api/v1/risc-v/lb.json"},{"mnemonic":"LBU","slug":"lbu","records":1,"summary":"Loads an 8-bit byte from memory and zero-extends it.","page":"https://instructionsets.com/risc-v/lbu/","api":"https://instructionsets.com/api/v1/risc-v/lbu.json"},{"mnemonic":"LD","slug":"ld","records":1,"summary":"Loads a 64-bit doubleword from memory.","page":"https://instructionsets.com/risc-v/ld/","api":"https://instructionsets.com/api/v1/risc-v/ld.json"},{"mnemonic":"LH","slug":"lh","records":1,"summary":"Loads a 16-bit halfword from memory and sign-extends it.","page":"https://instructionsets.com/risc-v/lh/","api":"https://instructionsets.com/api/v1/risc-v/lh.json"},{"mnemonic":"LHU","slug":"lhu","records":1,"summary":"Loads a 16-bit halfword from memory and zero-extends it.","page":"https://instructionsets.com/risc-v/lhu/","api":"https://instructionsets.com/api/v1/risc-v/lhu.json"},{"mnemonic":"LI","slug":"li","records":1,"summary":"Loads an arbitrary immediate value into a register.","page":"https://instructionsets.com/risc-v/li/","api":"https://instructionsets.com/api/v1/risc-v/li.json"},{"mnemonic":"LR.D","slug":"lr_d","records":1,"summary":"Loads a doubleword from memory and registers a reservation set.","page":"https://instructionsets.com/risc-v/lr_d/","api":"https://instructionsets.com/api/v1/risc-v/lr_d.json"},{"mnemonic":"LR.W","slug":"lr_w","records":1,"summary":"Loads a word from memory and registers a reservation set for the address.","page":"https://instructionsets.com/risc-v/lr_w/","api":"https://instructionsets.com/api/v1/risc-v/lr_w.json"},{"mnemonic":"LUI","slug":"lui","records":1,"summary":"Loads the 20-bit immediate into the upper 20 bits of the register (lower 12 bits are zero).","page":"https://instructionsets.com/risc-v/lui/","api":"https://instructionsets.com/api/v1/risc-v/lui.json"},{"mnemonic":"LW","slug":"lw","records":1,"summary":"Loads a 32-bit word from memory and sign-extends it to 64 bits.","page":"https://instructionsets.com/risc-v/lw/","api":"https://instructionsets.com/api/v1/risc-v/lw.json"},{"mnemonic":"LWU","slug":"lwu","records":1,"summary":"Loads a 32-bit word from memory and zero-extends it to 64 bits.","page":"https://instructionsets.com/risc-v/lwu/","api":"https://instructionsets.com/api/v1/risc-v/lwu.json"},{"mnemonic":"MAX","slug":"max","records":1,"summary":"Computes the signed maximum of two registers.","page":"https://instructionsets.com/risc-v/max/","api":"https://instructionsets.com/api/v1/risc-v/max.json"},{"mnemonic":"MAXU","slug":"maxu","records":1,"summary":"Computes the maximum of two unsigned integers.","page":"https://instructionsets.com/risc-v/maxu/","api":"https://instructionsets.com/api/v1/risc-v/maxu.json"},{"mnemonic":"MIN","slug":"min","records":1,"summary":"Computes the signed minimum of two registers.","page":"https://instructionsets.com/risc-v/min/","api":"https://instructionsets.com/api/v1/risc-v/min.json"},{"mnemonic":"MINU","slug":"minu","records":1,"summary":"Computes the minimum of two unsigned integers.","page":"https://instructionsets.com/risc-v/minu/","api":"https://instructionsets.com/api/v1/risc-v/minu.json"},{"mnemonic":"MRET","slug":"mret","records":1,"summary":"Returns from a machine-mode trap handler.","page":"https://instructionsets.com/risc-v/mret/","api":"https://instructionsets.com/api/v1/risc-v/mret.json"},{"mnemonic":"MUL","slug":"mul","records":1,"summary":"Performs a 32-bit (or 64-bit) multiplication of rs1 and rs2 and stores the lower bits in rd.","page":"https://instructionsets.com/risc-v/mul/","api":"https://instructionsets.com/api/v1/risc-v/mul.json"},{"mnemonic":"MULH","slug":"mulh","records":1,"summary":"Performs a signed multiplication and stores the upper bits of the result.","page":"https://instructionsets.com/risc-v/mulh/","api":"https://instructionsets.com/api/v1/risc-v/mulh.json"},{"mnemonic":"MULHSU","slug":"mulhsu","records":1,"summary":"Multiplies signed rs1 by unsigned rs2 and returns the upper XLEN bits.","page":"https://instructionsets.com/risc-v/mulhsu/","api":"https://instructionsets.com/api/v1/risc-v/mulhsu.json"},{"mnemonic":"MULHU","slug":"mulhu","records":1,"summary":"Performs unsigned multiplication and returns the upper XLEN bits.","page":"https://instructionsets.com/risc-v/mulhu/","api":"https://instructionsets.com/api/v1/risc-v/mulhu.json"},{"mnemonic":"MULW","slug":"mulw","records":1,"summary":"Performs 32-bit multiplication of rs1 and rs2, sign-extending the 32-bit result to 64 bits.","page":"https://instructionsets.com/risc-v/mulw/","api":"https://instructionsets.com/api/v1/risc-v/mulw.json"},{"mnemonic":"MV","slug":"mv","records":1,"summary":"Copies the value of one register into another.","page":"https://instructionsets.com/risc-v/mv/","api":"https://instructionsets.com/api/v1/risc-v/mv.json"},{"mnemonic":"NEG","slug":"neg","records":1,"summary":"Computes the two's complement negation (arithmetic negative).","page":"https://instructionsets.com/risc-v/neg/","api":"https://instructionsets.com/api/v1/risc-v/neg.json"},{"mnemonic":"NOP","slug":"nop","records":1,"summary":"Performs no operation. Used for alignment or timing delays.","page":"https://instructionsets.com/risc-v/nop/","api":"https://instructionsets.com/api/v1/risc-v/nop.json"},{"mnemonic":"NOT","slug":"not","records":1,"summary":"Computes the bitwise logical negation (one's complement).","page":"https://instructionsets.com/risc-v/not/","api":"https://instructionsets.com/api/v1/risc-v/not.json"},{"mnemonic":"NTL.ALL","slug":"ntl_all","records":1,"summary":"Hint that the subsequent store should bypass all cache levels.","page":"https://instructionsets.com/risc-v/ntl_all/","api":"https://instructionsets.com/api/v1/risc-v/ntl_all.json"},{"mnemonic":"NTL.P1","slug":"ntl_p1","records":1,"summary":"Hint that the target cache block will be needed, but is likely to be discarded after use (Stream data).","page":"https://instructionsets.com/risc-v/ntl_p1/","api":"https://instructionsets.com/api/v1/risc-v/ntl_p1.json"},{"mnemonic":"NTL.PALL","slug":"ntl_pall","records":1,"summary":"Hint that the target data should not be cached in any level of the cache hierarchy (Transient data).","page":"https://instructionsets.com/risc-v/ntl_pall/","api":"https://instructionsets.com/api/v1/risc-v/ntl_pall.json"},{"mnemonic":"NTL.S1","slug":"ntl_s1","records":1,"summary":"Hint that the subsequent store is non-temporal (Streaming Store).","page":"https://instructionsets.com/risc-v/ntl_s1/","api":"https://instructionsets.com/api/v1/risc-v/ntl_s1.json"},{"mnemonic":"OR","slug":"or","records":1,"summary":"Performs a bitwise logical OR operation.","page":"https://instructionsets.com/risc-v/or/","api":"https://instructionsets.com/api/v1/risc-v/or.json"},{"mnemonic":"ORC.B","slug":"orc_b","records":1,"summary":"Sets each byte of the result to 0xFF if the corresponding byte of the source is non-zero, else 0x00.","page":"https://instructionsets.com/risc-v/orc_b/","api":"https://instructionsets.com/api/v1/risc-v/orc_b.json"},{"mnemonic":"ORI","slug":"ori","records":1,"summary":"Performs a bitwise logical OR with a sign-extended immediate.","page":"https://instructionsets.com/risc-v/ori/","api":"https://instructionsets.com/api/v1/risc-v/ori.json"},{"mnemonic":"ORN","slug":"orn","records":1,"summary":"Performs bitwise OR with the bitwise negation of rs2 (rs1 | ~rs2).","page":"https://instructionsets.com/risc-v/orn/","api":"https://instructionsets.com/api/v1/risc-v/orn.json"},{"mnemonic":"PACK","slug":"pack","records":1,"summary":"Packs the lower halves of rs1 and rs2 into rd.","page":"https://instructionsets.com/risc-v/pack/","api":"https://instructionsets.com/api/v1/risc-v/pack.json"},{"mnemonic":"PACKH","slug":"packh","records":1,"summary":"Packs the lower bytes of rs1 and rs2 into a 16-bit value.","page":"https://instructionsets.com/risc-v/packh/","api":"https://instructionsets.com/api/v1/risc-v/packh.json"},{"mnemonic":"PAUSE","slug":"pause","records":1,"summary":"Hints that the current hart is in a spin-wait loop, allowing the hardware to reduce power consumption or yield resources.","page":"https://instructionsets.com/risc-v/pause/","api":"https://instructionsets.com/api/v1/risc-v/pause.json"},{"mnemonic":"PREFETCH.I","slug":"prefetch_i","records":1,"summary":"Hints to hardware to bring the cache block containing the instruction at the address into the instruction cache.","page":"https://instructionsets.com/risc-v/prefetch_i/","api":"https://instructionsets.com/api/v1/risc-v/prefetch_i.json"},{"mnemonic":"PREFETCH.R","slug":"prefetch_r","records":1,"summary":"Hints to hardware to bring the cache block at the address into the data cache for reading.","page":"https://instructionsets.com/risc-v/prefetch_r/","api":"https://instructionsets.com/api/v1/risc-v/prefetch_r.json"},{"mnemonic":"PREFETCH.W","slug":"prefetch_w","records":1,"summary":"Hints to hardware to bring the cache block at the address into the data cache for writing (exclusive ownership).","page":"https://instructionsets.com/risc-v/prefetch_w/","api":"https://instructionsets.com/api/v1/risc-v/prefetch_w.json"},{"mnemonic":"RDCYCLE","slug":"rdcycle","records":1,"summary":"Reads the lower 32/64 bits of the cycle counter.","page":"https://instructionsets.com/risc-v/rdcycle/","api":"https://instructionsets.com/api/v1/risc-v/rdcycle.json"},{"mnemonic":"RDINSTRET","slug":"rdinstret","records":1,"summary":"Reads the count of instructions retired (completed).","page":"https://instructionsets.com/risc-v/rdinstret/","api":"https://instructionsets.com/api/v1/risc-v/rdinstret.json"},{"mnemonic":"RDTIME","slug":"rdtime","records":1,"summary":"Reads the lower 32/64 bits of the real-time clock.","page":"https://instructionsets.com/risc-v/rdtime/","api":"https://instructionsets.com/api/v1/risc-v/rdtime.json"},{"mnemonic":"REM","slug":"rem","records":1,"summary":"Computes the signed remainder of division.","page":"https://instructionsets.com/risc-v/rem/","api":"https://instructionsets.com/api/v1/risc-v/rem.json"},{"mnemonic":"REMU","slug":"remu","records":1,"summary":"Computes the unsigned remainder of division.","page":"https://instructionsets.com/risc-v/remu/","api":"https://instructionsets.com/api/v1/risc-v/remu.json"},{"mnemonic":"REMUW","slug":"remuw","records":1,"summary":"Computes the remainder of 32-bit unsigned division, sign-extending the result.","page":"https://instructionsets.com/risc-v/remuw/","api":"https://instructionsets.com/api/v1/risc-v/remuw.json"},{"mnemonic":"REMW","slug":"remw","records":1,"summary":"Computes the remainder of 32-bit signed division, sign-extending the result.","page":"https://instructionsets.com/risc-v/remw/","api":"https://instructionsets.com/api/v1/risc-v/remw.json"},{"mnemonic":"RET","slug":"ret","records":1,"summary":"Returns from a subroutine call.","page":"https://instructionsets.com/risc-v/ret/","api":"https://instructionsets.com/api/v1/risc-v/ret.json"},{"mnemonic":"REV8","slug":"rev8","records":1,"summary":"Reverses the order of bytes in a register (Endian swap).","page":"https://instructionsets.com/risc-v/rev8/","api":"https://instructionsets.com/api/v1/risc-v/rev8.json"},{"mnemonic":"ROL","slug":"rol","records":1,"summary":"Rotates the bits in rs1 left by the amount in rs2.","page":"https://instructionsets.com/risc-v/rol/","api":"https://instructionsets.com/api/v1/risc-v/rol.json"},{"mnemonic":"ROR","slug":"ror","records":1,"summary":"Rotates the bits in rs1 right by the amount in rs2.","page":"https://instructionsets.com/risc-v/ror/","api":"https://instructionsets.com/api/v1/risc-v/ror.json"},{"mnemonic":"SB","slug":"sb","records":1,"summary":"Stores the lowest 8 bits of a register to memory.","page":"https://instructionsets.com/risc-v/sb/","api":"https://instructionsets.com/api/v1/risc-v/sb.json"},{"mnemonic":"SC.D","slug":"sc_d","records":1,"summary":"Conditionally stores a 64-bit value to memory if the reservation is valid.","page":"https://instructionsets.com/risc-v/sc_d/","api":"https://instructionsets.com/api/v1/risc-v/sc_d.json"},{"mnemonic":"SC.W","slug":"sc_w","records":1,"summary":"Conditionally stores a word to memory if the reservation (from LR) is still valid.","page":"https://instructionsets.com/risc-v/sc_w/","api":"https://instructionsets.com/api/v1/risc-v/sc_w.json"},{"mnemonic":"SD","slug":"sd","records":1,"summary":"Stores a 64-bit doubleword to memory.","page":"https://instructionsets.com/risc-v/sd/","api":"https://instructionsets.com/api/v1/risc-v/sd.json"},{"mnemonic":"SEQZ","slug":"seqz","records":1,"summary":"Sets rd to 1 if rs is zero, otherwise 0.","page":"https://instructionsets.com/risc-v/seqz/","api":"https://instructionsets.com/api/v1/risc-v/seqz.json"},{"mnemonic":"SEXT.B","slug":"sext_b","records":1,"summary":"Sign-extends the lowest byte (8 bits) to XLEN bits.","page":"https://instructionsets.com/risc-v/sext_b/","api":"https://instructionsets.com/api/v1/risc-v/sext_b.json"},{"mnemonic":"SEXT.H","slug":"sext_h","records":1,"summary":"Sign-extends the lowest halfword (16 bits) to XLEN bits.","page":"https://instructionsets.com/risc-v/sext_h/","api":"https://instructionsets.com/api/v1/risc-v/sext_h.json"},{"mnemonic":"SFENCE.INVAL.IR","slug":"sfence_inval_ir","records":1,"summary":"Invalidates a range of address translations based on ASID and Virtual Address.","page":"https://instructionsets.com/risc-v/sfence_inval_ir/","api":"https://instructionsets.com/api/v1/risc-v/sfence_inval_ir.json"},{"mnemonic":"SFENCE.VMA","slug":"sfence_vma","records":1,"summary":"Synchronizes updates to in-memory address translation data structures (TLB flush).","page":"https://instructionsets.com/risc-v/sfence_vma/","api":"https://instructionsets.com/api/v1/risc-v/sfence_vma.json"},{"mnemonic":"SFENCE.W.INVAL","slug":"sfence_w_inval","records":1,"summary":"Orders previous stores against subsequent local instruction fetches or translations (Memory Management).","page":"https://instructionsets.com/risc-v/sfence_w_inval/","api":"https://instructionsets.com/api/v1/risc-v/sfence_w_inval.json"},{"mnemonic":"SH","slug":"sh","records":1,"summary":"Stores the lowest 16 bits of a register to memory.","page":"https://instructionsets.com/risc-v/sh/","api":"https://instructionsets.com/api/v1/risc-v/sh.json"},{"mnemonic":"SH1ADD","slug":"sh1add","records":1,"summary":"Shifts rs1 left by 1 and adds rs2. Used for calculating addresses of 16-bit elements.","page":"https://instructionsets.com/risc-v/sh1add/","api":"https://instructionsets.com/api/v1/risc-v/sh1add.json"},{"mnemonic":"SH2ADD","slug":"sh2add","records":1,"summary":"Shifts rs1 left by 2 and adds rs2. Used for calculating addresses of 32-bit elements.","page":"https://instructionsets.com/risc-v/sh2add/","api":"https://instructionsets.com/api/v1/risc-v/sh2add.json"},{"mnemonic":"SH3ADD","slug":"sh3add","records":1,"summary":"Shifts rs1 left by 3 and adds rs2. Used for calculating addresses of 64-bit elements.","page":"https://instructionsets.com/risc-v/sh3add/","api":"https://instructionsets.com/api/v1/risc-v/sh3add.json"},{"mnemonic":"SHA256SIG0","slug":"sha256sig0","records":1,"summary":"Performs the Sigma0 transformation function for SHA-256.","page":"https://instructionsets.com/risc-v/sha256sig0/","api":"https://instructionsets.com/api/v1/risc-v/sha256sig0.json"},{"mnemonic":"SHA256SUM0","slug":"sha256sum0","records":1,"summary":"Performs the Sum0 transformation function for SHA-256.","page":"https://instructionsets.com/risc-v/sha256sum0/","api":"https://instructionsets.com/api/v1/risc-v/sha256sum0.json"},{"mnemonic":"SHA512SIG0","slug":"sha512sig0","records":1,"summary":"Performs SHA-512 Sigma0 transformation (RV64).","page":"https://instructionsets.com/risc-v/sha512sig0/","api":"https://instructionsets.com/api/v1/risc-v/sha512sig0.json"},{"mnemonic":"SHA512SIG1","slug":"sha512sig1","records":1,"summary":"Performs SHA-512 Sigma1 transformation (RV64).","page":"https://instructionsets.com/risc-v/sha512sig1/","api":"https://instructionsets.com/api/v1/risc-v/sha512sig1.json"},{"mnemonic":"SHA512SUM0","slug":"sha512sum0","records":1,"summary":"Performs SHA-512 Sum0 transformation (RV64).","page":"https://instructionsets.com/risc-v/sha512sum0/","api":"https://instructionsets.com/api/v1/risc-v/sha512sum0.json"},{"mnemonic":"SHA512SUM1","slug":"sha512sum1","records":1,"summary":"Performs SHA-512 Sum1 transformation (RV64).","page":"https://instructionsets.com/risc-v/sha512sum1/","api":"https://instructionsets.com/api/v1/risc-v/sha512sum1.json"},{"mnemonic":"SLL","slug":"sll","records":1,"summary":"Shifts a register left by the number of bits specified in another register.","page":"https://instructionsets.com/risc-v/sll/","api":"https://instructionsets.com/api/v1/risc-v/sll.json"},{"mnemonic":"SLLI","slug":"slli","records":1,"summary":"Shifts a register left by a constant amount.","page":"https://instructionsets.com/risc-v/slli/","api":"https://instructionsets.com/api/v1/risc-v/slli.json"},{"mnemonic":"SLLIW","slug":"slliw","records":1,"summary":"Shifts the lower 32 bits of rs1 left by a constant, sign-extending the result.","page":"https://instructionsets.com/risc-v/slliw/","api":"https://instructionsets.com/api/v1/risc-v/slliw.json"},{"mnemonic":"SLLW","slug":"sllw","records":1,"summary":"Performs a 32-bit logical left shift on rs1 by the amount in rs2 (lower 5 bits), sign-extending the result.","page":"https://instructionsets.com/risc-v/sllw/","api":"https://instructionsets.com/api/v1/risc-v/sllw.json"},{"mnemonic":"SLT","slug":"slt","records":1,"summary":"Sets rd to 1 if rs1 < rs2 (signed), otherwise 0.","page":"https://instructionsets.com/risc-v/slt/","api":"https://instructionsets.com/api/v1/risc-v/slt.json"},{"mnemonic":"SLTI","slug":"slti","records":1,"summary":"Sets rd to 1 if rs1 < immediate (signed), otherwise 0.","page":"https://instructionsets.com/risc-v/slti/","api":"https://instructionsets.com/api/v1/risc-v/slti.json"},{"mnemonic":"SLTIU","slug":"sltiu","records":1,"summary":"Sets rd to 1 if rs1 < immediate (unsigned comparison), otherwise 0.","page":"https://instructionsets.com/risc-v/sltiu/","api":"https://instructionsets.com/api/v1/risc-v/sltiu.json"},{"mnemonic":"SLTU","slug":"sltu","records":1,"summary":"Sets rd to 1 if rs1 < rs2 (unsigned comparison), otherwise 0.","page":"https://instructionsets.com/risc-v/sltu/","api":"https://instructionsets.com/api/v1/risc-v/sltu.json"},{"mnemonic":"SM3P0","slug":"sm3p0","records":1,"summary":"Performs the P0 permutation for the SM3 hash algorithm.","page":"https://instructionsets.com/risc-v/sm3p0/","api":"https://instructionsets.com/api/v1/risc-v/sm3p0.json"},{"mnemonic":"SM3P1","slug":"sm3p1","records":1,"summary":"Performs the P1 permutation for the SM3 hash algorithm.","page":"https://instructionsets.com/risc-v/sm3p1/","api":"https://instructionsets.com/api/v1/risc-v/sm3p1.json"},{"mnemonic":"SM4ED","slug":"sm4ed","records":1,"summary":"Accelerates the SM4 block cipher (encryption/decryption round).","page":"https://instructionsets.com/risc-v/sm4ed/","api":"https://instructionsets.com/api/v1/risc-v/sm4ed.json"},{"mnemonic":"SM4KS","slug":"sm4ks","records":1,"summary":"Accelerates the SM4 key schedule generation.","page":"https://instructionsets.com/risc-v/sm4ks/","api":"https://instructionsets.com/api/v1/risc-v/sm4ks.json"},{"mnemonic":"SNEZ","slug":"snez","records":1,"summary":"Sets rd to 1 if rs is not zero, otherwise 0.","page":"https://instructionsets.com/risc-v/snez/","api":"https://instructionsets.com/api/v1/risc-v/snez.json"},{"mnemonic":"SRA","slug":"sra","records":1,"summary":"Shifts a register right, preserving the sign bit.","page":"https://instructionsets.com/risc-v/sra/","api":"https://instructionsets.com/api/v1/risc-v/sra.json"},{"mnemonic":"SRAIW","slug":"sraiw","records":1,"summary":"Arithmetically shifts the lower 32 bits of rs1 right by a constant, sign-extending the result.","page":"https://instructionsets.com/risc-v/sraiw/","api":"https://instructionsets.com/api/v1/risc-v/sraiw.json"},{"mnemonic":"SRAW","slug":"sraw","records":1,"summary":"Performs a 32-bit arithmetic right shift on rs1, sign-extending the result.","page":"https://instructionsets.com/risc-v/sraw/","api":"https://instructionsets.com/api/v1/risc-v/sraw.json"},{"mnemonic":"SRET","slug":"sret","records":1,"summary":"Returns from a supervisor-mode trap handler.","page":"https://instructionsets.com/risc-v/sret/","api":"https://instructionsets.com/api/v1/risc-v/sret.json"},{"mnemonic":"SRL","slug":"srl","records":1,"summary":"Shifts a register right, shifting in zeros.","page":"https://instructionsets.com/risc-v/srl/","api":"https://instructionsets.com/api/v1/risc-v/srl.json"},{"mnemonic":"SRLIW","slug":"srliw","records":1,"summary":"Logically shifts the lower 32 bits of rs1 right by a constant, sign-extending the result.","page":"https://instructionsets.com/risc-v/srliw/","api":"https://instructionsets.com/api/v1/risc-v/srliw.json"},{"mnemonic":"SRLW","slug":"srlw","records":1,"summary":"Performs a 32-bit logical right shift on rs1 by the amount in rs2, sign-extending the result.","page":"https://instructionsets.com/risc-v/srlw/","api":"https://instructionsets.com/api/v1/risc-v/srlw.json"},{"mnemonic":"SUB","slug":"sub","records":1,"summary":"Subtracts rs2 from rs1.","page":"https://instructionsets.com/risc-v/sub/","api":"https://instructionsets.com/api/v1/risc-v/sub.json"},{"mnemonic":"SUBW","slug":"subw","records":1,"summary":"Subtracts the lower 32 bits of rs2 from rs1 and sign-extends the result to 64 bits.","page":"https://instructionsets.com/risc-v/subw/","api":"https://instructionsets.com/api/v1/risc-v/subw.json"},{"mnemonic":"SW","slug":"sw","records":1,"summary":"Stores a 32-bit word to memory.","page":"https://instructionsets.com/risc-v/sw/","api":"https://instructionsets.com/api/v1/risc-v/sw.json"},{"mnemonic":"URET","slug":"uret","records":1,"summary":"Returns from a user-mode trap handler (requires N extension).","page":"https://instructionsets.com/risc-v/uret/","api":"https://instructionsets.com/api/v1/risc-v/uret.json"},{"mnemonic":"VAADD.VV","slug":"vaadd_vv","records":1,"summary":"Computes (vs1 + vs2) >> 1 with rounding.","page":"https://instructionsets.com/risc-v/vaadd_vv/","api":"https://instructionsets.com/api/v1/risc-v/vaadd_vv.json"},{"mnemonic":"VAADDU.VV","slug":"vaaddu_vv","records":1,"summary":"Computes (a + b + 1) >> 1 for unsigned integers.","page":"https://instructionsets.com/risc-v/vaaddu_vv/","api":"https://instructionsets.com/api/v1/risc-v/vaaddu_vv.json"},{"mnemonic":"VADC.VVM","slug":"vadc_vvm","records":1,"summary":"Computes vd = vs1 + vs2 + carry (v0).","page":"https://instructionsets.com/risc-v/vadc_vvm/","api":"https://instructionsets.com/api/v1/risc-v/vadc_vvm.json"},{"mnemonic":"VADD.VI","slug":"vadd_vi","records":1,"summary":"Adds immediate to vector.","page":"https://instructionsets.com/risc-v/vadd_vi/","api":"https://instructionsets.com/api/v1/risc-v/vadd_vi.json"},{"mnemonic":"VADD.VV","slug":"vadd_vv","records":1,"summary":"Adds elements of two vector registers.","page":"https://instructionsets.com/risc-v/vadd_vv/","api":"https://instructionsets.com/api/v1/risc-v/vadd_vv.json"},{"mnemonic":"VAESDF.VV","slug":"vaesdf_vv","records":1,"summary":"Performs the final AES decryption round.","page":"https://instructionsets.com/risc-v/vaesdf_vv/","api":"https://instructionsets.com/api/v1/risc-v/vaesdf_vv.json"},{"mnemonic":"VAESDM.VV","slug":"vaesdm_vv","records":1,"summary":"Performs a middle AES decryption round.","page":"https://instructionsets.com/risc-v/vaesdm_vv/","api":"https://instructionsets.com/api/v1/risc-v/vaesdm_vv.json"},{"mnemonic":"VAESEF.VV","slug":"vaesef_vv","records":1,"summary":"Performs the final AES encryption round.","page":"https://instructionsets.com/risc-v/vaesef_vv/","api":"https://instructionsets.com/api/v1/risc-v/vaesef_vv.json"},{"mnemonic":"VAESEM.VV","slug":"vaesem_vv","records":1,"summary":"Performs a middle AES encryption round.","page":"https://instructionsets.com/risc-v/vaesem_vv/","api":"https://instructionsets.com/api/v1/risc-v/vaesem_vv.json"},{"mnemonic":"VAESKF1.VI","slug":"vaeskf1_vi","records":1,"summary":"Generates the next round key for AES (Step 1).","page":"https://instructionsets.com/risc-v/vaeskf1_vi/","api":"https://instructionsets.com/api/v1/risc-v/vaeskf1_vi.json"},{"mnemonic":"VAESKF2.VI","slug":"vaeskf2_vi","records":1,"summary":"Generates the next round key for AES (Step 2).","page":"https://instructionsets.com/risc-v/vaeskf2_vi/","api":"https://instructionsets.com/api/v1/risc-v/vaeskf2_vi.json"},{"mnemonic":"VAMOADDD.V","slug":"vamoaddd_v","records":1,"summary":"Atomically adds elements from vs2 to memory addresses (64-bit).","page":"https://instructionsets.com/risc-v/vamoaddd_v/","api":"https://instructionsets.com/api/v1/risc-v/vamoaddd_v.json"},{"mnemonic":"VAMOADDW.V","slug":"vamoaddw_v","records":1,"summary":"Atomically adds elements from vs2 to memory addresses in rs1 (indexed by vs2? No, rs1 is base, vs2 is index).","page":"https://instructionsets.com/risc-v/vamoaddw_v/","api":"https://instructionsets.com/api/v1/risc-v/vamoaddw_v.json"},{"mnemonic":"VAMOANDD.V","slug":"vamoandd_v","records":1,"summary":"Atomically ANDs elements (64-bit).","page":"https://instructionsets.com/risc-v/vamoandd_v/","api":"https://instructionsets.com/api/v1/risc-v/vamoandd_v.json"},{"mnemonic":"VAMOANDW.V","slug":"vamoandw_v","records":1,"summary":"Atomically ANDs elements.","page":"https://instructionsets.com/risc-v/vamoandw_v/","api":"https://instructionsets.com/api/v1/risc-v/vamoandw_v.json"},{"mnemonic":"VAMOMAXD.V","slug":"vamomaxd_v","records":1,"summary":"Atomic Max (Signed, 64-bit).","page":"https://instructionsets.com/risc-v/vamomaxd_v/","api":"https://instructionsets.com/api/v1/risc-v/vamomaxd_v.json"},{"mnemonic":"VAMOMAXU.V","slug":"vamomaxu_v","records":1,"summary":"Atomic Max (Unsigned, Width implicit).","page":"https://instructionsets.com/risc-v/vamomaxu_v/","api":"https://instructionsets.com/api/v1/risc-v/vamomaxu_v.json"},{"mnemonic":"VAMOMAXW.V","slug":"vamomaxw_v","records":1,"summary":"Atomic Max (Signed).","page":"https://instructionsets.com/risc-v/vamomaxw_v/","api":"https://instructionsets.com/api/v1/risc-v/vamomaxw_v.json"},{"mnemonic":"VAMOMIND.V","slug":"vamomind_v","records":1,"summary":"Atomic Min (Signed, 64-bit).","page":"https://instructionsets.com/risc-v/vamomind_v/","api":"https://instructionsets.com/api/v1/risc-v/vamomind_v.json"},{"mnemonic":"VAMOMINU.V","slug":"vamominu_v","records":1,"summary":"Atomic Min (Unsigned, Width implicit).","page":"https://instructionsets.com/risc-v/vamominu_v/","api":"https://instructionsets.com/api/v1/risc-v/vamominu_v.json"},{"mnemonic":"VAMOMINW.V","slug":"vamominw_v","records":1,"summary":"Atomic Min (Signed).","page":"https://instructionsets.com/risc-v/vamominw_v/","api":"https://instructionsets.com/api/v1/risc-v/vamominw_v.json"},{"mnemonic":"VAMOORD.V","slug":"vamoord_v","records":1,"summary":"Atomically ORs elements (64-bit).","page":"https://instructionsets.com/risc-v/vamoord_v/","api":"https://instructionsets.com/api/v1/risc-v/vamoord_v.json"},{"mnemonic":"VAMOORW.V","slug":"vamoorw_v","records":1,"summary":"Atomically ORs elements.","page":"https://instructionsets.com/risc-v/vamoorw_v/","api":"https://instructionsets.com/api/v1/risc-v/vamoorw_v.json"},{"mnemonic":"VAMOXORD.V","slug":"vamoxord_v","records":1,"summary":"Atomically XORs elements (64-bit).","page":"https://instructionsets.com/risc-v/vamoxord_v/","api":"https://instructionsets.com/api/v1/risc-v/vamoxord_v.json"},{"mnemonic":"VAMOXORW.V","slug":"vamoxorw_v","records":1,"summary":"Atomically XORs elements.","page":"https://instructionsets.com/risc-v/vamoxorw_v/","api":"https://instructionsets.com/api/v1/risc-v/vamoxorw_v.json"},{"mnemonic":"VAND.VI","slug":"vand_vi","records":1,"summary":"Bitwise AND with immediate.","page":"https://instructionsets.com/risc-v/vand_vi/","api":"https://instructionsets.com/api/v1/risc-v/vand_vi.json"},{"mnemonic":"VANDN.VV","slug":"vandn_vv","records":1,"summary":"Computes vd = vs2 & ~vs1 (bitwise AND with inverted source).","page":"https://instructionsets.com/risc-v/vandn_vv/","api":"https://instructionsets.com/api/v1/risc-v/vandn_vv.json"},{"mnemonic":"VANDN.VX","slug":"vandn_vx","records":1,"summary":"Computes vd = vs2 & ~rs1.","page":"https://instructionsets.com/risc-v/vandn_vx/","api":"https://instructionsets.com/api/v1/risc-v/vandn_vx.json"},{"mnemonic":"VASUB.VV","slug":"vasub_vv","records":1,"summary":"Computes (a - b) >> 1 for signed integers.","page":"https://instructionsets.com/risc-v/vasub_vv/","api":"https://instructionsets.com/api/v1/risc-v/vasub_vv.json"},{"mnemonic":"VASUBU.VV","slug":"vasubu_vv","records":1,"summary":"Computes (a - b) >> 1 for unsigned integers.","page":"https://instructionsets.com/risc-v/vasubu_vv/","api":"https://instructionsets.com/api/v1/risc-v/vasubu_vv.json"},{"mnemonic":"VBREV8.V","slug":"vbrev8_v","records":1,"summary":"Reverses the bits within each byte of the source elements.","page":"https://instructionsets.com/risc-v/vbrev8_v/","api":"https://instructionsets.com/api/v1/risc-v/vbrev8_v.json"},{"mnemonic":"VCLMUL.VV","slug":"vclmul_vv","records":1,"summary":"Performs carry-less multiplication on vector elements (GF(2^n)).","page":"https://instructionsets.com/risc-v/vclmul_vv/","api":"https://instructionsets.com/api/v1/risc-v/vclmul_vv.json"},{"mnemonic":"VCLMULH.VV","slug":"vclmulh_vv","records":1,"summary":"Performs carry-less multiplication, keeping the high half.","page":"https://instructionsets.com/risc-v/vclmulh_vv/","api":"https://instructionsets.com/api/v1/risc-v/vclmulh_vv.json"},{"mnemonic":"VCLZ.V","slug":"vclz_v","records":1,"summary":"Counts the number of leading zero bits in each element.","page":"https://instructionsets.com/risc-v/vclz_v/","api":"https://instructionsets.com/api/v1/risc-v/vclz_v.json"},{"mnemonic":"VCOMPRESS.VM","slug":"vcompress_vm","records":1,"summary":"Compacts elements from source vector into contiguous elements in dest where the mask is 1.","page":"https://instructionsets.com/risc-v/vcompress_vm/","api":"https://instructionsets.com/api/v1/risc-v/vcompress_vm.json"},{"mnemonic":"VCPOP.M","slug":"vcpop_m","records":1,"summary":"Counts set bits in the source mask register.","page":"https://instructionsets.com/risc-v/vcpop_m/","api":"https://instructionsets.com/api/v1/risc-v/vcpop_m.json"},{"mnemonic":"VCPOP.V","slug":"vcpop_v","records":1,"summary":"Counts the number of set bits (1s) in each element.","page":"https://instructionsets.com/risc-v/vcpop_v/","api":"https://instructionsets.com/api/v1/risc-v/vcpop_v.json"},{"mnemonic":"VCTZ.V","slug":"vctz_v","records":1,"summary":"Counts the number of trailing zero bits in each element.","page":"https://instructionsets.com/risc-v/vctz_v/","api":"https://instructionsets.com/api/v1/risc-v/vctz_v.json"},{"mnemonic":"VDIV.VV","slug":"vdiv_vv","records":1,"summary":"Divides signed vector elements.","page":"https://instructionsets.com/risc-v/vdiv_vv/","api":"https://instructionsets.com/api/v1/risc-v/vdiv_vv.json"},{"mnemonic":"VDIVU.VV","slug":"vdivu_vv","records":1,"summary":"Divides unsigned vector elements.","page":"https://instructionsets.com/risc-v/vdivu_vv/","api":"https://instructionsets.com/api/v1/risc-v/vdivu_vv.json"},{"mnemonic":"VFADD.VV","slug":"vfadd_vv","records":1,"summary":"Adds elements of two vector registers (Floating Point).","page":"https://instructionsets.com/risc-v/vfadd_vv/","api":"https://instructionsets.com/api/v1/risc-v/vfadd_vv.json"},{"mnemonic":"VFCLASS.V","slug":"vfclass_v","records":1,"summary":"Classifies elements of a float vector (NaN, Inf, etc.).","page":"https://instructionsets.com/risc-v/vfclass_v/","api":"https://instructionsets.com/api/v1/risc-v/vfclass_v.json"},{"mnemonic":"VFCVT.F.X.V","slug":"vfcvt_f_x_v","records":1,"summary":"Converts signed integer elements to floating-point.","page":"https://instructionsets.com/risc-v/vfcvt_f_x_v/","api":"https://instructionsets.com/api/v1/risc-v/vfcvt_f_x_v.json"},{"mnemonic":"VFCVT.X.F.V","slug":"vfcvt_x_f_v","records":1,"summary":"Converts floating-point elements to signed integers.","page":"https://instructionsets.com/risc-v/vfcvt_x_f_v/","api":"https://instructionsets.com/api/v1/risc-v/vfcvt_x_f_v.json"},{"mnemonic":"VFDIV.VV","slug":"vfdiv_vv","records":1,"summary":"Divides elements of two floating-point vectors.","page":"https://instructionsets.com/risc-v/vfdiv_vv/","api":"https://instructionsets.com/api/v1/risc-v/vfdiv_vv.json"},{"mnemonic":"VFIRST.M","slug":"vfirst_m","records":1,"summary":"Finds the index of the first set bit in the mask.","page":"https://instructionsets.com/risc-v/vfirst_m/","api":"https://instructionsets.com/api/v1/risc-v/vfirst_m.json"},{"mnemonic":"VFMADD.VV","slug":"vfmadd_vv","records":1,"summary":"Computes (vs1 * vs2) + vd (overwriting vd) with single rounding.","page":"https://instructionsets.com/risc-v/vfmadd_vv/","api":"https://instructionsets.com/api/v1/risc-v/vfmadd_vv.json"},{"mnemonic":"VFMAX.VV","slug":"vfmax_vv","records":1,"summary":"Writes the larger of two floating-point vector elements to vd.","page":"https://instructionsets.com/risc-v/vfmax_vv/","api":"https://instructionsets.com/api/v1/risc-v/vfmax_vv.json"},{"mnemonic":"VFMIN.VV","slug":"vfmin_vv","records":1,"summary":"Writes the smaller of two floating-point vector elements to vd.","page":"https://instructionsets.com/risc-v/vfmin_vv/","api":"https://instructionsets.com/api/v1/risc-v/vfmin_vv.json"},{"mnemonic":"VFMUL.VV","slug":"vfmul_vv","records":1,"summary":"Multiplies elements of two floating-point vectors.","page":"https://instructionsets.com/risc-v/vfmul_vv/","api":"https://instructionsets.com/api/v1/risc-v/vfmul_vv.json"},{"mnemonic":"VFMV.F.S","slug":"vfmv_f_s","records":1,"summary":"Moves element 0 of a float vector to a scalar float register.","page":"https://instructionsets.com/risc-v/vfmv_f_s/","api":"https://instructionsets.com/api/v1/risc-v/vfmv_f_s.json"},{"mnemonic":"VFMV.S.F","slug":"vfmv_s_f","records":1,"summary":"Moves a scalar float register to element 0 of a vector.","page":"https://instructionsets.com/risc-v/vfmv_s_f/","api":"https://instructionsets.com/api/v1/risc-v/vfmv_s_f.json"},{"mnemonic":"VFNCVT.F.F.W","slug":"vfncvt_f_f_w","records":1,"summary":"Converts 2*N-bit floats to N-bit floats (e.g., FP32 -> FP16).","page":"https://instructionsets.com/risc-v/vfncvt_f_f_w/","api":"https://instructionsets.com/api/v1/risc-v/vfncvt_f_f_w.json"},{"mnemonic":"VFNCVT.X.F.W","slug":"vfncvt_x_f_w","records":1,"summary":"Converts 2*N-bit float to N-bit signed integer.","page":"https://instructionsets.com/risc-v/vfncvt_x_f_w/","api":"https://instructionsets.com/api/v1/risc-v/vfncvt_x_f_w.json"},{"mnemonic":"VFREC7.V","slug":"vfrec7_v","records":1,"summary":"Computes an estimate of 1/x (7-bit precision). Used for fast division/normalization loops.","page":"https://instructionsets.com/risc-v/vfrec7_v/","api":"https://instructionsets.com/api/v1/risc-v/vfrec7_v.json"},{"mnemonic":"VFREDMAX.VS","slug":"vfredmax_vs","records":1,"summary":"Reduces a float vector to a scalar by finding the maximum element.","page":"https://instructionsets.com/risc-v/vfredmax_vs/","api":"https://instructionsets.com/api/v1/risc-v/vfredmax_vs.json"},{"mnemonic":"VFREDOSUM.VS","slug":"vfredosum_vs","records":1,"summary":"Sums float vector elements in exact order (0 to vl-1).","page":"https://instructionsets.com/risc-v/vfredosum_vs/","api":"https://instructionsets.com/api/v1/risc-v/vfredosum_vs.json"},{"mnemonic":"VFREDUSUM.VS","slug":"vfredusum_vs","records":1,"summary":"Reduces a float vector to a scalar by summing elements (Order not preserved, faster).","page":"https://instructionsets.com/risc-v/vfredusum_vs/","api":"https://instructionsets.com/api/v1/risc-v/vfredusum_vs.json"},{"mnemonic":"VFRSQRT7.V","slug":"vfrsqrt7_v","records":1,"summary":"Computes an estimate of 1/sqrt(x). Critical for vector normalization.","page":"https://instructionsets.com/risc-v/vfrsqrt7_v/","api":"https://instructionsets.com/api/v1/risc-v/vfrsqrt7_v.json"},{"mnemonic":"VFSGNJ.VV","slug":"vfsgnj_vv","records":1,"summary":"Injects the sign of vs2 into vs1 (Copy Sign).","page":"https://instructionsets.com/risc-v/vfsgnj_vv/","api":"https://instructionsets.com/api/v1/risc-v/vfsgnj_vv.json"},{"mnemonic":"VFSQRT.V","slug":"vfsqrt_v","records":1,"summary":"Computes the square root of elements in a floating-point vector.","page":"https://instructionsets.com/risc-v/vfsqrt_v/","api":"https://instructionsets.com/api/v1/risc-v/vfsqrt_v.json"},{"mnemonic":"VFWADD.VV","slug":"vfwadd_vv","records":1,"summary":"Adds N-bit floats to produce 2*N-bit float results (e.g., FP16 + FP16 -> FP32).","page":"https://instructionsets.com/risc-v/vfwadd_vv/","api":"https://instructionsets.com/api/v1/risc-v/vfwadd_vv.json"},{"mnemonic":"VFWCVT.F.F.V","slug":"vfwcvt_f_f_v","records":1,"summary":"Converts N-bit floats to 2*N-bit floats (e.g., FP16 -> FP32).","page":"https://instructionsets.com/risc-v/vfwcvt_f_f_v/","api":"https://instructionsets.com/api/v1/risc-v/vfwcvt_f_f_v.json"},{"mnemonic":"VFWCVT.F.X.V","slug":"vfwcvt_f_x_v","records":1,"summary":"Converts N-bit integers to 2*N-bit floats (e.g., Int16 -> FP32).","page":"https://instructionsets.com/risc-v/vfwcvt_f_x_v/","api":"https://instructionsets.com/api/v1/risc-v/vfwcvt_f_x_v.json"},{"mnemonic":"VFWCVT.X.F.V","slug":"vfwcvt_x_f_v","records":1,"summary":"Converts N-bit float to 2*N-bit signed integer.","page":"https://instructionsets.com/risc-v/vfwcvt_x_f_v/","api":"https://instructionsets.com/api/v1/risc-v/vfwcvt_x_f_v.json"},{"mnemonic":"VFWMUL.VV","slug":"vfwmul_vv","records":1,"summary":"Multiplies N-bit floats to produce 2*N-bit float results.","page":"https://instructionsets.com/risc-v/vfwmul_vv/","api":"https://instructionsets.com/api/v1/risc-v/vfwmul_vv.json"},{"mnemonic":"VFWREDOSUM.VS","slug":"vfwredosum_vs","records":1,"summary":"Sums N-bit floats into 2*N-bit scalar accumulator (Ordered).","page":"https://instructionsets.com/risc-v/vfwredosum_vs/","api":"https://instructionsets.com/api/v1/risc-v/vfwredosum_vs.json"},{"mnemonic":"VFWREDUSUM.VS","slug":"vfwredusum_vs","records":1,"summary":"Sums N-bit floats into 2*N-bit scalar accumulator (Unordered).","page":"https://instructionsets.com/risc-v/vfwredusum_vs/","api":"https://instructionsets.com/api/v1/risc-v/vfwredusum_vs.json"},{"mnemonic":"VGHSH.VV","slug":"vghsh_vv","records":1,"summary":"Performs GHASH multiply-add for AES-GCM.","page":"https://instructionsets.com/risc-v/vghsh_vv/","api":"https://instructionsets.com/api/v1/risc-v/vghsh_vv.json"},{"mnemonic":"VID.V","slug":"vid_v","records":1,"summary":"Writes the element index (0, 1, 2...) to the destination.","page":"https://instructionsets.com/risc-v/vid_v/","api":"https://instructionsets.com/api/v1/risc-v/vid_v.json"},{"mnemonic":"VIOTA.M","slug":"viota_m","records":1,"summary":"Writes the index of the active element to the destination. Useful for parallel prefix sums.","page":"https://instructionsets.com/risc-v/viota_m/","api":"https://instructionsets.com/api/v1/risc-v/viota_m.json"},{"mnemonic":"VLE16.V","slug":"vle16_v","records":1,"summary":"Loads a vector of 16-bit elements from memory.","page":"https://instructionsets.com/risc-v/vle16_v/","api":"https://instructionsets.com/api/v1/risc-v/vle16_v.json"},{"mnemonic":"VLE16FF.V","slug":"vle16ff_v","records":1,"summary":"Loads 16-bit elements with fault suppression.","page":"https://instructionsets.com/risc-v/vle16ff_v/","api":"https://instructionsets.com/api/v1/risc-v/vle16ff_v.json"},{"mnemonic":"VLE32.V","slug":"vle32_v","records":1,"summary":"Loads a vector of 32-bit elements from memory into a vector register.","page":"https://instructionsets.com/risc-v/vle32_v/","api":"https://instructionsets.com/api/v1/risc-v/vle32_v.json"},{"mnemonic":"VLE32FF.V","slug":"vle32ff_v","records":1,"summary":"Loads 32-bit elements with fault suppression.","page":"https://instructionsets.com/risc-v/vle32ff_v/","api":"https://instructionsets.com/api/v1/risc-v/vle32ff_v.json"},{"mnemonic":"VLE64.V","slug":"vle64_v","records":1,"summary":"Loads a vector of 64-bit elements from memory.","page":"https://instructionsets.com/risc-v/vle64_v/","api":"https://instructionsets.com/api/v1/risc-v/vle64_v.json"},{"mnemonic":"VLE64FF.V","slug":"vle64ff_v","records":1,"summary":"Loads 64-bit elements with fault suppression.","page":"https://instructionsets.com/risc-v/vle64ff_v/","api":"https://instructionsets.com/api/v1/risc-v/vle64ff_v.json"},{"mnemonic":"VLE8.V","slug":"vle8_v","records":1,"summary":"Loads a vector of 8-bit elements from memory.","page":"https://instructionsets.com/risc-v/vle8_v/","api":"https://instructionsets.com/api/v1/risc-v/vle8_v.json"},{"mnemonic":"VLE8FF.V","slug":"vle8ff_v","records":1,"summary":"Loads 8-bit elements, suppressing faults on elements after the first. Sets VL to number of elements loaded. Critical for strings.","page":"https://instructionsets.com/risc-v/vle8ff_v/","api":"https://instructionsets.com/api/v1/risc-v/vle8ff_v.json"},{"mnemonic":"VLM.V","slug":"vlm_v","records":1,"summary":"Loads a vector mask register from memory.","page":"https://instructionsets.com/risc-v/vlm_v/","api":"https://instructionsets.com/api/v1/risc-v/vlm_v.json"},{"mnemonic":"VLOXEI32.V","slug":"vloxei32_v","records":1,"summary":"Loads elements using indices, ensuring order (useful for I/O buffers).","page":"https://instructionsets.com/risc-v/vloxei32_v/","api":"https://instructionsets.com/api/v1/risc-v/vloxei32_v.json"},{"mnemonic":"VLSE32.V","slug":"vlse32_v","records":1,"summary":"Loads elements from memory with a fixed stride.","page":"https://instructionsets.com/risc-v/vlse32_v/","api":"https://instructionsets.com/api/v1/risc-v/vlse32_v.json"},{"mnemonic":"VLSEG2E16.V","slug":"vlseg2e16_v","records":1,"summary":"Loads 2 fields (e.g., Complex Real/Imag) of 16-bit elements.","page":"https://instructionsets.com/risc-v/vlseg2e16_v/","api":"https://instructionsets.com/api/v1/risc-v/vlseg2e16_v.json"},{"mnemonic":"VLSEG3E8.V","slug":"vlseg3e8_v","records":1,"summary":"Loads 3 fields (e.g., RGB) of 8-bit elements into 3 vector registers.","page":"https://instructionsets.com/risc-v/vlseg3e8_v/","api":"https://instructionsets.com/api/v1/risc-v/vlseg3e8_v.json"},{"mnemonic":"VLSEG4E8.V","slug":"vlseg4e8_v","records":1,"summary":"Loads 4 fields (e.g., RGBA) of 8-bit elements into 4 vector registers.","page":"https://instructionsets.com/risc-v/vlseg4e8_v/","api":"https://instructionsets.com/api/v1/risc-v/vlseg4e8_v.json"},{"mnemonic":"VLUXEI32.V","slug":"vluxei32_v","records":1,"summary":"Loads elements from memory using a vector of indices (Gather).","page":"https://instructionsets.com/risc-v/vluxei32_v/","api":"https://instructionsets.com/api/v1/risc-v/vluxei32_v.json"},{"mnemonic":"VMACC.VV","slug":"vmacc_vv","records":1,"summary":"Computes vd = vd + (vs1 * vs2). Essential for dot products.","page":"https://instructionsets.com/risc-v/vmacc_vv/","api":"https://instructionsets.com/api/v1/risc-v/vmacc_vv.json"},{"mnemonic":"VMADC.VIM","slug":"vmadc_vim","records":1,"summary":"Add Immediate with Carry.","page":"https://instructionsets.com/risc-v/vmadc_vim/","api":"https://instructionsets.com/api/v1/risc-v/vmadc_vim.json"},{"mnemonic":"VMADC.VVM","slug":"vmadc_vvm","records":1,"summary":"Adds two vectors and a carry-in, producing the carry-out to the destination mask.","page":"https://instructionsets.com/risc-v/vmadc_vvm/","api":"https://instructionsets.com/api/v1/risc-v/vmadc_vvm.json"},{"mnemonic":"VMAND.MM","slug":"vmand_mm","records":1,"summary":"Performs bitwise AND on vector mask registers.","page":"https://instructionsets.com/risc-v/vmand_mm/","api":"https://instructionsets.com/api/v1/risc-v/vmand_mm.json"},{"mnemonic":"VMANDN.MM","slug":"vmandn_mm","records":1,"summary":"Computes vd = vs1 & ~vs2 (mask operation).","page":"https://instructionsets.com/risc-v/vmandn_mm/","api":"https://instructionsets.com/api/v1/risc-v/vmandn_mm.json"},{"mnemonic":"VMAX.VV","slug":"vmax_vv","records":1,"summary":"Computes the signed maximum of elements in two vectors.","page":"https://instructionsets.com/risc-v/vmax_vv/","api":"https://instructionsets.com/api/v1/risc-v/vmax_vv.json"},{"mnemonic":"VMAXU.VV","slug":"vmaxu_vv","records":1,"summary":"Computes the unsigned maximum of elements in two vectors.","page":"https://instructionsets.com/risc-v/vmaxu_vv/","api":"https://instructionsets.com/api/v1/risc-v/vmaxu_vv.json"},{"mnemonic":"VMERGE.VIM","slug":"vmerge_vim","records":1,"summary":"Merges immediate vs vector based on mask.","page":"https://instructionsets.com/risc-v/vmerge_vim/","api":"https://instructionsets.com/api/v1/risc-v/vmerge_vim.json"},{"mnemonic":"VMERGE.VVM","slug":"vmerge_vvm","records":1,"summary":"Merges two vectors based on the mask (if mask=0, pick vs2; if mask=1, pick vs1).","page":"https://instructionsets.com/risc-v/vmerge_vvm/","api":"https://instructionsets.com/api/v1/risc-v/vmerge_vvm.json"},{"mnemonic":"VMERGE.VXM","slug":"vmerge_vxm","records":1,"summary":"Merges integer scalar vs vector based on mask.","page":"https://instructionsets.com/risc-v/vmerge_vxm/","api":"https://instructionsets.com/api/v1/risc-v/vmerge_vxm.json"},{"mnemonic":"VMFEQ.VV","slug":"vmfeq_vv","records":1,"summary":"Compares float vectors for equality, writing result to mask register.","page":"https://instructionsets.com/risc-v/vmfeq_vv/","api":"https://instructionsets.com/api/v1/risc-v/vmfeq_vv.json"},{"mnemonic":"VMFLE.VV","slug":"vmfle_vv","records":1,"summary":"Compares float vectors (vs2 <= vs1), writing result to mask register.","page":"https://instructionsets.com/risc-v/vmfle_vv/","api":"https://instructionsets.com/api/v1/risc-v/vmfle_vv.json"},{"mnemonic":"VMFLT.VV","slug":"vmflt_vv","records":1,"summary":"Compares float vectors (vs2 < vs1), writing result to mask register.","page":"https://instructionsets.com/risc-v/vmflt_vv/","api":"https://instructionsets.com/api/v1/risc-v/vmflt_vv.json"},{"mnemonic":"VMIN.VV","slug":"vmin_vv","records":1,"summary":"Computes the signed minimum of elements in two vectors.","page":"https://instructionsets.com/risc-v/vmin_vv/","api":"https://instructionsets.com/api/v1/risc-v/vmin_vv.json"},{"mnemonic":"VMINU.VV","slug":"vminu_vv","records":1,"summary":"Computes the unsigned minimum of elements in two vectors.","page":"https://instructionsets.com/risc-v/vminu_vv/","api":"https://instructionsets.com/api/v1/risc-v/vminu_vv.json"},{"mnemonic":"VMNAND.MM","slug":"vmnand_mm","records":1,"summary":"Performs bitwise NAND on vector mask registers. Used to invert masks (NOT).","page":"https://instructionsets.com/risc-v/vmnand_mm/","api":"https://instructionsets.com/api/v1/risc-v/vmnand_mm.json"},{"mnemonic":"VMORN.MM","slug":"vmorn_mm","records":1,"summary":"Computes vd = vs1 | ~vs2 (mask operation).","page":"https://instructionsets.com/risc-v/vmorn_mm/","api":"https://instructionsets.com/api/v1/risc-v/vmorn_mm.json"},{"mnemonic":"VMSBC.VV","slug":"vmsbc_vv","records":1,"summary":"Writes a mask where bits are 1 before the first element in vs2 that is 1.","page":"https://instructionsets.com/risc-v/vmsbc_vv/","api":"https://instructionsets.com/api/v1/risc-v/vmsbc_vv.json"},{"mnemonic":"VMSBF.M","slug":"vmsbf_m","records":1,"summary":"Sets mask bits before the first set bit in the source mask.","page":"https://instructionsets.com/risc-v/vmsbf_m/","api":"https://instructionsets.com/api/v1/risc-v/vmsbf_m.json"},{"mnemonic":"VMSEQ.VI","slug":"vmseq_vi","records":1,"summary":"Sets mask if element == imm.","page":"https://instructionsets.com/risc-v/vmseq_vi/","api":"https://instructionsets.com/api/v1/risc-v/vmseq_vi.json"},{"mnemonic":"VMSEQ.VV","slug":"vmseq_vv","records":1,"summary":"Sets destination mask bit if elements are equal.","page":"https://instructionsets.com/risc-v/vmseq_vv/","api":"https://instructionsets.com/api/v1/risc-v/vmseq_vv.json"},{"mnemonic":"VMSGE.VV","slug":"vmsge_vv","records":1,"summary":"Sets mask if vs2 >= vs1.","page":"https://instructionsets.com/risc-v/vmsge_vv/","api":"https://instructionsets.com/api/v1/risc-v/vmsge_vv.json"},{"mnemonic":"VMSGEU.VV","slug":"vmsgeu_vv","records":1,"summary":"Sets mask if vs2 >= vs1 (Unsigned).","page":"https://instructionsets.com/risc-v/vmsgeu_vv/","api":"https://instructionsets.com/api/v1/risc-v/vmsgeu_vv.json"},{"mnemonic":"VMSGT.VV","slug":"vmsgt_vv","records":1,"summary":"Sets mask if vs2 > vs1.","page":"https://instructionsets.com/risc-v/vmsgt_vv/","api":"https://instructionsets.com/api/v1/risc-v/vmsgt_vv.json"},{"mnemonic":"VMSGTU.VV","slug":"vmsgtu_vv","records":1,"summary":"Sets mask if vs2 > vs1 (Unsigned).","page":"https://instructionsets.com/risc-v/vmsgtu_vv/","api":"https://instructionsets.com/api/v1/risc-v/vmsgtu_vv.json"},{"mnemonic":"VMSIF.M","slug":"vmsif_m","records":1,"summary":"Sets mask bits up to and including the first set bit in the source.","page":"https://instructionsets.com/risc-v/vmsif_m/","api":"https://instructionsets.com/api/v1/risc-v/vmsif_m.json"},{"mnemonic":"VMSLE.VI","slug":"vmsle_vi","records":1,"summary":"Sets mask if element <= imm (Signed).","page":"https://instructionsets.com/risc-v/vmsle_vi/","api":"https://instructionsets.com/api/v1/risc-v/vmsle_vi.json"},{"mnemonic":"VMSLE.VV","slug":"vmsle_vv","records":1,"summary":"Sets mask if vs2 <= vs1.","page":"https://instructionsets.com/risc-v/vmsle_vv/","api":"https://instructionsets.com/api/v1/risc-v/vmsle_vv.json"},{"mnemonic":"VMSLEU.VI","slug":"vmsleu_vi","records":1,"summary":"Sets mask if element <= imm (Unsigned).","page":"https://instructionsets.com/risc-v/vmsleu_vi/","api":"https://instructionsets.com/api/v1/risc-v/vmsleu_vi.json"},{"mnemonic":"VMSLEU.VV","slug":"vmsleu_vv","records":1,"summary":"Sets mask if vs2 <= vs1 (Unsigned).","page":"https://instructionsets.com/risc-v/vmsleu_vv/","api":"https://instructionsets.com/api/v1/risc-v/vmsleu_vv.json"},{"mnemonic":"VMSLT.VI","slug":"vmslt_vi","records":1,"summary":"Sets mask if element < imm (Signed).","page":"https://instructionsets.com/risc-v/vmslt_vi/","api":"https://instructionsets.com/api/v1/risc-v/vmslt_vi.json"},{"mnemonic":"VMSLT.VV","slug":"vmslt_vv","records":1,"summary":"Sets destination mask bit if vs2 < vs1 (signed).","page":"https://instructionsets.com/risc-v/vmslt_vv/","api":"https://instructionsets.com/api/v1/risc-v/vmslt_vv.json"},{"mnemonic":"VMSLTU.VI","slug":"vmsltu_vi","records":1,"summary":"Sets mask if element < imm (Unsigned).","page":"https://instructionsets.com/risc-v/vmsltu_vi/","api":"https://instructionsets.com/api/v1/risc-v/vmsltu_vi.json"},{"mnemonic":"VMSLTU.VV","slug":"vmsltu_vv","records":1,"summary":"Sets destination mask bit if vs2 < vs1 (unsigned).","page":"https://instructionsets.com/risc-v/vmsltu_vv/","api":"https://instructionsets.com/api/v1/risc-v/vmsltu_vv.json"},{"mnemonic":"VMSNE.VI","slug":"vmsne_vi","records":1,"summary":"Sets mask if element != imm.","page":"https://instructionsets.com/risc-v/vmsne_vi/","api":"https://instructionsets.com/api/v1/risc-v/vmsne_vi.json"},{"mnemonic":"VMSOF.M","slug":"vmsof_m","records":1,"summary":"Sets only the first set bit from the source mask.","page":"https://instructionsets.com/risc-v/vmsof_m/","api":"https://instructionsets.com/api/v1/risc-v/vmsof_m.json"},{"mnemonic":"VMUL.VV","slug":"vmul_vv","records":1,"summary":"Multiplies elements of two vector registers.","page":"https://instructionsets.com/risc-v/vmul_vv/","api":"https://instructionsets.com/api/v1/risc-v/vmul_vv.json"},{"mnemonic":"VMULH.VV","slug":"vmulh_vv","records":1,"summary":"Multiplies signed integers and keeps the high N bits.","page":"https://instructionsets.com/risc-v/vmulh_vv/","api":"https://instructionsets.com/api/v1/risc-v/vmulh_vv.json"},{"mnemonic":"VMULHU.VV","slug":"vmulhu_vv","records":1,"summary":"Multiplies unsigned integers and keeps the high N bits.","page":"https://instructionsets.com/risc-v/vmulhu_vv/","api":"https://instructionsets.com/api/v1/risc-v/vmulhu_vv.json"},{"mnemonic":"VMV1R.V","slug":"vmv1r_v","records":1,"summary":"Moves a single vector register to another, ignoring VL and VTYPE (used for spilling).","page":"https://instructionsets.com/risc-v/vmv1r_v/","api":"https://instructionsets.com/api/v1/risc-v/vmv1r_v.json"},{"mnemonic":"VMV2R.V","slug":"vmv2r_v","records":1,"summary":"Moves 2 consecutive vector registers, ignoring VL and VTYPE.","page":"https://instructionsets.com/risc-v/vmv2r_v/","api":"https://instructionsets.com/api/v1/risc-v/vmv2r_v.json"},{"mnemonic":"VMV4R.V","slug":"vmv4r_v","records":1,"summary":"Moves 4 consecutive vector registers, ignoring VL and VTYPE.","page":"https://instructionsets.com/risc-v/vmv4r_v/","api":"https://instructionsets.com/api/v1/risc-v/vmv4r_v.json"},{"mnemonic":"VMV8R.V","slug":"vmv8r_v","records":1,"summary":"Moves 8 consecutive vector registers, ignoring VL and VTYPE.","page":"https://instructionsets.com/risc-v/vmv8r_v/","api":"https://instructionsets.com/api/v1/risc-v/vmv8r_v.json"},{"mnemonic":"VMV.S.X","slug":"vmv_s_x","records":1,"summary":"Copies an integer register to element 0 of a vector.","page":"https://instructionsets.com/risc-v/vmv_s_x/","api":"https://instructionsets.com/api/v1/risc-v/vmv_s_x.json"},{"mnemonic":"VMV.V.V","slug":"vmv_v_v","records":1,"summary":"Copies a vector register.","page":"https://instructionsets.com/risc-v/vmv_v_v/","api":"https://instructionsets.com/api/v1/risc-v/vmv_v_v.json"},{"mnemonic":"VMV.X.S","slug":"vmv_x_s","records":1,"summary":"Copies element 0 of a vector to an integer register.","page":"https://instructionsets.com/risc-v/vmv_x_s/","api":"https://instructionsets.com/api/v1/risc-v/vmv_x_s.json"},{"mnemonic":"VMXNOR.MM","slug":"vmxnor_mm","records":1,"summary":"Computes vd = ~(vs1 ^ vs2) (mask operation).","page":"https://instructionsets.com/risc-v/vmxnor_mm/","api":"https://instructionsets.com/api/v1/risc-v/vmxnor_mm.json"},{"mnemonic":"VNCLIP.WV","slug":"vnclip_wv","records":1,"summary":"Shifts elements right, rounds, and clips (saturates) the result to the destination width. Critical for Quantization.","page":"https://instructionsets.com/risc-v/vnclip_wv/","api":"https://instructionsets.com/api/v1/risc-v/vnclip_wv.json"},{"mnemonic":"VNCLIPU.WI","slug":"vnclipu_wi","records":1,"summary":"Shifts right (logical), rounds, and clips to unsigned destination. Used for pixel packing.","page":"https://instructionsets.com/risc-v/vnclipu_wi/","api":"https://instructionsets.com/api/v1/risc-v/vnclipu_wi.json"},{"mnemonic":"VNMSUB.VV","slug":"vnmsub_vv","records":1,"summary":"Computes vd = -(vd - (vs1 * vs2)).","page":"https://instructionsets.com/risc-v/vnmsub_vv/","api":"https://instructionsets.com/api/v1/risc-v/vnmsub_vv.json"},{"mnemonic":"VNSRA.WI","slug":"vnsra_wi","records":1,"summary":"Shifts wide elements right (arithmetic) by immediate and narrows.","page":"https://instructionsets.com/risc-v/vnsra_wi/","api":"https://instructionsets.com/api/v1/risc-v/vnsra_wi.json"},{"mnemonic":"VNSRA.WX","slug":"vnsra_wx","records":1,"summary":"Arithmetically shifts 2*N-bit elements right and narrows to N-bits.","page":"https://instructionsets.com/risc-v/vnsra_wx/","api":"https://instructionsets.com/api/v1/risc-v/vnsra_wx.json"},{"mnemonic":"VNSRL.WI","slug":"vnsrl_wi","records":1,"summary":"Shifts wide elements right by immediate and narrows.","page":"https://instructionsets.com/risc-v/vnsrl_wi/","api":"https://instructionsets.com/api/v1/risc-v/vnsrl_wi.json"},{"mnemonic":"VNSRL.WX","slug":"vnsrl_wx","records":1,"summary":"Shifts 2*N-bit elements right and narrows the result to N-bits.","page":"https://instructionsets.com/risc-v/vnsrl_wx/","api":"https://instructionsets.com/api/v1/risc-v/vnsrl_wx.json"},{"mnemonic":"VOR.VI","slug":"vor_vi","records":1,"summary":"Bitwise OR with immediate.","page":"https://instructionsets.com/risc-v/vor_vi/","api":"https://instructionsets.com/api/v1/risc-v/vor_vi.json"},{"mnemonic":"VOR.VV","slug":"vor_vv","records":1,"summary":"Performs bitwise OR on elements of two vectors.","page":"https://instructionsets.com/risc-v/vor_vv/","api":"https://instructionsets.com/api/v1/risc-v/vor_vv.json"},{"mnemonic":"VREDAND.VS","slug":"vredand_vs","records":1,"summary":"Reduces a vector to a scalar using bitwise AND.","page":"https://instructionsets.com/risc-v/vredand_vs/","api":"https://instructionsets.com/api/v1/risc-v/vredand_vs.json"},{"mnemonic":"VREDMAX.VS","slug":"vredmax_vs","records":1,"summary":"Reduces a vector to a scalar by finding the maximum signed element.","page":"https://instructionsets.com/risc-v/vredmax_vs/","api":"https://instructionsets.com/api/v1/risc-v/vredmax_vs.json"},{"mnemonic":"VREDMIN.VS","slug":"vredmin_vs","records":1,"summary":"Reduces a vector to a scalar by finding the minimum signed element.","page":"https://instructionsets.com/risc-v/vredmin_vs/","api":"https://instructionsets.com/api/v1/risc-v/vredmin_vs.json"},{"mnemonic":"VREDOR.VS","slug":"vredor_vs","records":1,"summary":"Reduces a vector to a scalar using bitwise OR.","page":"https://instructionsets.com/risc-v/vredor_vs/","api":"https://instructionsets.com/api/v1/risc-v/vredor_vs.json"},{"mnemonic":"VREDSUM.VS","slug":"vredsum_vs","records":1,"summary":"Reduces a vector to a scalar by summing all elements.","page":"https://instructionsets.com/risc-v/vredsum_vs/","api":"https://instructionsets.com/api/v1/risc-v/vredsum_vs.json"},{"mnemonic":"VREM.VV","slug":"vrem_vv","records":1,"summary":"Computes signed remainder.","page":"https://instructionsets.com/risc-v/vrem_vv/","api":"https://instructionsets.com/api/v1/risc-v/vrem_vv.json"},{"mnemonic":"VREMU.VV","slug":"vremu_vv","records":1,"summary":"Computes unsigned remainder.","page":"https://instructionsets.com/risc-v/vremu_vv/","api":"https://instructionsets.com/api/v1/risc-v/vremu_vv.json"},{"mnemonic":"VREV8.V","slug":"vrev8_v","records":1,"summary":"Reverses the order of bytes within each element (Endian swap).","page":"https://instructionsets.com/risc-v/vrev8_v/","api":"https://instructionsets.com/api/v1/risc-v/vrev8_v.json"},{"mnemonic":"VRGATHER.VI","slug":"vrgather_vi","records":1,"summary":"Gathers element at index 'imm' from vs2 (splat).","page":"https://instructionsets.com/risc-v/vrgather_vi/","api":"https://instructionsets.com/api/v1/risc-v/vrgather_vi.json"},{"mnemonic":"VRGATHER.VV","slug":"vrgather_vv","records":1,"summary":"Gathers elements from a vector register using indices from another vector register.","page":"https://instructionsets.com/risc-v/vrgather_vv/","api":"https://instructionsets.com/api/v1/risc-v/vrgather_vv.json"},{"mnemonic":"VROL.VV","slug":"vrol_vv","records":1,"summary":"Rotates bits in elements of vs2 left by amounts in vs1.","page":"https://instructionsets.com/risc-v/vrol_vv/","api":"https://instructionsets.com/api/v1/risc-v/vrol_vv.json"},{"mnemonic":"VROL.VX","slug":"vrol_vx","records":1,"summary":"Rotates bits in elements of vs2 left by scalar rs1.","page":"https://instructionsets.com/risc-v/vrol_vx/","api":"https://instructionsets.com/api/v1/risc-v/vrol_vx.json"},{"mnemonic":"VROR.VV","slug":"vror_vv","records":1,"summary":"Rotates bits in elements of vs2 right by amounts in vs1.","page":"https://instructionsets.com/risc-v/vror_vv/","api":"https://instructionsets.com/api/v1/risc-v/vror_vv.json"},{"mnemonic":"VROR.VX","slug":"vror_vx","records":1,"summary":"Rotates bits in elements of vs2 right by scalar rs1.","page":"https://instructionsets.com/risc-v/vror_vx/","api":"https://instructionsets.com/api/v1/risc-v/vror_vx.json"},{"mnemonic":"VRSUB.VI","slug":"vrsub_vi","records":1,"summary":"Computes vd = imm - vs2.","page":"https://instructionsets.com/risc-v/vrsub_vi/","api":"https://instructionsets.com/api/v1/risc-v/vrsub_vi.json"},{"mnemonic":"VRSUB.VX","slug":"vrsub_vx","records":1,"summary":"Subtracts vector elements from a scalar value (scalar - vector).","page":"https://instructionsets.com/risc-v/vrsub_vx/","api":"https://instructionsets.com/api/v1/risc-v/vrsub_vx.json"},{"mnemonic":"VSADD.VV","slug":"vsadd_vv","records":1,"summary":"Adds elements with signed saturation (clips to Max/Min instead of wrapping).","page":"https://instructionsets.com/risc-v/vsadd_vv/","api":"https://instructionsets.com/api/v1/risc-v/vsadd_vv.json"},{"mnemonic":"VSADDU.VV","slug":"vsaddu_vv","records":1,"summary":"Adds unsigned integers with saturation (clips to max instead of wrapping).","page":"https://instructionsets.com/risc-v/vsaddu_vv/","api":"https://instructionsets.com/api/v1/risc-v/vsaddu_vv.json"},{"mnemonic":"VSBC.VVM","slug":"vsbc_vvm","records":1,"summary":"Subtracts two vectors minus a borrow-in from the mask register.","page":"https://instructionsets.com/risc-v/vsbc_vvm/","api":"https://instructionsets.com/api/v1/risc-v/vsbc_vvm.json"},{"mnemonic":"VSE16.V","slug":"vse16_v","records":1,"summary":"Stores a vector of 16-bit elements to memory.","page":"https://instructionsets.com/risc-v/vse16_v/","api":"https://instructionsets.com/api/v1/risc-v/vse16_v.json"},{"mnemonic":"VSE32.V","slug":"vse32_v","records":1,"summary":"Stores a vector of 32-bit elements from a vector register to memory.","page":"https://instructionsets.com/risc-v/vse32_v/","api":"https://instructionsets.com/api/v1/risc-v/vse32_v.json"},{"mnemonic":"VSE64.V","slug":"vse64_v","records":1,"summary":"Stores a vector of 64-bit elements to memory.","page":"https://instructionsets.com/risc-v/vse64_v/","api":"https://instructionsets.com/api/v1/risc-v/vse64_v.json"},{"mnemonic":"VSE8.V","slug":"vse8_v","records":1,"summary":"Stores a vector of 8-bit elements to memory.","page":"https://instructionsets.com/risc-v/vse8_v/","api":"https://instructionsets.com/api/v1/risc-v/vse8_v.json"},{"mnemonic":"VSETIVLI","slug":"vsetivli","records":1,"summary":"Sets vector length (VL) and type (VTYPE) using a 5-bit immediate for the requested length.","page":"https://instructionsets.com/risc-v/vsetivli/","api":"https://instructionsets.com/api/v1/risc-v/vsetivli.json"},{"mnemonic":"VSETVL","slug":"vsetvl","records":1,"summary":"Sets the vector length (VL) based on the application vector length (AVL) in rs1 and configuration in rs2.","page":"https://instructionsets.com/risc-v/vsetvl/","api":"https://instructionsets.com/api/v1/risc-v/vsetvl.json"},{"mnemonic":"VSETVLI","slug":"vsetvli","records":1,"summary":"Configures the vector length (vl) and vector type (vtype) based on application needs.","page":"https://instructionsets.com/risc-v/vsetvli/","api":"https://instructionsets.com/api/v1/risc-v/vsetvli.json"},{"mnemonic":"VSHA2CH.VV","slug":"vsha2ch_vv","records":1,"summary":"Performs SHA-256 compression (high 128 bits).","page":"https://instructionsets.com/risc-v/vsha2ch_vv/","api":"https://instructionsets.com/api/v1/risc-v/vsha2ch_vv.json"},{"mnemonic":"VSHA2CL.VV","slug":"vsha2cl_vv","records":1,"summary":"Performs SHA-256 compression (low 128 bits).","page":"https://instructionsets.com/risc-v/vsha2cl_vv/","api":"https://instructionsets.com/api/v1/risc-v/vsha2cl_vv.json"},{"mnemonic":"VSHA2MS.VV","slug":"vsha2ms_vv","records":1,"summary":"Generates SHA-256 message schedule words.","page":"https://instructionsets.com/risc-v/vsha2ms_vv/","api":"https://instructionsets.com/api/v1/risc-v/vsha2ms_vv.json"},{"mnemonic":"VSLIDE1DOWN.VX","slug":"vslide1down_vx","records":1,"summary":"Moves elements down by 1, injecting scalar into top index.","page":"https://instructionsets.com/risc-v/vslide1down_vx/","api":"https://instructionsets.com/api/v1/risc-v/vslide1down_vx.json"},{"mnemonic":"VSLIDE1UP.VX","slug":"vslide1up_vx","records":1,"summary":"Moves elements up by 1, injecting scalar into index 0.","page":"https://instructionsets.com/risc-v/vslide1up_vx/","api":"https://instructionsets.com/api/v1/risc-v/vslide1up_vx.json"},{"mnemonic":"VSLIDEDOWN.VI","slug":"vslidedown_vi","records":1,"summary":"Moves elements down by immediate amount.","page":"https://instructionsets.com/risc-v/vslidedown_vi/","api":"https://instructionsets.com/api/v1/risc-v/vslidedown_vi.json"},{"mnemonic":"VSLIDEDOWN.VX","slug":"vslidedown_vx","records":1,"summary":"Moves elements down by a scalar amount (vd[i] = vs2[i + rs1]).","page":"https://instructionsets.com/risc-v/vslidedown_vx/","api":"https://instructionsets.com/api/v1/risc-v/vslidedown_vx.json"},{"mnemonic":"VSLIDEUP.VI","slug":"vslideup_vi","records":1,"summary":"Moves elements up by immediate amount.","page":"https://instructionsets.com/risc-v/vslideup_vi/","api":"https://instructionsets.com/api/v1/risc-v/vslideup_vi.json"},{"mnemonic":"VSLIDEUP.VX","slug":"vslideup_vx","records":1,"summary":"Moves elements up by a scalar amount (vd[i] = vs2[i - rs1]).","page":"https://instructionsets.com/risc-v/vslideup_vx/","api":"https://instructionsets.com/api/v1/risc-v/vslideup_vx.json"},{"mnemonic":"VSLL.VI","slug":"vsll_vi","records":1,"summary":"Shifts elements left by immediate.","page":"https://instructionsets.com/risc-v/vsll_vi/","api":"https://instructionsets.com/api/v1/risc-v/vsll_vi.json"},{"mnemonic":"VSLL.VV","slug":"vsll_vv","records":1,"summary":"Shifts elements of vector vs2 left by amounts in vs1.","page":"https://instructionsets.com/risc-v/vsll_vv/","api":"https://instructionsets.com/api/v1/risc-v/vsll_vv.json"},{"mnemonic":"VSM.V","slug":"vsm_v","records":1,"summary":"Stores a vector mask register to memory.","page":"https://instructionsets.com/risc-v/vsm_v/","api":"https://instructionsets.com/api/v1/risc-v/vsm_v.json"},{"mnemonic":"VSMUL.VV","slug":"vsmul_vv","records":1,"summary":"Performs signed saturating multiplication, keeping the high half of the product (Fixed-point support).","page":"https://instructionsets.com/risc-v/vsmul_vv/","api":"https://instructionsets.com/api/v1/risc-v/vsmul_vv.json"},{"mnemonic":"VSOXEI32.V","slug":"vsoxei32_v","records":1,"summary":"Stores elements using indices, ensuring order.","page":"https://instructionsets.com/risc-v/vsoxei32_v/","api":"https://instructionsets.com/api/v1/risc-v/vsoxei32_v.json"},{"mnemonic":"VSRA.VI","slug":"vsra_vi","records":1,"summary":"Shifts elements right (arithmetic) by immediate.","page":"https://instructionsets.com/risc-v/vsra_vi/","api":"https://instructionsets.com/api/v1/risc-v/vsra_vi.json"},{"mnemonic":"VSRA.VV","slug":"vsra_vv","records":1,"summary":"Shifts elements of vector vs2 right (arithmetic) by amounts in vs1.","page":"https://instructionsets.com/risc-v/vsra_vv/","api":"https://instructionsets.com/api/v1/risc-v/vsra_vv.json"},{"mnemonic":"VSRL.VI","slug":"vsrl_vi","records":1,"summary":"Shifts elements right (logical) by immediate.","page":"https://instructionsets.com/risc-v/vsrl_vi/","api":"https://instructionsets.com/api/v1/risc-v/vsrl_vi.json"},{"mnemonic":"VSRL.VV","slug":"vsrl_vv","records":1,"summary":"Shifts elements of vector vs2 right (logical) by amounts in vs1.","page":"https://instructionsets.com/risc-v/vsrl_vv/","api":"https://instructionsets.com/api/v1/risc-v/vsrl_vv.json"},{"mnemonic":"VSSE32.V","slug":"vsse32_v","records":1,"summary":"Stores elements to memory with a fixed stride.","page":"https://instructionsets.com/risc-v/vsse32_v/","api":"https://instructionsets.com/api/v1/risc-v/vsse32_v.json"},{"mnemonic":"VSSEG2E16.V","slug":"vsseg2e16_v","records":1,"summary":"Stores 2 vector registers as interleaved 16-bit fields.","page":"https://instructionsets.com/risc-v/vsseg2e16_v/","api":"https://instructionsets.com/api/v1/risc-v/vsseg2e16_v.json"},{"mnemonic":"VSSEG3E8.V","slug":"vsseg3e8_v","records":1,"summary":"Stores 3 vector registers (e.g., RGB) into memory as interleaved 8-bit fields.","page":"https://instructionsets.com/risc-v/vsseg3e8_v/","api":"https://instructionsets.com/api/v1/risc-v/vsseg3e8_v.json"},{"mnemonic":"VSSEG4E8.V","slug":"vsseg4e8_v","records":1,"summary":"Stores 4 vector registers (e.g., RGBA) into memory as interleaved 8-bit fields.","page":"https://instructionsets.com/risc-v/vsseg4e8_v/","api":"https://instructionsets.com/api/v1/risc-v/vsseg4e8_v.json"},{"mnemonic":"VSSRA.VV","slug":"vssra_vv","records":1,"summary":"Shifts right with sign extension and rounding/saturation logic.","page":"https://instructionsets.com/risc-v/vssra_vv/","api":"https://instructionsets.com/api/v1/risc-v/vssra_vv.json"},{"mnemonic":"VSSRL.VV","slug":"vssrl_vv","records":1,"summary":"Shifts right with zero extension and rounding/saturation logic.","page":"https://instructionsets.com/risc-v/vssrl_vv/","api":"https://instructionsets.com/api/v1/risc-v/vssrl_vv.json"},{"mnemonic":"VSSUB.VV","slug":"vssub_vv","records":1,"summary":"Subtracts elements with signed saturation.","page":"https://instructionsets.com/risc-v/vssub_vv/","api":"https://instructionsets.com/api/v1/risc-v/vssub_vv.json"},{"mnemonic":"VSSUBU.VV","slug":"vssubu_vv","records":1,"summary":"Subtracts unsigned integers with saturation (clips to 0 instead of wrapping).","page":"https://instructionsets.com/risc-v/vssubu_vv/","api":"https://instructionsets.com/api/v1/risc-v/vssubu_vv.json"},{"mnemonic":"VSUB.VV","slug":"vsub_vv","records":1,"summary":"Subtracts elements of two vector registers.","page":"https://instructionsets.com/risc-v/vsub_vv/","api":"https://instructionsets.com/api/v1/risc-v/vsub_vv.json"},{"mnemonic":"VSUXEI32.V","slug":"vsuxei32_v","records":1,"summary":"Stores elements to memory using a vector of indices (Scatter).","page":"https://instructionsets.com/risc-v/vsuxei32_v/","api":"https://instructionsets.com/api/v1/risc-v/vsuxei32_v.json"},{"mnemonic":"VWADD.VV","slug":"vwadd_vv","records":1,"summary":"Adds N-bit elements to produce 2*N-bit results (Widening).","page":"https://instructionsets.com/risc-v/vwadd_vv/","api":"https://instructionsets.com/api/v1/risc-v/vwadd_vv.json"},{"mnemonic":"VWADDU.VV","slug":"vwaddu_vv","records":1,"summary":"Adds unsigned N-bit elements to produce unsigned 2*N-bit results.","page":"https://instructionsets.com/risc-v/vwaddu_vv/","api":"https://instructionsets.com/api/v1/risc-v/vwaddu_vv.json"},{"mnemonic":"VWMACC.VV","slug":"vwmacc_vv","records":1,"summary":"Computes vd = vd + (vs1 * vs2) with widening (N*N -> 2N + 2N).","page":"https://instructionsets.com/risc-v/vwmacc_vv/","api":"https://instructionsets.com/api/v1/risc-v/vwmacc_vv.json"},{"mnemonic":"VWMACCSU.VV","slug":"vwmaccsu_vv","records":1,"summary":"vd = vd + (signed(vs1) * unsigned(vs2)).","page":"https://instructionsets.com/risc-v/vwmaccsu_vv/","api":"https://instructionsets.com/api/v1/risc-v/vwmaccsu_vv.json"},{"mnemonic":"VWMACCU.VV","slug":"vwmaccu_vv","records":1,"summary":"Computes vd = vd + (vs1 * vs2) widening unsigned.","page":"https://instructionsets.com/risc-v/vwmaccu_vv/","api":"https://instructionsets.com/api/v1/risc-v/vwmaccu_vv.json"},{"mnemonic":"VWMACCUS.VX","slug":"vwmaccus_vx","records":1,"summary":"vd = vd + (unsigned(vs1) * signed(vs2)).","page":"https://instructionsets.com/risc-v/vwmaccus_vx/","api":"https://instructionsets.com/api/v1/risc-v/vwmaccus_vx.json"},{"mnemonic":"VWMUL.VV","slug":"vwmul_vv","records":1,"summary":"Multiplies N-bit elements to produce 2*N-bit results.","page":"https://instructionsets.com/risc-v/vwmul_vv/","api":"https://instructionsets.com/api/v1/risc-v/vwmul_vv.json"},{"mnemonic":"VWREDSUM.VS","slug":"vwredsum_vs","records":1,"summary":"Sums N-bit elements into a 2*N-bit scalar accumulator (Signed).","page":"https://instructionsets.com/risc-v/vwredsum_vs/","api":"https://instructionsets.com/api/v1/risc-v/vwredsum_vs.json"},{"mnemonic":"VWREDSUMU.VS","slug":"vwredsumu_vs","records":1,"summary":"Sums N-bit elements into a 2*N-bit scalar accumulator (Unsigned).","page":"https://instructionsets.com/risc-v/vwredsumu_vs/","api":"https://instructionsets.com/api/v1/risc-v/vwredsumu_vs.json"},{"mnemonic":"VWSLL.VI","slug":"vwsll_vi","records":1,"summary":"Shifts elements left by immediate, widening the result.","page":"https://instructionsets.com/risc-v/vwsll_vi/","api":"https://instructionsets.com/api/v1/risc-v/vwsll_vi.json"},{"mnemonic":"VWSLL.VV","slug":"vwsll_vv","records":1,"summary":"Shifts N-bit elements left to produce 2*N-bit results.","page":"https://instructionsets.com/risc-v/vwsll_vv/","api":"https://instructionsets.com/api/v1/risc-v/vwsll_vv.json"},{"mnemonic":"VWSLL.VX","slug":"vwsll_vx","records":1,"summary":"Shifts elements left by scalar rs1, widening the result.","page":"https://instructionsets.com/risc-v/vwsll_vx/","api":"https://instructionsets.com/api/v1/risc-v/vwsll_vx.json"},{"mnemonic":"VWSUB.VV","slug":"vwsub_vv","records":1,"summary":"Subtracts N-bit elements to produce 2*N-bit results.","page":"https://instructionsets.com/risc-v/vwsub_vv/","api":"https://instructionsets.com/api/v1/risc-v/vwsub_vv.json"},{"mnemonic":"VXOR.VI","slug":"vxor_vi","records":1,"summary":"Bitwise XOR with immediate.","page":"https://instructionsets.com/risc-v/vxor_vi/","api":"https://instructionsets.com/api/v1/risc-v/vxor_vi.json"},{"mnemonic":"VXOR.VV","slug":"vxor_vv","records":1,"summary":"Performs bitwise XOR on elements of two vectors.","page":"https://instructionsets.com/risc-v/vxor_vv/","api":"https://instructionsets.com/api/v1/risc-v/vxor_vv.json"},{"mnemonic":"WFI","slug":"wfi","records":1,"summary":"Provides a hint to the implementation that the current hart can be stalled until an interrupt occurs.","page":"https://instructionsets.com/risc-v/wfi/","api":"https://instructionsets.com/api/v1/risc-v/wfi.json"},{"mnemonic":"WRS.NTO","slug":"wrs_nto","records":1,"summary":"Stalls the hart until a reservation set is invalid or a short timeout expires. Used for efficient polling/spinlocks.","page":"https://instructionsets.com/risc-v/wrs_nto/","api":"https://instructionsets.com/api/v1/risc-v/wrs_nto.json"},{"mnemonic":"WRS.STO","slug":"wrs_sto","records":1,"summary":"Stalls the hart until a reservation set is invalid or a very short implementation-defined timeout expires.","page":"https://instructionsets.com/risc-v/wrs_sto/","api":"https://instructionsets.com/api/v1/risc-v/wrs_sto.json"},{"mnemonic":"XNOR","slug":"xnor","records":1,"summary":"Performs bitwise exclusive-NOR (rs1 ^ ~rs2).","page":"https://instructionsets.com/risc-v/xnor/","api":"https://instructionsets.com/api/v1/risc-v/xnor.json"},{"mnemonic":"XOR","slug":"xor","records":1,"summary":"Performs a bitwise logical Exclusive-OR operation.","page":"https://instructionsets.com/risc-v/xor/","api":"https://instructionsets.com/api/v1/risc-v/xor.json"},{"mnemonic":"XORI","slug":"xori","records":1,"summary":"Performs a bitwise logical Exclusive-OR with a sign-extended immediate.","page":"https://instructionsets.com/risc-v/xori/","api":"https://instructionsets.com/api/v1/risc-v/xori.json"},{"mnemonic":"ZEXT.H","slug":"zext_h","records":1,"summary":"Zero-extends the lowest halfword (16 bits) to XLEN bits.","page":"https://instructionsets.com/risc-v/zext_h/","api":"https://instructionsets.com/api/v1/risc-v/zext_h.json"}]}