{"api_version":"1","snapshot":"2026-10-08","licence":"CC0-1.0","architecture":"PowerISA","records":1187,"mnemonics":[{"mnemonic":"add","slug":"add","records":1,"summary":"Adds the contents of two registers and places the result in a third register.","page":"https://instructionsets.com/powerisa/add/","api":"https://instructionsets.com/api/v1/powerisa/add.json"},{"mnemonic":"add.","slug":"add_","records":1,"summary":"Adds the contents of two registers and updates the condition register.","page":"https://instructionsets.com/powerisa/add_/","api":"https://instructionsets.com/api/v1/powerisa/add_.json"},{"mnemonic":"addc","slug":"addc","records":1,"summary":"Adds the contents of two registers and a carry bit, placing the result in a target register.","page":"https://instructionsets.com/powerisa/addc/","api":"https://instructionsets.com/api/v1/powerisa/addc.json"},{"mnemonic":"addc.","slug":"addc_","records":1,"summary":"Adds the contents of two registers and a carry bit, placing the result in a target register.","page":"https://instructionsets.com/powerisa/addc_/","api":"https://instructionsets.com/api/v1/powerisa/addc_.json"},{"mnemonic":"addco","slug":"addco","records":1,"summary":"Adds the contents of two registers and a carry bit, placing the result in a target register.","page":"https://instructionsets.com/powerisa/addco/","api":"https://instructionsets.com/api/v1/powerisa/addco.json"},{"mnemonic":"addco.","slug":"addco_","records":1,"summary":"Adds the contents of two registers and a carry bit, placing the result in a target register.","page":"https://instructionsets.com/powerisa/addco_/","api":"https://instructionsets.com/api/v1/powerisa/addco_.json"},{"mnemonic":"adde","slug":"adde","records":1,"summary":"Adds two registers plus the current Carry bit.","page":"https://instructionsets.com/powerisa/adde/","api":"https://instructionsets.com/api/v1/powerisa/adde.json"},{"mnemonic":"addex","slug":"addex","records":1,"summary":"Adds the contents of two registers and an alternate carry bit, updating the condition register.","page":"https://instructionsets.com/powerisa/addex/","api":"https://instructionsets.com/api/v1/powerisa/addex.json"},{"mnemonic":"addg6s","slug":"addg6s","records":1,"summary":"Adds the contents of two registers and generates sixes based on carry bits.","page":"https://instructionsets.com/powerisa/addg6s/","api":"https://instructionsets.com/api/v1/powerisa/addg6s.json"},{"mnemonic":"addi","slug":"addi","records":1,"summary":"Adds a signed immediate value to the contents of a register and places the result in another register.","page":"https://instructionsets.com/powerisa/addi/","api":"https://instructionsets.com/api/v1/powerisa/addi.json"},{"mnemonic":"addic","slug":"addic","records":1,"summary":"Adds an immediate to a register and updates the Carry bit.","page":"https://instructionsets.com/powerisa/addic/","api":"https://instructionsets.com/api/v1/powerisa/addic.json"},{"mnemonic":"addic.","slug":"addic_","records":1,"summary":"Adds an immediate, updates Carry, and updates Condition Register Field 0 (CR0).","page":"https://instructionsets.com/powerisa/addic_/","api":"https://instructionsets.com/api/v1/powerisa/addic_.json"},{"mnemonic":"addis","slug":"addis","records":1,"summary":"Adds an immediate value shifted left by 16 bits to the contents of a register and places the result in another register.","page":"https://instructionsets.com/powerisa/addis/","api":"https://instructionsets.com/api/v1/powerisa/addis.json"},{"mnemonic":"addme","slug":"addme","records":1,"summary":"Adds the contents of a register and a constant minus one, with optional overflow exception.","page":"https://instructionsets.com/powerisa/addme/","api":"https://instructionsets.com/api/v1/powerisa/addme.json"},{"mnemonic":"addme.","slug":"addme_","records":1,"summary":"Adds the contents of two registers and subtracts one, then updates the condition register.","page":"https://instructionsets.com/powerisa/addme_/","api":"https://instructionsets.com/api/v1/powerisa/addme_.json"},{"mnemonic":"addmeo","slug":"addmeo","records":1,"summary":"Adds the contents of a register and a constant minus one, with optional overflow exception.","page":"https://instructionsets.com/powerisa/addmeo/","api":"https://instructionsets.com/api/v1/powerisa/addmeo.json"},{"mnemonic":"addmeo.","slug":"addmeo_","records":1,"summary":"Adds the contents of a register and a constant minus one, with optional overflow exception.","page":"https://instructionsets.com/powerisa/addmeo_/","api":"https://instructionsets.com/api/v1/powerisa/addmeo_.json"},{"mnemonic":"addze","slug":"addze","records":1,"summary":"Adds a register, 0, and the Carry bit.","page":"https://instructionsets.com/powerisa/addze/","api":"https://instructionsets.com/api/v1/powerisa/addze.json"},{"mnemonic":"and","slug":"and","records":1,"summary":"Performs a bitwise AND operation on the contents of two registers and places the result into another register.","page":"https://instructionsets.com/powerisa/and/","api":"https://instructionsets.com/api/v1/powerisa/and.json"},{"mnemonic":"and.","slug":"and_","records":1,"summary":"Performs a bitwise AND operation on the contents of two registers and places the result into another register.","page":"https://instructionsets.com/powerisa/and_/","api":"https://instructionsets.com/api/v1/powerisa/and_.json"},{"mnemonic":"andc","slug":"andc","records":1,"summary":"Performs a bitwise AND between RS and the one's complement of RB.","page":"https://instructionsets.com/powerisa/andc/","api":"https://instructionsets.com/api/v1/powerisa/andc.json"},{"mnemonic":"andi.","slug":"andi_","records":1,"summary":"Performs a bitwise AND operation between the contents of a register and an immediate value, and updates the condition register.","page":"https://instructionsets.com/powerisa/andi_/","api":"https://instructionsets.com/api/v1/powerisa/andi_.json"},{"mnemonic":"andis.","slug":"andis_","records":1,"summary":"Performs a bitwise AND between a register and a 16-bit immediate shifted left by 16 bits. Always updates CR0.","page":"https://instructionsets.com/powerisa/andis_/","api":"https://instructionsets.com/api/v1/powerisa/andis_.json"},{"mnemonic":"attn","slug":"attn","records":1,"summary":"Stops execution and alerts the hardware debugger.","page":"https://instructionsets.com/powerisa/attn/","api":"https://instructionsets.com/api/v1/powerisa/attn.json"},{"mnemonic":"b","slug":"b","records":1,"summary":"Unconditionally branches to a target address relative to the current instruction pointer.","page":"https://instructionsets.com/powerisa/b/","api":"https://instructionsets.com/api/v1/powerisa/b.json"},{"mnemonic":"ba","slug":"ba","records":1,"summary":"Unconditionally branches to an absolute address.","page":"https://instructionsets.com/powerisa/ba/","api":"https://instructionsets.com/api/v1/powerisa/ba.json"},{"mnemonic":"bc","slug":"bc","records":1,"summary":"Branches conditionally based on the Count Register (CTR) and/or a bit in the Condition Register (CR).","page":"https://instructionsets.com/powerisa/bc/","api":"https://instructionsets.com/api/v1/powerisa/bc.json"},{"mnemonic":"bca","slug":"bca","records":1,"summary":"Branches to the target address if the specified condition is met.","page":"https://instructionsets.com/powerisa/bca/","api":"https://instructionsets.com/api/v1/powerisa/bca.json"},{"mnemonic":"bcctr","slug":"bcctr","records":1,"summary":"Branches to the address in the Count Register (CTR) if the condition is met. Used for computed jumps and switch statements.","page":"https://instructionsets.com/powerisa/bcctr/","api":"https://instructionsets.com/api/v1/powerisa/bcctr.json"},{"mnemonic":"bcdadd.","slug":"bcdadd_","records":1,"summary":"Adds two packed decimal integers and updates the condition register.","page":"https://instructionsets.com/powerisa/bcdadd_/","api":"https://instructionsets.com/api/v1/powerisa/bcdadd_.json"},{"mnemonic":"bcdcfn.","slug":"bcdcfn_","records":1,"summary":"Converts a national decimal value to packed decimal format and stores it in the target vector register.","page":"https://instructionsets.com/powerisa/bcdcfn_/","api":"https://instructionsets.com/api/v1/powerisa/bcdcfn_.json"},{"mnemonic":"bcdcfsq.","slug":"bcdcfsq_","records":1,"summary":"Converts a signed quadword integer to packed decimal format and updates the condition register.","page":"https://instructionsets.com/powerisa/bcdcfsq_/","api":"https://instructionsets.com/api/v1/powerisa/bcdcfsq_.json"},{"mnemonic":"bcdcfz.","slug":"bcdcfz_","records":1,"summary":"Converts BCD Zoned format to Signed Packed BCD.","page":"https://instructionsets.com/powerisa/bcdcfz_/","api":"https://instructionsets.com/api/v1/powerisa/bcdcfz_.json"},{"mnemonic":"bcdcpsgn.","slug":"bcdcpsgn_","records":1,"summary":"Copies the sign of a decimal value from one register to another while preserving the magnitude.","page":"https://instructionsets.com/powerisa/bcdcpsgn_/","api":"https://instructionsets.com/api/v1/powerisa/bcdcpsgn_.json"},{"mnemonic":"bcdctn.","slug":"bcdctn_","records":1,"summary":"Converts a packed decimal value to national decimal format and stores it in a vector register.","page":"https://instructionsets.com/powerisa/bcdctn_/","api":"https://instructionsets.com/api/v1/powerisa/bcdctn_.json"},{"mnemonic":"bcdctsq.","slug":"bcdctsq_","records":1,"summary":"Compares two binary coded decimal (BCD) numbers in a quadword format and tests the sign.","page":"https://instructionsets.com/powerisa/bcdctsq_/","api":"https://instructionsets.com/api/v1/powerisa/bcdctsq_.json"},{"mnemonic":"bcdctz.","slug":"bcdctz_","records":1,"summary":"Converts Signed Packed BCD to Zoned format.","page":"https://instructionsets.com/powerisa/bcdctz_/","api":"https://instructionsets.com/api/v1/powerisa/bcdctz_.json"},{"mnemonic":"bcds.","slug":"bcds_","records":1,"summary":"Shifts a signed packed decimal value by a specified number of digits and rounds the result.","page":"https://instructionsets.com/powerisa/bcds_/","api":"https://instructionsets.com/api/v1/powerisa/bcds_.json"},{"mnemonic":"bcdsetsgn.","slug":"bcdsetsgn_","records":1,"summary":"Sets the sign of a packed decimal value in a vector register based on the specified conditions.","page":"https://instructionsets.com/powerisa/bcdsetsgn_/","api":"https://instructionsets.com/api/v1/powerisa/bcdsetsgn_.json"},{"mnemonic":"bcdsr.","slug":"bcdsr_","records":1,"summary":"Shifts a binary coded decimal value by a specified number of digits and rounds the result.","page":"https://instructionsets.com/powerisa/bcdsr_/","api":"https://instructionsets.com/api/v1/powerisa/bcdsr_.json"},{"mnemonic":"bcdtrunc.","slug":"bcdtrunc_","records":1,"summary":"Truncates a decimal value to a specified length and updates the condition register.","page":"https://instructionsets.com/powerisa/bcdtrunc_/","api":"https://instructionsets.com/api/v1/powerisa/bcdtrunc_.json"},{"mnemonic":"bcdus.","slug":"bcdus_","records":1,"summary":"Performs an unsigned shift on packed decimal values in vector registers.","page":"https://instructionsets.com/powerisa/bcdus_/","api":"https://instructionsets.com/api/v1/powerisa/bcdus_.json"},{"mnemonic":"bcdutrunc.","slug":"bcdutrunc_","records":1,"summary":"Truncates the unsigned decimal value in VRB to a specified length and places it into VRT.","page":"https://instructionsets.com/powerisa/bcdutrunc_/","api":"https://instructionsets.com/api/v1/powerisa/bcdutrunc_.json"},{"mnemonic":"bcl","slug":"bcl","records":1,"summary":"Branches to the target address if the specified condition is met.","page":"https://instructionsets.com/powerisa/bcl/","api":"https://instructionsets.com/api/v1/powerisa/bcl.json"},{"mnemonic":"bcla","slug":"bcla","records":1,"summary":"Branches to the target address if the specified condition is met.","page":"https://instructionsets.com/powerisa/bcla/","api":"https://instructionsets.com/api/v1/powerisa/bcla.json"},{"mnemonic":"bclr","slug":"bclr","records":1,"summary":"Branches to the address in the Link Register (LR) if the condition is met. Used for function returns.","page":"https://instructionsets.com/powerisa/bclr/","api":"https://instructionsets.com/api/v1/powerisa/bclr.json"},{"mnemonic":"bclrl","slug":"bclrl","records":1,"summary":"Branches to the address in the Link Register if the specified condition is met, and sets the Link Register to the return address.","page":"https://instructionsets.com/powerisa/bclrl/","api":"https://instructionsets.com/api/v1/powerisa/bclrl.json"},{"mnemonic":"bctar","slug":"bctar","records":1,"summary":"Conditional branch based on the contents of the Condition Register and the Count Register.","page":"https://instructionsets.com/powerisa/bctar/","api":"https://instructionsets.com/api/v1/powerisa/bctar.json"},{"mnemonic":"bl","slug":"bl","records":1,"summary":"Branches to a target address and saves the return address (CIA + 4) in the Link Register (LR). Used for function calls.","page":"https://instructionsets.com/powerisa/bl/","api":"https://instructionsets.com/api/v1/powerisa/bl.json"},{"mnemonic":"bla","slug":"bla","records":1,"summary":"Branches to the target address and sets the Link Register to the return address.","page":"https://instructionsets.com/powerisa/bla/","api":"https://instructionsets.com/api/v1/powerisa/bla.json"},{"mnemonic":"blt","slug":"blt","records":1,"summary":"Branches to a target address if the condition 'less than' is true.","page":"https://instructionsets.com/powerisa/blt/","api":"https://instructionsets.com/api/v1/powerisa/blt.json"},{"mnemonic":"blt+","slug":"blt+","records":1,"summary":"Branches to the target address if CR0 reflects condition 'less than', predicting the branch will be taken.","page":"https://instructionsets.com/powerisa/blt+/","api":"https://instructionsets.com/api/v1/powerisa/blt+.json"},{"mnemonic":"bpermd","slug":"bpermd","records":1,"summary":"Permutes bits from RS based on the index values in RB. Highly optimized for bit shuffling.","page":"https://instructionsets.com/powerisa/bpermd/","api":"https://instructionsets.com/api/v1/powerisa/bpermd.json"},{"mnemonic":"brd","slug":"brd","records":1,"summary":"Reverses the bytes in a doubleword.","page":"https://instructionsets.com/powerisa/brd/","api":"https://instructionsets.com/api/v1/powerisa/brd.json"},{"mnemonic":"brh","slug":"brh","records":1,"summary":"Reverses the byte order of a halfword in a register.","page":"https://instructionsets.com/powerisa/brh/","api":"https://instructionsets.com/api/v1/powerisa/brh.json"},{"mnemonic":"cfuged","slug":"cfuged","records":1,"summary":"Separates bits of the source register into two groups based on a mask (Power10 Scalar).","page":"https://instructionsets.com/powerisa/cfuged/","api":"https://instructionsets.com/api/v1/powerisa/cfuged.json"},{"mnemonic":"clrbhrb","slug":"clrbhrb","records":1,"summary":"Clear Branch History Rolling Buffer. Clears all entries in the Branch History Rolling Buffer (BHRB) to zero. Used to flush branch prediction history, for example when switching execution contexts to prevent information leakage between security domains.","page":"https://instructionsets.com/powerisa/clrbhrb/","api":"https://instructionsets.com/api/v1/powerisa/clrbhrb.json"},{"mnemonic":"cmp","slug":"cmp","records":1,"summary":"Compares two registers as signed integers and records the result in the specified Condition Register Field.","page":"https://instructionsets.com/powerisa/cmp/","api":"https://instructionsets.com/api/v1/powerisa/cmp.json"},{"mnemonic":"cmpb","slug":"cmpb","records":1,"summary":"Compares bytes in two GPRs, result is byte mask.","page":"https://instructionsets.com/powerisa/cmpb/","api":"https://instructionsets.com/api/v1/powerisa/cmpb.json"},{"mnemonic":"cmpdi","slug":"cmpdi","records":1,"summary":"Compares a doubleword immediate value with the contents of a register and updates the condition register.","page":"https://instructionsets.com/powerisa/cmpdi/","api":"https://instructionsets.com/api/v1/powerisa/cmpdi.json"},{"mnemonic":"cmpeqb","slug":"cmpeqb","records":1,"summary":"Compares the contents of bits 56:63 of register RA with each byte in register RB and sets the condition register field BF.","page":"https://instructionsets.com/powerisa/cmpeqb/","api":"https://instructionsets.com/api/v1/powerisa/cmpeqb.json"},{"mnemonic":"cmpi","slug":"cmpi","records":1,"summary":"Compares the contents of register RA with a sign-extended immediate value.","page":"https://instructionsets.com/powerisa/cmpi/","api":"https://instructionsets.com/api/v1/powerisa/cmpi.json"},{"mnemonic":"cmpl","slug":"cmpl","records":1,"summary":"Compares two registers as unsigned integers.","page":"https://instructionsets.com/powerisa/cmpl/","api":"https://instructionsets.com/api/v1/powerisa/cmpl.json"},{"mnemonic":"cmpli","slug":"cmpli","records":1,"summary":"Compares the contents of a register with an immediate value and updates the condition register.","page":"https://instructionsets.com/powerisa/cmpli/","api":"https://instructionsets.com/api/v1/powerisa/cmpli.json"},{"mnemonic":"cmprb","slug":"cmprb","records":1,"summary":"Compares a byte value in one register to see if it falls within a range defined by another register.","page":"https://instructionsets.com/powerisa/cmprb/","api":"https://instructionsets.com/api/v1/powerisa/cmprb.json"},{"mnemonic":"cntlzd","slug":"cntlzd","records":1,"summary":"Counts the number of consecutive 0 bits starting from bit 0 (MSB of 64-bit reg).","page":"https://instructionsets.com/powerisa/cntlzd/","api":"https://instructionsets.com/api/v1/powerisa/cntlzd.json"},{"mnemonic":"cntlzd.","slug":"cntlzd_","records":1,"summary":"Counts the number of consecutive 0 bits starting from bit 0 (MSB of 64-bit reg).","page":"https://instructionsets.com/powerisa/cntlzd_/","api":"https://instructionsets.com/api/v1/powerisa/cntlzd_.json"},{"mnemonic":"cntlzdm","slug":"cntlzdm","records":1,"summary":"Counts leading zeros in RS, but only considering bits set in mask RB.","page":"https://instructionsets.com/powerisa/cntlzdm/","api":"https://instructionsets.com/api/v1/powerisa/cntlzdm.json"},{"mnemonic":"cntlzw","slug":"cntlzw","records":1,"summary":"Counts the number of consecutive 0 bits starting from bit 32 (MSB of the low word).","page":"https://instructionsets.com/powerisa/cntlzw/","api":"https://instructionsets.com/api/v1/powerisa/cntlzw.json"},{"mnemonic":"cnttzd","slug":"cnttzd","records":1,"summary":"Counts the number of trailing zeros in 64-bits.","page":"https://instructionsets.com/powerisa/cnttzd/","api":"https://instructionsets.com/api/v1/powerisa/cnttzd.json"},{"mnemonic":"cnttzdm","slug":"cnttzdm","records":1,"summary":"Counts trailing zeros in RS, but only considering bits set in mask RB.","page":"https://instructionsets.com/powerisa/cnttzdm/","api":"https://instructionsets.com/api/v1/powerisa/cnttzdm.json"},{"mnemonic":"cnttzw","slug":"cnttzw","records":1,"summary":"Counts the number of trailing zeros in the low 32-bits.","page":"https://instructionsets.com/powerisa/cnttzw/","api":"https://instructionsets.com/api/v1/powerisa/cnttzw.json"},{"mnemonic":"copy","slug":"copy","records":1,"summary":"Initiates a hardware copy (accelerator) operation.","page":"https://instructionsets.com/powerisa/copy/","api":"https://instructionsets.com/api/v1/powerisa/copy.json"},{"mnemonic":"cp_abort","slug":"cp_abort","records":1,"summary":"Aborts a hardware accelerator copy-paste sequence.","page":"https://instructionsets.com/powerisa/cp_abort/","api":"https://instructionsets.com/api/v1/powerisa/cp_abort.json"},{"mnemonic":"cpabort","slug":"cpabort","records":1,"summary":"Aborts any in-progress copy-paste operation, discarding any pending copy target set by a previous Copy instruction.","page":"https://instructionsets.com/powerisa/cpabort/","api":"https://instructionsets.com/api/v1/powerisa/cpabort.json"},{"mnemonic":"crand","slug":"crand","records":1,"summary":"Performs a bitwise AND between two bits in the Condition Register.","page":"https://instructionsets.com/powerisa/crand/","api":"https://instructionsets.com/api/v1/powerisa/crand.json"},{"mnemonic":"crc32b","slug":"crc32b","records":1,"summary":"Accumulates a CRC32 checksum using the low byte of RS.","page":"https://instructionsets.com/powerisa/crc32b/","api":"https://instructionsets.com/api/v1/powerisa/crc32b.json"},{"mnemonic":"crc32d","slug":"crc32d","records":1,"summary":"Accumulates a CRC32 checksum using the doubleword in RS.","page":"https://instructionsets.com/powerisa/crc32d/","api":"https://instructionsets.com/api/v1/powerisa/crc32d.json"},{"mnemonic":"crc32h","slug":"crc32h","records":1,"summary":"Accumulates a CRC32 checksum using the low halfword of RS.","page":"https://instructionsets.com/powerisa/crc32h/","api":"https://instructionsets.com/api/v1/powerisa/crc32h.json"},{"mnemonic":"crc32w","slug":"crc32w","records":1,"summary":"Accumulates a CRC32 checksum using the word in RS.","page":"https://instructionsets.com/powerisa/crc32w/","api":"https://instructionsets.com/api/v1/powerisa/crc32w.json"},{"mnemonic":"creqv","slug":"creqv","records":1,"summary":"Sets the condition register field to 1 if the corresponding fields of two source registers are equal, otherwise sets it to 0.","page":"https://instructionsets.com/powerisa/creqv/","api":"https://instructionsets.com/api/v1/powerisa/creqv.json"},{"mnemonic":"crnor","slug":"crnor","records":1,"summary":"Performs a bitwise NOR operation on the specified bits of the Condition Registers and stores the result in another bit of the Condition Register.","page":"https://instructionsets.com/powerisa/crnor/","api":"https://instructionsets.com/api/v1/powerisa/crnor.json"},{"mnemonic":"cror","slug":"cror","records":1,"summary":"Performs a bitwise OR between two bits in the Condition Register.","page":"https://instructionsets.com/powerisa/cror/","api":"https://instructionsets.com/api/v1/powerisa/cror.json"},{"mnemonic":"crxor","slug":"crxor","records":1,"summary":"Performs a bitwise XOR between two bits in the Condition Register. Used to clear CR bits (crxor x,x,x).","page":"https://instructionsets.com/powerisa/crxor/","api":"https://instructionsets.com/api/v1/powerisa/crxor.json"},{"mnemonic":"ctfix","slug":"ctfix","records":1,"summary":"Converts a decimal floating-point value to a fixed-point integer.","page":"https://instructionsets.com/powerisa/ctfix/","api":"https://instructionsets.com/api/v1/powerisa/ctfix.json"},{"mnemonic":"dadd","slug":"dadd","records":1,"summary":"Adds two 64-bit Decimal Floating Point (DFP) numbers. Used in financial calculations to avoid rounding errors.","page":"https://instructionsets.com/powerisa/dadd/","api":"https://instructionsets.com/api/v1/powerisa/dadd.json"},{"mnemonic":"dadd.","slug":"dadd_","records":1,"summary":"Adds the contents of two double precision floating-point registers and updates the condition register.","page":"https://instructionsets.com/powerisa/dadd_/","api":"https://instructionsets.com/api/v1/powerisa/dadd_.json"},{"mnemonic":"daddq","slug":"daddq","records":1,"summary":"Adds two 128-bit DFP numbers.","page":"https://instructionsets.com/powerisa/daddq/","api":"https://instructionsets.com/api/v1/powerisa/daddq.json"},{"mnemonic":"darn","slug":"darn","records":1,"summary":"Returns a random number from the hardware RNG. (L=3: Raw, L=1: Conditioned, L=0: 32-bit).","page":"https://instructionsets.com/powerisa/darn/","api":"https://instructionsets.com/api/v1/powerisa/darn.json"},{"mnemonic":"dcba","slug":"dcba","records":1,"summary":"Allocates a cache block without loading from memory (optimization for overwrite).","page":"https://instructionsets.com/powerisa/dcba/","api":"https://instructionsets.com/api/v1/powerisa/dcba.json"},{"mnemonic":"dcbf","slug":"dcbf","records":1,"summary":"Flushes the cache block from the data cache to main memory and invalidates it. Used for DMA coherency.","page":"https://instructionsets.com/powerisa/dcbf/","api":"https://instructionsets.com/api/v1/powerisa/dcbf.json"},{"mnemonic":"dcbi","slug":"dcbi","records":1,"summary":"Invalidates a cache block (Privileged).","page":"https://instructionsets.com/powerisa/dcbi/","api":"https://instructionsets.com/api/v1/powerisa/dcbi.json"},{"mnemonic":"dcblc","slug":"dcblc","records":1,"summary":"Clears a cache line lock.","page":"https://instructionsets.com/powerisa/dcblc/","api":"https://instructionsets.com/api/v1/powerisa/dcblc.json"},{"mnemonic":"dcbst","slug":"dcbst","records":1,"summary":"Writes the cache block to main memory if it is modified (Clean), but keeps it in the cache.","page":"https://instructionsets.com/powerisa/dcbst/","api":"https://instructionsets.com/api/v1/powerisa/dcbst.json"},{"mnemonic":"dcbt","slug":"dcbt","records":1,"summary":"Hints to the hardware to prefetch the cache block at the specified address into the cache.","page":"https://instructionsets.com/powerisa/dcbt/","api":"https://instructionsets.com/api/v1/powerisa/dcbt.json"},{"mnemonic":"dcbtls","slug":"dcbtls","records":1,"summary":"Locks a cache line in the L1 cache.","page":"https://instructionsets.com/powerisa/dcbtls/","api":"https://instructionsets.com/api/v1/powerisa/dcbtls.json"},{"mnemonic":"dcbtst","slug":"dcbtst","records":1,"summary":"Provides a hint that describes a block or data stream to which the program may perform a store access.","page":"https://instructionsets.com/powerisa/dcbtst/","api":"https://instructionsets.com/api/v1/powerisa/dcbtst.json"},{"mnemonic":"dcbz","slug":"dcbz","records":1,"summary":"Zeros out an entire cache block (usually 128 bytes) in memory. Critical for optimizing memory clears (memset).","page":"https://instructionsets.com/powerisa/dcbz/","api":"https://instructionsets.com/api/v1/powerisa/dcbz.json"},{"mnemonic":"dcbzl","slug":"dcbzl","records":1,"summary":"Zeros a cache block (implementation defined size).","page":"https://instructionsets.com/powerisa/dcbzl/","api":"https://instructionsets.com/api/v1/powerisa/dcbzl.json"},{"mnemonic":"dccci","slug":"dccci","records":1,"summary":"Invalidates a congruence class in the data cache (Embedded).","page":"https://instructionsets.com/powerisa/dccci/","api":"https://instructionsets.com/api/v1/powerisa/dccci.json"},{"mnemonic":"dcffix","slug":"dcffix","records":1,"summary":"Converts a 64-bit integer to DFP.","page":"https://instructionsets.com/powerisa/dcffix/","api":"https://instructionsets.com/api/v1/powerisa/dcffix.json"},{"mnemonic":"dcffixq","slug":"dcffixq","records":1,"summary":"Converts 64-bit integer to 128-bit DFP.","page":"https://instructionsets.com/powerisa/dcffixq/","api":"https://instructionsets.com/api/v1/powerisa/dcffixq.json"},{"mnemonic":"dcffixqq","slug":"dcffixqq","records":1,"summary":"Converts a double-precision floating-point value to a quadword integer.","page":"https://instructionsets.com/powerisa/dcffixqq/","api":"https://instructionsets.com/api/v1/powerisa/dcffixqq.json"},{"mnemonic":"dcmpo","slug":"dcmpo","records":1,"summary":"Compares two decimal floating-point operands and updates the condition register.","page":"https://instructionsets.com/powerisa/dcmpo/","api":"https://instructionsets.com/api/v1/powerisa/dcmpo.json"},{"mnemonic":"dcmpoq","slug":"dcmpoq","records":1,"summary":"Compares two DFP values and sets the condition register based on their order.","page":"https://instructionsets.com/powerisa/dcmpoq/","api":"https://instructionsets.com/api/v1/powerisa/dcmpoq.json"},{"mnemonic":"dcmpu","slug":"dcmpu","records":1,"summary":"Compares two DFP operands and sets the CR field to indicate the result.","page":"https://instructionsets.com/powerisa/dcmpu/","api":"https://instructionsets.com/api/v1/powerisa/dcmpu.json"},{"mnemonic":"dcmpuq","slug":"dcmpuq","records":1,"summary":"Compares two 128-bit DFP numbers (Non-signaling).","page":"https://instructionsets.com/powerisa/dcmpuq/","api":"https://instructionsets.com/api/v1/powerisa/dcmpuq.json"},{"mnemonic":"dcread","slug":"dcread","records":1,"summary":"Reads a data cache tag or data (Debug).","page":"https://instructionsets.com/powerisa/dcread/","api":"https://instructionsets.com/api/v1/powerisa/dcread.json"},{"mnemonic":"dctdp","slug":"dctdp","records":1,"summary":"Converts DFP Short (32-bit compressed) to DFP Long (64-bit).","page":"https://instructionsets.com/powerisa/dctdp/","api":"https://instructionsets.com/api/v1/powerisa/dctdp.json"},{"mnemonic":"dctfix","slug":"dctfix","records":1,"summary":"Converts a decimal floating-point number to a fixed-point integer.","page":"https://instructionsets.com/powerisa/dctfix/","api":"https://instructionsets.com/api/v1/powerisa/dctfix.json"},{"mnemonic":"dctfix.","slug":"dctfix_","records":1,"summary":"Converts a decimal floating-point number to a fixed-point integer.","page":"https://instructionsets.com/powerisa/dctfix_/","api":"https://instructionsets.com/api/v1/powerisa/dctfix_.json"},{"mnemonic":"dctfixq","slug":"dctfixq","records":1,"summary":"Converts 128-bit DFP to 64-bit integer.","page":"https://instructionsets.com/powerisa/dctfixq/","api":"https://instructionsets.com/api/v1/powerisa/dctfixq.json"},{"mnemonic":"dctqpq","slug":"dctqpq","records":1,"summary":"Converts DFP Long (64-bit) to DFP Quad (128-bit).","page":"https://instructionsets.com/powerisa/dctqpq/","api":"https://instructionsets.com/api/v1/powerisa/dctqpq.json"},{"mnemonic":"ddedpd","slug":"ddedpd","records":1,"summary":"Converts a portion of the significand of a DFP operand to a signed or unsigned BCD number.","page":"https://instructionsets.com/powerisa/ddedpd/","api":"https://instructionsets.com/api/v1/powerisa/ddedpd.json"},{"mnemonic":"ddedpd.","slug":"ddedpd_","records":1,"summary":"Converts a portion of the significand of a DFP operand to a signed or unsigned BCD number.","page":"https://instructionsets.com/powerisa/ddedpd_/","api":"https://instructionsets.com/api/v1/powerisa/ddedpd_.json"},{"mnemonic":"ddedpdq","slug":"ddedpdq","records":1,"summary":"Decodes BCD to 128-bit DFP.","page":"https://instructionsets.com/powerisa/ddedpdq/","api":"https://instructionsets.com/api/v1/powerisa/ddedpdq.json"},{"mnemonic":"ddiv","slug":"ddiv","records":1,"summary":"Divides the contents of two decimal floating-point registers and places the result in a target register.","page":"https://instructionsets.com/powerisa/ddiv/","api":"https://instructionsets.com/api/v1/powerisa/ddiv.json"},{"mnemonic":"ddiv.","slug":"ddiv_","records":1,"summary":"Divides the contents of two decimal floating-point registers and places the result in a target register.","page":"https://instructionsets.com/powerisa/ddiv_/","api":"https://instructionsets.com/api/v1/powerisa/ddiv_.json"},{"mnemonic":"ddivq","slug":"ddivq","records":1,"summary":"Divides two 128-bit DFP numbers.","page":"https://instructionsets.com/powerisa/ddivq/","api":"https://instructionsets.com/api/v1/powerisa/ddivq.json"},{"mnemonic":"denbcd","slug":"denbcd","records":1,"summary":"Encodes a DFP number into BCD format.","page":"https://instructionsets.com/powerisa/denbcd/","api":"https://instructionsets.com/api/v1/powerisa/denbcd.json"},{"mnemonic":"denbcdq","slug":"denbcdq","records":1,"summary":"Encodes 128-bit DFP to BCD.","page":"https://instructionsets.com/powerisa/denbcdq/","api":"https://instructionsets.com/api/v1/powerisa/denbcdq.json"},{"mnemonic":"diex","slug":"diex","records":1,"summary":"Combines a sign/coefficient from FRA and exponent from FRB.","page":"https://instructionsets.com/powerisa/diex/","api":"https://instructionsets.com/api/v1/powerisa/diex.json"},{"mnemonic":"diexq","slug":"diexq","records":1,"summary":"Inserts exponent into 128-bit DFP.","page":"https://instructionsets.com/powerisa/diexq/","api":"https://instructionsets.com/api/v1/powerisa/diexq.json"},{"mnemonic":"diexq.","slug":"diexq_","records":1,"summary":"Inserts the biased exponent from a source register into a destination register in quad format.","page":"https://instructionsets.com/powerisa/diexq_/","api":"https://instructionsets.com/api/v1/powerisa/diexq_.json"},{"mnemonic":"divd","slug":"divd","records":1,"summary":"Divides the contents of two registers and places the quotient into a target register.","page":"https://instructionsets.com/powerisa/divd/","api":"https://instructionsets.com/api/v1/powerisa/divd.json"},{"mnemonic":"divde","slug":"divde","records":1,"summary":"Divides the contents of two registers and updates the condition register.","page":"https://instructionsets.com/powerisa/divde/","api":"https://instructionsets.com/api/v1/powerisa/divde.json"},{"mnemonic":"divdeu","slug":"divdeu","records":1,"summary":"64-bit extended unsigned division.","page":"https://instructionsets.com/powerisa/divdeu/","api":"https://instructionsets.com/api/v1/powerisa/divdeu.json"},{"mnemonic":"divdu","slug":"divdu","records":1,"summary":"Divides the 64-bit value in RA by the 64-bit value in RB (Unsigned).","page":"https://instructionsets.com/powerisa/divdu/","api":"https://instructionsets.com/api/v1/powerisa/divdu.json"},{"mnemonic":"divsq","slug":"divsq","records":1,"summary":"Divides a 128-bit signed integer by a 128-bit signed integer (using VSX pairs).","page":"https://instructionsets.com/powerisa/divsq/","api":"https://instructionsets.com/api/v1/powerisa/divsq.json"},{"mnemonic":"divuq","slug":"divuq","records":1,"summary":"Divides a 128-bit unsigned integer by a 128-bit unsigned integer.","page":"https://instructionsets.com/powerisa/divuq/","api":"https://instructionsets.com/api/v1/powerisa/divuq.json"},{"mnemonic":"divw","slug":"divw","records":1,"summary":"Divides the contents of two registers and places the quotient into a target register.","page":"https://instructionsets.com/powerisa/divw/","api":"https://instructionsets.com/api/v1/powerisa/divw.json"},{"mnemonic":"divwe","slug":"divwe","records":1,"summary":"Performs a signed division of a 64-bit dividend by a 32-bit divisor and places the result in a 32-bit register.","page":"https://instructionsets.com/powerisa/divwe/","api":"https://instructionsets.com/api/v1/powerisa/divwe.json"},{"mnemonic":"divweu","slug":"divweu","records":1,"summary":"Performs an unsigned division of a 64-bit dividend by a 32-bit divisor and returns the quotient in a 32-bit register.","page":"https://instructionsets.com/powerisa/divweu/","api":"https://instructionsets.com/api/v1/powerisa/divweu.json"},{"mnemonic":"divwu","slug":"divwu","records":1,"summary":"Divides the lower 32 bits of RA by the lower 32 bits of RB (Unsigned).","page":"https://instructionsets.com/powerisa/divwu/","api":"https://instructionsets.com/api/v1/powerisa/divwu.json"},{"mnemonic":"dmul","slug":"dmul","records":1,"summary":"Multiplies the contents of two DFP registers and places the result in another DFP register.","page":"https://instructionsets.com/powerisa/dmul/","api":"https://instructionsets.com/api/v1/powerisa/dmul.json"},{"mnemonic":"dmul.","slug":"dmul_","records":1,"summary":"Multiplies the contents of two DFP registers and places the result in another DFP register.","page":"https://instructionsets.com/powerisa/dmul_/","api":"https://instructionsets.com/api/v1/powerisa/dmul_.json"},{"mnemonic":"dmulq","slug":"dmulq","records":1,"summary":"Multiplies two 128-bit DFP numbers.","page":"https://instructionsets.com/powerisa/dmulq/","api":"https://instructionsets.com/api/v1/powerisa/dmulq.json"},{"mnemonic":"dqua","slug":"dqua","records":1,"summary":"Adjusts the exponent of a DFP number to match a reference. Critical for aligning decimal points before addition.","page":"https://instructionsets.com/powerisa/dqua/","api":"https://instructionsets.com/api/v1/powerisa/dqua.json"},{"mnemonic":"dqua.","slug":"dqua_","records":1,"summary":"Adjusts the exponent of a DFP number to match a reference. Critical for aligning decimal points before addition.","page":"https://instructionsets.com/powerisa/dqua_/","api":"https://instructionsets.com/api/v1/powerisa/dqua_.json"},{"mnemonic":"dquai","slug":"dquai","records":1,"summary":"Adjusts the value to a form having the specified exponent in the range -16 to 15.","page":"https://instructionsets.com/powerisa/dquai/","api":"https://instructionsets.com/api/v1/powerisa/dquai.json"},{"mnemonic":"dquai.","slug":"dquai_","records":1,"summary":"Quantizes a DFP value to an immediate number of decimal digits.","page":"https://instructionsets.com/powerisa/dquai_/","api":"https://instructionsets.com/api/v1/powerisa/dquai_.json"},{"mnemonic":"dquaq","slug":"dquaq","records":1,"summary":"Adjusts exponent of 128-bit DFP number.","page":"https://instructionsets.com/powerisa/dquaq/","api":"https://instructionsets.com/api/v1/powerisa/dquaq.json"},{"mnemonic":"drdpq","slug":"drdpq","records":1,"summary":"Rounds DFP Quad (128-bit) to DFP Long (64-bit).","page":"https://instructionsets.com/powerisa/drdpq/","api":"https://instructionsets.com/api/v1/powerisa/drdpq.json"},{"mnemonic":"drintn","slug":"drintn","records":1,"summary":"Rounds a decimal floating-point number to an integer without recognizing an inexact exception.","page":"https://instructionsets.com/powerisa/drintn/","api":"https://instructionsets.com/api/v1/powerisa/drintn.json"},{"mnemonic":"drintn.","slug":"drintn_","records":1,"summary":"Rounds a decimal floating-point number to an integer without recognizing an inexact exception.","page":"https://instructionsets.com/powerisa/drintn_/","api":"https://instructionsets.com/api/v1/powerisa/drintn_.json"},{"mnemonic":"drintx","slug":"drintx","records":1,"summary":"Rounds a decimal floating-point number to the nearest integer and places it into a floating-point register.","page":"https://instructionsets.com/powerisa/drintx/","api":"https://instructionsets.com/api/v1/powerisa/drintx.json"},{"mnemonic":"drintx.","slug":"drintx_","records":1,"summary":"Rounds a decimal floating-point number to the nearest integer and places it into a floating-point register.","page":"https://instructionsets.com/powerisa/drintx_/","api":"https://instructionsets.com/api/v1/powerisa/drintx_.json"},{"mnemonic":"drrnd","slug":"drrnd","records":1,"summary":"Rounds a decimal floating-point value to the specified number of significant digits.","page":"https://instructionsets.com/powerisa/drrnd/","api":"https://instructionsets.com/api/v1/powerisa/drrnd.json"},{"mnemonic":"drrnd.","slug":"drrnd_","records":1,"summary":"Rerounds a decimal floating-point number to the specified precision.","page":"https://instructionsets.com/powerisa/drrnd_/","api":"https://instructionsets.com/api/v1/powerisa/drrnd_.json"},{"mnemonic":"drrndq","slug":"drrndq","records":1,"summary":"Rerounds a 128-bit DFP number to fewer digits.","page":"https://instructionsets.com/powerisa/drrndq/","api":"https://instructionsets.com/api/v1/powerisa/drrndq.json"},{"mnemonic":"drsp","slug":"drsp","records":1,"summary":"Rounds DFP Long (64-bit) to DFP Short (32-bit compressed).","page":"https://instructionsets.com/powerisa/drsp/","api":"https://instructionsets.com/api/v1/powerisa/drsp.json"},{"mnemonic":"drsp.","slug":"drsp_","records":1,"summary":"Rounds DFP Long (64-bit) to DFP Short (32-bit compressed).","page":"https://instructionsets.com/powerisa/drsp_/","api":"https://instructionsets.com/api/v1/powerisa/drsp_.json"},{"mnemonic":"dscli","slug":"dscli","records":1,"summary":"Shifts the significand of a DFP operand left by a specified number of digits.","page":"https://instructionsets.com/powerisa/dscli/","api":"https://instructionsets.com/api/v1/powerisa/dscli.json"},{"mnemonic":"dsri","slug":"dsri","records":1,"summary":"Shifts the coefficient of a DFP number right.","page":"https://instructionsets.com/powerisa/dsri/","api":"https://instructionsets.com/api/v1/powerisa/dsri.json"},{"mnemonic":"dss","slug":"dss","records":1,"summary":"Stops a data stream prefetch operation.","page":"https://instructionsets.com/powerisa/dss/","api":"https://instructionsets.com/api/v1/powerisa/dss.json"},{"mnemonic":"dssall","slug":"dssall","records":1,"summary":"Stops all active data stream prefetch operations.","page":"https://instructionsets.com/powerisa/dssall/","api":"https://instructionsets.com/api/v1/powerisa/dssall.json"},{"mnemonic":"dst","slug":"dst","records":1,"summary":"Initiates a hardware data stream prefetch (AltiVec Legacy).","page":"https://instructionsets.com/powerisa/dst/","api":"https://instructionsets.com/api/v1/powerisa/dst.json"},{"mnemonic":"dstst","slug":"dstst","records":1,"summary":"Initiates a prefetch for writing.","page":"https://instructionsets.com/powerisa/dstst/","api":"https://instructionsets.com/api/v1/powerisa/dstst.json"},{"mnemonic":"dststt","slug":"dststt","records":1,"summary":"Initiates a transient prefetch for writing.","page":"https://instructionsets.com/powerisa/dststt/","api":"https://instructionsets.com/api/v1/powerisa/dststt.json"},{"mnemonic":"dstt","slug":"dstt","records":1,"summary":"Initiates a transient (non-temporal) data stream prefetch.","page":"https://instructionsets.com/powerisa/dstt/","api":"https://instructionsets.com/api/v1/powerisa/dstt.json"},{"mnemonic":"dsub","slug":"dsub","records":1,"summary":"Subtracts the contents of two DFP registers and places the result in another DFP register.","page":"https://instructionsets.com/powerisa/dsub/","api":"https://instructionsets.com/api/v1/powerisa/dsub.json"},{"mnemonic":"dsubq","slug":"dsubq","records":1,"summary":"Subtracts two 128-bit DFP numbers.","page":"https://instructionsets.com/powerisa/dsubq/","api":"https://instructionsets.com/api/v1/powerisa/dsubq.json"},{"mnemonic":"dtstdc","slug":"dtstdc","records":1,"summary":"Tests the data class of a DFP operand and sets the CR field.","page":"https://instructionsets.com/powerisa/dtstdc/","api":"https://instructionsets.com/api/v1/powerisa/dtstdc.json"},{"mnemonic":"dtstex","slug":"dtstex","records":1,"summary":"Compares the exponent values of two DFP operands and updates CR field BF and FPCC.","page":"https://instructionsets.com/powerisa/dtstex/","api":"https://instructionsets.com/api/v1/powerisa/dtstex.json"},{"mnemonic":"dtstsf","slug":"dtstsf","records":1,"summary":"Tests the significance of a DFP value in FPR[FRB] against a reference significance.","page":"https://instructionsets.com/powerisa/dtstsf/","api":"https://instructionsets.com/api/v1/powerisa/dtstsf.json"},{"mnemonic":"dtstsfi","slug":"dtstsfi","records":1,"summary":"Tests the significance of a decimal floating-point value in FPR[FRB] against an immediate value UIM.","page":"https://instructionsets.com/powerisa/dtstsfi/","api":"https://instructionsets.com/api/v1/powerisa/dtstsfi.json"},{"mnemonic":"dtstsfiq","slug":"dtstsfiq","records":1,"summary":"Tests DFP Quad significance.","page":"https://instructionsets.com/powerisa/dtstsfiq/","api":"https://instructionsets.com/api/v1/powerisa/dtstsfiq.json"},{"mnemonic":"dxex","slug":"dxex","records":1,"summary":"Extracts the biased exponent of a DFP operand in FRB and places it into FRT.","page":"https://instructionsets.com/powerisa/dxex/","api":"https://instructionsets.com/api/v1/powerisa/dxex.json"},{"mnemonic":"dxex.","slug":"dxex_","records":1,"summary":"Extracts the biased exponent of a DFP operand in FRB and places it into FRT.","page":"https://instructionsets.com/powerisa/dxex_/","api":"https://instructionsets.com/api/v1/powerisa/dxex_.json"},{"mnemonic":"dxexq","slug":"dxexq","records":1,"summary":"Extracts exponent from 128-bit DFP.","page":"https://instructionsets.com/powerisa/dxexq/","api":"https://instructionsets.com/api/v1/powerisa/dxexq.json"},{"mnemonic":"eciwx","slug":"eciwx","records":1,"summary":"Loads a word from an external device using the EAR register.","page":"https://instructionsets.com/powerisa/eciwx/","api":"https://instructionsets.com/api/v1/powerisa/eciwx.json"},{"mnemonic":"ecowx","slug":"ecowx","records":1,"summary":"Stores a word to an external device using the EAR register.","page":"https://instructionsets.com/powerisa/ecowx/","api":"https://instructionsets.com/api/v1/powerisa/ecowx.json"},{"mnemonic":"ehpriv","slug":"ehpriv","records":1,"summary":"Enters embedded hypervisor privileged state.","page":"https://instructionsets.com/powerisa/ehpriv/","api":"https://instructionsets.com/api/v1/powerisa/ehpriv.json"},{"mnemonic":"eieio","slug":"eieio","records":1,"summary":"Ensures that load/store instructions preceding the EIEIO complete before those following it. Used for Memory-Mapped I/O synchronization.","page":"https://instructionsets.com/powerisa/eieio/","api":"https://instructionsets.com/api/v1/powerisa/eieio.json"},{"mnemonic":"eqv","slug":"eqv","records":1,"summary":"Bitwise Equivalence (XNOR). RA = ~(RS ^ RB).","page":"https://instructionsets.com/powerisa/eqv/","api":"https://instructionsets.com/api/v1/powerisa/eqv.json"},{"mnemonic":"extldi","slug":"extldi","records":1,"summary":"Extracts a field of n bits starting at bit position b in the source register, left justifies this field in the target register, and clears all other bits of the target register to 0.","page":"https://instructionsets.com/powerisa/extldi/","api":"https://instructionsets.com/api/v1/powerisa/extldi.json"},{"mnemonic":"extlwi","slug":"extlwi","records":1,"summary":"Extracts a specified number of bits from the source register, left-justifies them, and places them in the target register.","page":"https://instructionsets.com/powerisa/extlwi/","api":"https://instructionsets.com/api/v1/powerisa/extlwi.json"},{"mnemonic":"extsb","slug":"extsb","records":1,"summary":"Sign extends the low byte of a register to the full width.","page":"https://instructionsets.com/powerisa/extsb/","api":"https://instructionsets.com/api/v1/powerisa/extsb.json"},{"mnemonic":"extsb.","slug":"extsb_","records":1,"summary":"Sign extends the low byte of a register to the full width.","page":"https://instructionsets.com/powerisa/extsb_/","api":"https://instructionsets.com/api/v1/powerisa/extsb_.json"},{"mnemonic":"extsh","slug":"extsh","records":1,"summary":"Sign extends the low halfword.","page":"https://instructionsets.com/powerisa/extsh/","api":"https://instructionsets.com/api/v1/powerisa/extsh.json"},{"mnemonic":"extsw","slug":"extsw","records":1,"summary":"Sign extends the low word (32-bit) to 64 bits.","page":"https://instructionsets.com/powerisa/extsw/","api":"https://instructionsets.com/api/v1/powerisa/extsw.json"},{"mnemonic":"extsw.","slug":"extsw_","records":1,"summary":"Sign extends the low word (32-bit) to 64 bits.","page":"https://instructionsets.com/powerisa/extsw_/","api":"https://instructionsets.com/api/v1/powerisa/extsw_.json"},{"mnemonic":"extswsli","slug":"extswsli","records":1,"summary":"Sign-extends the low-order 32 bits of a register, shifts it left by SH bits, and places the result in another register.","page":"https://instructionsets.com/powerisa/extswsli/","api":"https://instructionsets.com/api/v1/powerisa/extswsli.json"},{"mnemonic":"fabs","slug":"fabs","records":1,"summary":"Computes absolute value of a float.","page":"https://instructionsets.com/powerisa/fabs/","api":"https://instructionsets.com/api/v1/powerisa/fabs.json"},{"mnemonic":"fadd","slug":"fadd","records":1,"summary":"Adds the contents of two floating-point registers and places the result into another register.","page":"https://instructionsets.com/powerisa/fadd/","api":"https://instructionsets.com/api/v1/powerisa/fadd.json"},{"mnemonic":"fadd.","slug":"fadd_","records":1,"summary":"Adds the contents of two floating-point registers and places the result into another register.","page":"https://instructionsets.com/powerisa/fadd_/","api":"https://instructionsets.com/api/v1/powerisa/fadd_.json"},{"mnemonic":"fcfid","slug":"fcfid","records":1,"summary":"Converts a signed doubleword integer to a double-precision floating-point number.","page":"https://instructionsets.com/powerisa/fcfid/","api":"https://instructionsets.com/api/v1/powerisa/fcfid.json"},{"mnemonic":"fcfid.","slug":"fcfid_","records":1,"summary":"Converts a signed doubleword integer to a double-precision floating-point number.","page":"https://instructionsets.com/powerisa/fcfid_/","api":"https://instructionsets.com/api/v1/powerisa/fcfid_.json"},{"mnemonic":"fcfids","slug":"fcfids","records":1,"summary":"Converts a 64-bit signed fixed-point operand in register FRB to single-precision floating-point.","page":"https://instructionsets.com/powerisa/fcfids/","api":"https://instructionsets.com/api/v1/powerisa/fcfids.json"},{"mnemonic":"fcfids.","slug":"fcfids_","records":1,"summary":"Converts a 64-bit signed fixed-point operand in register FRB to single-precision floating-point.","page":"https://instructionsets.com/powerisa/fcfids_/","api":"https://instructionsets.com/api/v1/powerisa/fcfids_.json"},{"mnemonic":"fcfidu","slug":"fcfidu","records":1,"summary":"Converts 64-bit Unsigned Int to Double.","page":"https://instructionsets.com/powerisa/fcfidu/","api":"https://instructionsets.com/api/v1/powerisa/fcfidu.json"},{"mnemonic":"fcfidus","slug":"fcfidus","records":1,"summary":"Converts 64-bit Unsigned Int to Single.","page":"https://instructionsets.com/powerisa/fcfidus/","api":"https://instructionsets.com/api/v1/powerisa/fcfidus.json"},{"mnemonic":"fcfidus.","slug":"fcfidus_","records":1,"summary":"Converts an unsigned doubleword integer in a floating-point register to a single-precision floating-point number, rounding the result.","page":"https://instructionsets.com/powerisa/fcfidus_/","api":"https://instructionsets.com/api/v1/powerisa/fcfidus_.json"},{"mnemonic":"fcmpu","slug":"fcmpu","records":1,"summary":"Compares two floating-point registers and sets the Condition Register (CR) field. Does not trap on NaNs.","page":"https://instructionsets.com/powerisa/fcmpu/","api":"https://instructionsets.com/api/v1/powerisa/fcmpu.json"},{"mnemonic":"fcpsgn","slug":"fcpsgn","records":1,"summary":"Copies sign from FRB to FRA.","page":"https://instructionsets.com/powerisa/fcpsgn/","api":"https://instructionsets.com/api/v1/powerisa/fcpsgn.json"},{"mnemonic":"fcpsgn.","slug":"fcpsgn_","records":1,"summary":"Copies the sign of one floating-point number to another.","page":"https://instructionsets.com/powerisa/fcpsgn_/","api":"https://instructionsets.com/api/v1/powerisa/fcpsgn_.json"},{"mnemonic":"fctid","slug":"fctid","records":1,"summary":"Converts a double-precision floating-point value to a signed 64-bit integer using rounding.","page":"https://instructionsets.com/powerisa/fctid/","api":"https://instructionsets.com/api/v1/powerisa/fctid.json"},{"mnemonic":"fctidu","slug":"fctidu","records":1,"summary":"Converts a double-precision floating-point value to an unsigned 64-bit integer using rounding.","page":"https://instructionsets.com/powerisa/fctidu/","api":"https://instructionsets.com/api/v1/powerisa/fctidu.json"},{"mnemonic":"fctidz","slug":"fctidz","records":1,"summary":"Converts Double to 64-bit Int (Truncate).","page":"https://instructionsets.com/powerisa/fctidz/","api":"https://instructionsets.com/api/v1/powerisa/fctidz.json"},{"mnemonic":"fctiw","slug":"fctiw","records":1,"summary":"Converts a float to a 32-bit signed integer (using the current rounding mode) and stores it in the lower half of the FPR.","page":"https://instructionsets.com/powerisa/fctiw/","api":"https://instructionsets.com/api/v1/powerisa/fctiw.json"},{"mnemonic":"fctiw.","slug":"fctiw_","records":1,"summary":"Converts a float to a 32-bit signed integer (using the current rounding mode) and stores it in the lower half of the FPR.","page":"https://instructionsets.com/powerisa/fctiw_/","api":"https://instructionsets.com/api/v1/powerisa/fctiw_.json"},{"mnemonic":"fctiwu","slug":"fctiwu","records":1,"summary":"Converts a double-precision floating-point value to an unsigned integer using rounding.","page":"https://instructionsets.com/powerisa/fctiwu/","api":"https://instructionsets.com/api/v1/powerisa/fctiwu.json"},{"mnemonic":"fctiwuz","slug":"fctiwuz","records":1,"summary":"Converts a double-precision floating-point number to an unsigned integer word.","page":"https://instructionsets.com/powerisa/fctiwuz/","api":"https://instructionsets.com/api/v1/powerisa/fctiwuz.json"},{"mnemonic":"fctiwz","slug":"fctiwz","records":1,"summary":"Converts Double to 32-bit Int (Truncate).","page":"https://instructionsets.com/powerisa/fctiwz/","api":"https://instructionsets.com/api/v1/powerisa/fctiwz.json"},{"mnemonic":"fdiv.","slug":"fdiv_","records":1,"summary":"Divides the contents of two floating-point registers and updates the condition register.","page":"https://instructionsets.com/powerisa/fdiv_/","api":"https://instructionsets.com/api/v1/powerisa/fdiv_.json"},{"mnemonic":"fdivs","slug":"fdivs","records":1,"summary":"Divides the contents of two single precision floating point registers.","page":"https://instructionsets.com/powerisa/fdivs/","api":"https://instructionsets.com/api/v1/powerisa/fdivs.json"},{"mnemonic":"fmadd","slug":"fmadd","records":1,"summary":"Performs (A * C) + B with a single rounding step. (The classic FMA).","page":"https://instructionsets.com/powerisa/fmadd/","api":"https://instructionsets.com/api/v1/powerisa/fmadd.json"},{"mnemonic":"fmadd.","slug":"fmadd_","records":1,"summary":"Performs (A * C) + B with a single rounding step. (The classic FMA).","page":"https://instructionsets.com/powerisa/fmadd_/","api":"https://instructionsets.com/api/v1/powerisa/fmadd_.json"},{"mnemonic":"fmr","slug":"fmr","records":1,"summary":"Copies a float register (Pseudo: for FRB).","page":"https://instructionsets.com/powerisa/fmr/","api":"https://instructionsets.com/api/v1/powerisa/fmr.json"},{"mnemonic":"fmr.","slug":"fmr_","records":1,"summary":"Copies a float register (Pseudo: for FRB).","page":"https://instructionsets.com/powerisa/fmr_/","api":"https://instructionsets.com/api/v1/powerisa/fmr_.json"},{"mnemonic":"fmrgew","slug":"fmrgew","records":1,"summary":"Merges the even words from two floating-point registers into a third.","page":"https://instructionsets.com/powerisa/fmrgew/","api":"https://instructionsets.com/api/v1/powerisa/fmrgew.json"},{"mnemonic":"fmsub","slug":"fmsub","records":1,"summary":"Multiplies two floating-point values and subtracts a third.","page":"https://instructionsets.com/powerisa/fmsub/","api":"https://instructionsets.com/api/v1/powerisa/fmsub.json"},{"mnemonic":"fmul","slug":"fmul","records":1,"summary":"Multiplies the contents of two floating-point registers and places the result into another register.","page":"https://instructionsets.com/powerisa/fmul/","api":"https://instructionsets.com/api/v1/powerisa/fmul.json"},{"mnemonic":"fmul.","slug":"fmul_","records":1,"summary":"Multiplies the contents of two floating-point registers and places the result into another register.","page":"https://instructionsets.com/powerisa/fmul_/","api":"https://instructionsets.com/api/v1/powerisa/fmul_.json"},{"mnemonic":"fnabs","slug":"fnabs","records":1,"summary":"Computes negative absolute value of a float.","page":"https://instructionsets.com/powerisa/fnabs/","api":"https://instructionsets.com/api/v1/powerisa/fnabs.json"},{"mnemonic":"fneg","slug":"fneg","records":1,"summary":"Negates a float.","page":"https://instructionsets.com/powerisa/fneg/","api":"https://instructionsets.com/api/v1/powerisa/fneg.json"},{"mnemonic":"fnmadd","slug":"fnmadd","records":1,"summary":"Performs a floating-point negative multiply-add operation.","page":"https://instructionsets.com/powerisa/fnmadd/","api":"https://instructionsets.com/api/v1/powerisa/fnmadd.json"},{"mnemonic":"fnmadd.","slug":"fnmadd_","records":1,"summary":"Performs a floating-point negative multiply-add operation.","page":"https://instructionsets.com/powerisa/fnmadd_/","api":"https://instructionsets.com/api/v1/powerisa/fnmadd_.json"},{"mnemonic":"fnmsub","slug":"fnmsub","records":1,"summary":"-(A*C - B)","page":"https://instructionsets.com/powerisa/fnmsub/","api":"https://instructionsets.com/api/v1/powerisa/fnmsub.json"},{"mnemonic":"fre","slug":"fre","records":1,"summary":"Estimates the reciprocal of a floating-point operand.","page":"https://instructionsets.com/powerisa/fre/","api":"https://instructionsets.com/api/v1/powerisa/fre.json"},{"mnemonic":"fre.","slug":"fre_","records":1,"summary":"Estimates the reciprocal of a floating-point number.","page":"https://instructionsets.com/powerisa/fre_/","api":"https://instructionsets.com/api/v1/powerisa/fre_.json"},{"mnemonic":"fres","slug":"fres","records":1,"summary":"Estimates the reciprocal of a single-precision floating-point number.","page":"https://instructionsets.com/powerisa/fres/","api":"https://instructionsets.com/api/v1/powerisa/fres.json"},{"mnemonic":"frin","slug":"frin","records":1,"summary":"Rounds the floating-point operand in register FRB to an integral value using the rounding mode round to nearest.","page":"https://instructionsets.com/powerisa/frin/","api":"https://instructionsets.com/api/v1/powerisa/frin.json"},{"mnemonic":"frin.","slug":"frin_","records":1,"summary":"Rounds the floating-point operand in register FRB to an integral value using the rounding mode round to nearest.","page":"https://instructionsets.com/powerisa/frin_/","api":"https://instructionsets.com/api/v1/powerisa/frin_.json"},{"mnemonic":"frip","slug":"frip","records":1,"summary":"Rounds a floating-point operand towards +infinity and places the result into a register.","page":"https://instructionsets.com/powerisa/frip/","api":"https://instructionsets.com/api/v1/powerisa/frip.json"},{"mnemonic":"frip.","slug":"frip_","records":1,"summary":"Rounds a floating-point operand towards +infinity and places the result into a register.","page":"https://instructionsets.com/powerisa/frip_/","api":"https://instructionsets.com/api/v1/powerisa/frip_.json"},{"mnemonic":"frsp","slug":"frsp","records":1,"summary":"Rounds the contents of a floating-point register to single-precision.","page":"https://instructionsets.com/powerisa/frsp/","api":"https://instructionsets.com/api/v1/powerisa/frsp.json"},{"mnemonic":"frsp.","slug":"frsp_","records":1,"summary":"Rounds the contents of a floating-point register to single-precision.","page":"https://instructionsets.com/powerisa/frsp_/","api":"https://instructionsets.com/api/v1/powerisa/frsp_.json"},{"mnemonic":"frsqrte","slug":"frsqrte","records":1,"summary":"Estimates the reciprocal of the square root of a floating-point operand.","page":"https://instructionsets.com/powerisa/frsqrte/","api":"https://instructionsets.com/api/v1/powerisa/frsqrte.json"},{"mnemonic":"frsqrte.","slug":"frsqrte_","records":1,"summary":"Estimates the reciprocal of the square root of a floating-point operand.","page":"https://instructionsets.com/powerisa/frsqrte_/","api":"https://instructionsets.com/api/v1/powerisa/frsqrte_.json"},{"mnemonic":"frsqrtes","slug":"frsqrtes","records":1,"summary":"Estimates 1/sqrt(x) (Single Precision).","page":"https://instructionsets.com/powerisa/frsqrtes/","api":"https://instructionsets.com/api/v1/powerisa/frsqrtes.json"},{"mnemonic":"fsel","slug":"fsel","records":1,"summary":"Selects FRA if FRC >= 0, else FRB (Optional).","page":"https://instructionsets.com/powerisa/fsel/","api":"https://instructionsets.com/api/v1/powerisa/fsel.json"},{"mnemonic":"fsel.","slug":"fsel_","records":1,"summary":"Selects FRA if FRC >= 0, else FRB (Optional).","page":"https://instructionsets.com/powerisa/fsel_/","api":"https://instructionsets.com/api/v1/powerisa/fsel_.json"},{"mnemonic":"fsqrt","slug":"fsqrt","records":1,"summary":"Computes the square root of a floating-point number.","page":"https://instructionsets.com/powerisa/fsqrt/","api":"https://instructionsets.com/api/v1/powerisa/fsqrt.json"},{"mnemonic":"fsqrt.","slug":"fsqrt_","records":1,"summary":"Computes the square root of a floating-point number.","page":"https://instructionsets.com/powerisa/fsqrt_/","api":"https://instructionsets.com/api/v1/powerisa/fsqrt_.json"},{"mnemonic":"fsqrts","slug":"fsqrts","records":1,"summary":"Computes square root (Single).","page":"https://instructionsets.com/powerisa/fsqrts/","api":"https://instructionsets.com/api/v1/powerisa/fsqrts.json"},{"mnemonic":"ftdiv","slug":"ftdiv","records":1,"summary":"Tests the double-precision floating-point operand in register FRB and sets flags based on certain conditions.","page":"https://instructionsets.com/powerisa/ftdiv/","api":"https://instructionsets.com/api/v1/powerisa/ftdiv.json"},{"mnemonic":"ftsqrt","slug":"ftsqrt","records":1,"summary":"Tests for conditions that would cause a sqrt exception.","page":"https://instructionsets.com/powerisa/ftsqrt/","api":"https://instructionsets.com/api/v1/powerisa/ftsqrt.json"},{"mnemonic":"hashchk","slug":"hashchk","records":1,"summary":"Checks the hash of the Return Address Stack (ROP Protection).","page":"https://instructionsets.com/powerisa/hashchk/","api":"https://instructionsets.com/api/v1/powerisa/hashchk.json"},{"mnemonic":"hashchkp","slug":"hashchkp","records":1,"summary":"Checks the hash value of a memory location against a computed hash.","page":"https://instructionsets.com/powerisa/hashchkp/","api":"https://instructionsets.com/api/v1/powerisa/hashchkp.json"},{"mnemonic":"hashst","slug":"hashst","records":1,"summary":"Stores the computed doubleword hash value to a doubleword storage location.","page":"https://instructionsets.com/powerisa/hashst/","api":"https://instructionsets.com/api/v1/powerisa/hashst.json"},{"mnemonic":"hashstp","slug":"hashstp","records":1,"summary":"Privileged version of hash store.","page":"https://instructionsets.com/powerisa/hashstp/","api":"https://instructionsets.com/api/v1/powerisa/hashstp.json"},{"mnemonic":"hrfid","slug":"hrfid","records":1,"summary":"Returns from a hypervisor interrupt.","page":"https://instructionsets.com/powerisa/hrfid/","api":"https://instructionsets.com/api/v1/powerisa/hrfid.json"},{"mnemonic":"icbi","slug":"icbi","records":1,"summary":"Invalidates the instruction cache block associated with the address. Critical for self-modifying code or JITs.","page":"https://instructionsets.com/powerisa/icbi/","api":"https://instructionsets.com/api/v1/powerisa/icbi.json"},{"mnemonic":"icblc","slug":"icblc","records":1,"summary":"Clears an instruction cache line lock.","page":"https://instructionsets.com/powerisa/icblc/","api":"https://instructionsets.com/api/v1/powerisa/icblc.json"},{"mnemonic":"icbt","slug":"icbt","records":1,"summary":"Provides a hint that the program will soon execute code from the block containing the byte addressed by EA, and that the block should be loaded into the cache specified by the CT field.","page":"https://instructionsets.com/powerisa/icbt/","api":"https://instructionsets.com/api/v1/powerisa/icbt.json"},{"mnemonic":"iccci","slug":"iccci","records":1,"summary":"Invalidates a congruence class in the instruction cache (Embedded).","page":"https://instructionsets.com/powerisa/iccci/","api":"https://instructionsets.com/api/v1/powerisa/iccci.json"},{"mnemonic":"icread","slug":"icread","records":1,"summary":"Reads an instruction cache tag or data (Debug).","page":"https://instructionsets.com/powerisa/icread/","api":"https://instructionsets.com/api/v1/powerisa/icread.json"},{"mnemonic":"isel","slug":"isel","records":1,"summary":"Conditionally copies RA or RB to RT based on a CR bit. (Equivalent to C ternary operator 'cond ? a : b').","page":"https://instructionsets.com/powerisa/isel/","api":"https://instructionsets.com/api/v1/powerisa/isel.json"},{"mnemonic":"isync","slug":"isync","records":1,"summary":"Ensures that all instructions preceding the isync instruction have completed before it completes, and that no subsequent instructions are initiated until after the isync instruction completes.","page":"https://instructionsets.com/powerisa/isync/","api":"https://instructionsets.com/api/v1/powerisa/isync.json"},{"mnemonic":"lbarx","slug":"lbarx","records":1,"summary":"Loads a byte from memory and reserves the location for exclusive access.","page":"https://instructionsets.com/powerisa/lbarx/","api":"https://instructionsets.com/api/v1/powerisa/lbarx.json"},{"mnemonic":"lbz","slug":"lbz","records":1,"summary":"Loads a byte from memory into the low 8 bits of a register and clears the upper 56 bits.","page":"https://instructionsets.com/powerisa/lbz/","api":"https://instructionsets.com/api/v1/powerisa/lbz.json"},{"mnemonic":"lbzcix","slug":"lbzcix","records":1,"summary":"Loads a byte from memory into a register, zeroing the upper bits of the target register.","page":"https://instructionsets.com/powerisa/lbzcix/","api":"https://instructionsets.com/api/v1/powerisa/lbzcix.json"},{"mnemonic":"lbzepx","slug":"lbzepx","records":1,"summary":"Loads a byte using the External PID (for OS kernels accessing user memory).","page":"https://instructionsets.com/powerisa/lbzepx/","api":"https://instructionsets.com/api/v1/powerisa/lbzepx.json"},{"mnemonic":"lbzu","slug":"lbzu","records":1,"summary":"Loads a byte from memory into a register, zeroing the upper bits of the target register, and updates the base address register.","page":"https://instructionsets.com/powerisa/lbzu/","api":"https://instructionsets.com/api/v1/powerisa/lbzu.json"},{"mnemonic":"lbzux","slug":"lbzux","records":1,"summary":"Loads a byte from memory into a register, zero-extends it to 32 bits, and updates the base address.","page":"https://instructionsets.com/powerisa/lbzux/","api":"https://instructionsets.com/api/v1/powerisa/lbzux.json"},{"mnemonic":"ld","slug":"ld","records":1,"summary":"Loads a doubleword (64 bits) from memory.","page":"https://instructionsets.com/powerisa/ld/","api":"https://instructionsets.com/api/v1/powerisa/ld.json"},{"mnemonic":"ldarx","slug":"ldarx","records":1,"summary":"Loads a doubleword and creates a reservation. 64-bit version of lwarx.","page":"https://instructionsets.com/powerisa/ldarx/","api":"https://instructionsets.com/api/v1/powerisa/ldarx.json"},{"mnemonic":"ldat","slug":"ldat","records":1,"summary":"Atomically loads a doubleword from memory.","page":"https://instructionsets.com/powerisa/ldat/","api":"https://instructionsets.com/api/v1/powerisa/ldat.json"},{"mnemonic":"ldbrx","slug":"ldbrx","records":1,"summary":"Loads a doubleword from memory, byte-reversing it before storing in the target register.","page":"https://instructionsets.com/powerisa/ldbrx/","api":"https://instructionsets.com/api/v1/powerisa/ldbrx.json"},{"mnemonic":"ldci","slug":"ldci","records":1,"summary":"Loads a doubleword bypassing the cache.","page":"https://instructionsets.com/powerisa/ldci/","api":"https://instructionsets.com/api/v1/powerisa/ldci.json"},{"mnemonic":"lfd","slug":"lfd","records":1,"summary":"Loads a double-precision floating-point value from memory into a floating-point register.","page":"https://instructionsets.com/powerisa/lfd/","api":"https://instructionsets.com/api/v1/powerisa/lfd.json"},{"mnemonic":"lfdp","slug":"lfdp","records":1,"summary":"Loads a doubleword-pair from storage into an even-odd pair of FPRs.","page":"https://instructionsets.com/powerisa/lfdp/","api":"https://instructionsets.com/api/v1/powerisa/lfdp.json"},{"mnemonic":"lfdu","slug":"lfdu","records":1,"summary":"Loads a doubleword from memory into a floating-point register and updates the base address register.","page":"https://instructionsets.com/powerisa/lfdu/","api":"https://instructionsets.com/api/v1/powerisa/lfdu.json"},{"mnemonic":"lfs","slug":"lfs","records":1,"summary":"Loads a single-precision floating-point value from memory into a floating-point register and converts it to double precision.","page":"https://instructionsets.com/powerisa/lfs/","api":"https://instructionsets.com/api/v1/powerisa/lfs.json"},{"mnemonic":"lfsu","slug":"lfsu","records":1,"summary":"Loads a floating-point single-precision operand from memory into a register and updates the base address.","page":"https://instructionsets.com/powerisa/lfsu/","api":"https://instructionsets.com/api/v1/powerisa/lfsu.json"},{"mnemonic":"lfsx","slug":"lfsx","records":1,"summary":"Loads a single-precision floating-point value from memory into a floating-point register.","page":"https://instructionsets.com/powerisa/lfsx/","api":"https://instructionsets.com/api/v1/powerisa/lfsx.json"},{"mnemonic":"lha","slug":"lha","records":1,"summary":"Loads a halfword (16 bits) from memory and sign-extends it to 64 bits.","page":"https://instructionsets.com/powerisa/lha/","api":"https://instructionsets.com/api/v1/powerisa/lha.json"},{"mnemonic":"lharx","slug":"lharx","records":1,"summary":"Atomic Load Halfword.","page":"https://instructionsets.com/powerisa/lharx/","api":"https://instructionsets.com/api/v1/powerisa/lharx.json"},{"mnemonic":"lhax","slug":"lhax","records":1,"summary":"Loads a halfword from memory into a register and extends it to a full word, with indexed addressing.","page":"https://instructionsets.com/powerisa/lhax/","api":"https://instructionsets.com/api/v1/powerisa/lhax.json"},{"mnemonic":"lhbrx","slug":"lhbrx","records":1,"summary":"Loads a halfword from memory, byte-reverses it, and stores it in a register.","page":"https://instructionsets.com/powerisa/lhbrx/","api":"https://instructionsets.com/api/v1/powerisa/lhbrx.json"},{"mnemonic":"lhz","slug":"lhz","records":1,"summary":"Loads a halfword (16 bits) from memory and clears the upper 48 bits.","page":"https://instructionsets.com/powerisa/lhz/","api":"https://instructionsets.com/api/v1/powerisa/lhz.json"},{"mnemonic":"lhzci","slug":"lhzci","records":1,"summary":"Loads a halfword bypassing the cache.","page":"https://instructionsets.com/powerisa/lhzci/","api":"https://instructionsets.com/api/v1/powerisa/lhzci.json"},{"mnemonic":"lhzepx","slug":"lhzepx","records":1,"summary":"Loads a halfword using the External PID.","page":"https://instructionsets.com/powerisa/lhzepx/","api":"https://instructionsets.com/api/v1/powerisa/lhzepx.json"},{"mnemonic":"lhzu","slug":"lhzu","records":1,"summary":"Loads a halfword from memory into a register, zero-extends it to 64 bits, and updates the base address.","page":"https://instructionsets.com/powerisa/lhzu/","api":"https://instructionsets.com/api/v1/powerisa/lhzu.json"},{"mnemonic":"li","slug":"li","records":1,"summary":"Loads a 16-bit signed immediate into a register. (Alias for 'addi RT, 0, SIM').","page":"https://instructionsets.com/powerisa/li/","api":"https://instructionsets.com/api/v1/powerisa/li.json"},{"mnemonic":"lis","slug":"lis","records":1,"summary":"Loads a 16-bit immediate into the upper half of a 32-bit word. (Alias for 'addis RT, 0, SIM').","page":"https://instructionsets.com/powerisa/lis/","api":"https://instructionsets.com/api/v1/powerisa/lis.json"},{"mnemonic":"lmw","slug":"lmw","records":1,"summary":"Loads words from memory into registers RT through R31 (Context Switch).","page":"https://instructionsets.com/powerisa/lmw/","api":"https://instructionsets.com/api/v1/powerisa/lmw.json"},{"mnemonic":"lq","slug":"lq","records":1,"summary":"Loads 128 bits into two adjacent GPRs (Even/Odd pair).","page":"https://instructionsets.com/powerisa/lq/","api":"https://instructionsets.com/api/v1/powerisa/lq.json"},{"mnemonic":"lqarx","slug":"lqarx","records":1,"summary":"Loads a quadword from memory and reserves the location for conditional store.","page":"https://instructionsets.com/powerisa/lqarx/","api":"https://instructionsets.com/api/v1/powerisa/lqarx.json"},{"mnemonic":"lswi","slug":"lswi","records":1,"summary":"Loads a sequence of bytes from memory into general-purpose registers.","page":"https://instructionsets.com/powerisa/lswi/","api":"https://instructionsets.com/api/v1/powerisa/lswi.json"},{"mnemonic":"lswx","slug":"lswx","records":1,"summary":"Loads N bytes from memory (N in XER).","page":"https://instructionsets.com/powerisa/lswx/","api":"https://instructionsets.com/api/v1/powerisa/lswx.json"},{"mnemonic":"lvebx","slug":"lvebx","records":1,"summary":"Loads a byte from memory into a vector register element.","page":"https://instructionsets.com/powerisa/lvebx/","api":"https://instructionsets.com/api/v1/powerisa/lvebx.json"},{"mnemonic":"lvehx","slug":"lvehx","records":1,"summary":"Loads a halfword element from memory into the corresponding halfword element of a vector register, with the address computed as the sum of RA and RB, aligned to a halfword boundary.","page":"https://instructionsets.com/powerisa/lvehx/","api":"https://instructionsets.com/api/v1/powerisa/lvehx.json"},{"mnemonic":"lvewx","slug":"lvewx","records":1,"summary":"Loads a word from memory into a vector register element.","page":"https://instructionsets.com/powerisa/lvewx/","api":"https://instructionsets.com/api/v1/powerisa/lvewx.json"},{"mnemonic":"lvsl","slug":"lvsl","records":1,"summary":"Loads a vector pattern suitable for shifting left indexed.","page":"https://instructionsets.com/powerisa/lvsl/","api":"https://instructionsets.com/api/v1/powerisa/lvsl.json"},{"mnemonic":"lvx","slug":"lvx","records":1,"summary":"Loads a 128-bit vector from memory into a Vector Register. Address must be 16-byte aligned (bits 60-63 of effective address are ignored).","page":"https://instructionsets.com/powerisa/lvx/","api":"https://instructionsets.com/api/v1/powerisa/lvx.json"},{"mnemonic":"lwa","slug":"lwa","records":1,"summary":"Loads a word (32 bits) from memory and sign-extends it to 64 bits.","page":"https://instructionsets.com/powerisa/lwa/","api":"https://instructionsets.com/api/v1/powerisa/lwa.json"},{"mnemonic":"lwarx","slug":"lwarx","records":1,"summary":"Loads a word and creates a reservation for use with 'stwcx.'. Critical for implementing atomic primitives (mutexes).","page":"https://instructionsets.com/powerisa/lwarx/","api":"https://instructionsets.com/api/v1/powerisa/lwarx.json"},{"mnemonic":"lwat","slug":"lwat","records":1,"summary":"Loads a word from memory atomically.","page":"https://instructionsets.com/powerisa/lwat/","api":"https://instructionsets.com/api/v1/powerisa/lwat.json"},{"mnemonic":"lwax","slug":"lwax","records":1,"summary":"Loads a word from memory into a register using an indexed address.","page":"https://instructionsets.com/powerisa/lwax/","api":"https://instructionsets.com/api/v1/powerisa/lwax.json"},{"mnemonic":"lwbrx","slug":"lwbrx","records":1,"summary":"Loads a word and swaps bytes.","page":"https://instructionsets.com/powerisa/lwbrx/","api":"https://instructionsets.com/api/v1/powerisa/lwbrx.json"},{"mnemonic":"lwdi","slug":"lwdi","records":1,"summary":"Loads a word and sends decoration sideband signals to the bus.","page":"https://instructionsets.com/powerisa/lwdi/","api":"https://instructionsets.com/api/v1/powerisa/lwdi.json"},{"mnemonic":"lwsync","slug":"lwsync","records":1,"summary":"Orders loads with loads, stores with stores, and loads with stores. Does NOT order stores with loads. (Encoded as sync 1).","page":"https://instructionsets.com/powerisa/lwsync/","api":"https://instructionsets.com/api/v1/powerisa/lwsync.json"},{"mnemonic":"lwz","slug":"lwz","records":1,"summary":"Loads a word (32 bits) from memory and clears the upper 32 bits.","page":"https://instructionsets.com/powerisa/lwz/","api":"https://instructionsets.com/api/v1/powerisa/lwz.json"},{"mnemonic":"lwzci","slug":"lwzci","records":1,"summary":"Loads a word bypassing the cache.","page":"https://instructionsets.com/powerisa/lwzci/","api":"https://instructionsets.com/api/v1/powerisa/lwzci.json"},{"mnemonic":"lwzepx","slug":"lwzepx","records":1,"summary":"Loads a word using the External PID.","page":"https://instructionsets.com/powerisa/lwzepx/","api":"https://instructionsets.com/api/v1/powerisa/lwzepx.json"},{"mnemonic":"lxsd","slug":"lxsd","records":1,"summary":"Loads a doubleword from memory into a VSX scalar register.","page":"https://instructionsets.com/powerisa/lxsd/","api":"https://instructionsets.com/api/v1/powerisa/lxsd.json"},{"mnemonic":"lxsdx","slug":"lxsdx","records":1,"summary":"Loads a doubleword from memory into a VSX scalar register.","page":"https://instructionsets.com/powerisa/lxsdx/","api":"https://instructionsets.com/api/v1/powerisa/lxsdx.json"},{"mnemonic":"lxsibzx","slug":"lxsibzx","records":1,"summary":"Loads a byte from memory and places it into the specified VSX register, zeroing the upper half.","page":"https://instructionsets.com/powerisa/lxsibzx/","api":"https://instructionsets.com/api/v1/powerisa/lxsibzx.json"},{"mnemonic":"lxsiwax","slug":"lxsiwax","records":1,"summary":"Loads a word from memory into the left-most doubleword element of a VSR, sign-extends it to 64 bits, and aligns it.","page":"https://instructionsets.com/powerisa/lxsiwax/","api":"https://instructionsets.com/api/v1/powerisa/lxsiwax.json"},{"mnemonic":"lxsiwzx","slug":"lxsiwzx","records":1,"summary":"Loads a word from memory and places it into the specified VSX register, zero-extending it.","page":"https://instructionsets.com/powerisa/lxsiwzx/","api":"https://instructionsets.com/api/v1/powerisa/lxsiwzx.json"},{"mnemonic":"lxssp","slug":"lxssp","records":1,"summary":"Accesses a floating-point operand in single-precision format from storage, converts it to double-precision format, and loads it into a VSR.","page":"https://instructionsets.com/powerisa/lxssp/","api":"https://instructionsets.com/api/v1/powerisa/lxssp.json"},{"mnemonic":"lxsspx","slug":"lxsspx","records":1,"summary":"Loads a single-precision floating-point value from memory and converts it to double-precision format in a VSX register.","page":"https://instructionsets.com/powerisa/lxsspx/","api":"https://instructionsets.com/api/v1/powerisa/lxsspx.json"},{"mnemonic":"lxv","slug":"lxv","records":1,"summary":"Loads a 128-bit vector from memory (VSX aligned offset).","page":"https://instructionsets.com/powerisa/lxv/","api":"https://instructionsets.com/api/v1/powerisa/lxv.json"},{"mnemonic":"lxvb16x","slug":"lxvb16x","records":1,"summary":"Loads a vector of 16 byte elements from memory into a VSX register.","page":"https://instructionsets.com/powerisa/lxvb16x/","api":"https://instructionsets.com/api/v1/powerisa/lxvb16x.json"},{"mnemonic":"lxvd2x","slug":"lxvd2x","records":1,"summary":"Loads a 128-bit vector from memory into a VSX register. Does NOT require 16-byte alignment (unlike lvx).","page":"https://instructionsets.com/powerisa/lxvd2x/","api":"https://instructionsets.com/api/v1/powerisa/lxvd2x.json"},{"mnemonic":"lxvdsx","slug":"lxvdsx","records":1,"summary":"Loads a doubleword from memory and splats it into two elements of a VSX vector register.","page":"https://instructionsets.com/powerisa/lxvdsx/","api":"https://instructionsets.com/api/v1/powerisa/lxvdsx.json"},{"mnemonic":"lxvh8x","slug":"lxvh8x","records":1,"summary":"Loads a vector of 8 halfwords from memory into a VSX register.","page":"https://instructionsets.com/powerisa/lxvh8x/","api":"https://instructionsets.com/api/v1/powerisa/lxvh8x.json"},{"mnemonic":"lxvkq","slug":"lxvkq","records":1,"summary":"Loads a special value into a VSX vector register.","page":"https://instructionsets.com/powerisa/lxvkq/","api":"https://instructionsets.com/api/v1/powerisa/lxvkq.json"},{"mnemonic":"lxvl","slug":"lxvl","records":1,"summary":"Loads N bytes into a vector, where N is specified in a GPR.","page":"https://instructionsets.com/powerisa/lxvl/","api":"https://instructionsets.com/api/v1/powerisa/lxvl.json"},{"mnemonic":"lxvll","slug":"lxvll","records":1,"summary":"Loads a variable-length vector from memory into a VSX register, left-justifying the data.","page":"https://instructionsets.com/powerisa/lxvll/","api":"https://instructionsets.com/api/v1/powerisa/lxvll.json"},{"mnemonic":"lxvp","slug":"lxvp","records":1,"summary":"Loads a double quadword from memory into two VSX registers.","page":"https://instructionsets.com/powerisa/lxvp/","api":"https://instructionsets.com/api/v1/powerisa/lxvp.json"},{"mnemonic":"lxvpx","slug":"lxvpx","records":1,"summary":"Loads a vector from memory into two VSR registers.","page":"https://instructionsets.com/powerisa/lxvpx/","api":"https://instructionsets.com/api/v1/powerisa/lxvpx.json"},{"mnemonic":"lxvrbx","slug":"lxvrbx","records":1,"summary":"Loads a byte from memory into the rightmost byte of a VSX vector register.","page":"https://instructionsets.com/powerisa/lxvrbx/","api":"https://instructionsets.com/api/v1/powerisa/lxvrbx.json"},{"mnemonic":"lxvrdx","slug":"lxvrdx","records":1,"summary":"Loads a doubleword from memory into the rightmost element of a VSX vector register.","page":"https://instructionsets.com/powerisa/lxvrdx/","api":"https://instructionsets.com/api/v1/powerisa/lxvrdx.json"},{"mnemonic":"lxvrhx","slug":"lxvrhx","records":1,"summary":"Loads a halfword from memory into the rightmost element of a VSX vector register.","page":"https://instructionsets.com/powerisa/lxvrhx/","api":"https://instructionsets.com/api/v1/powerisa/lxvrhx.json"},{"mnemonic":"lxvrwx","slug":"lxvrwx","records":1,"summary":"Loads a word from memory into the rightmost word of a VSX vector register.","page":"https://instructionsets.com/powerisa/lxvrwx/","api":"https://instructionsets.com/api/v1/powerisa/lxvrwx.json"},{"mnemonic":"lxvw4x","slug":"lxvw4x","records":1,"summary":"Loads four words into a vector (unaligned).","page":"https://instructionsets.com/powerisa/lxvw4x/","api":"https://instructionsets.com/api/v1/powerisa/lxvw4x.json"},{"mnemonic":"lxvwsx","slug":"lxvwsx","records":1,"summary":"Loads a 32-bit word and replicates it across the vector.","page":"https://instructionsets.com/powerisa/lxvwsx/","api":"https://instructionsets.com/api/v1/powerisa/lxvwsx.json"},{"mnemonic":"lxvx","slug":"lxvx","records":1,"summary":"Loads a quadword from memory into a VSX register.","page":"https://instructionsets.com/powerisa/lxvx/","api":"https://instructionsets.com/api/v1/powerisa/lxvx.json"},{"mnemonic":"macchw","slug":"macchw","records":1,"summary":"Multiply bottom half of RA by top half of RB, add to RT.","page":"https://instructionsets.com/powerisa/macchw/","api":"https://instructionsets.com/api/v1/powerisa/macchw.json"},{"mnemonic":"macchws","slug":"macchws","records":1,"summary":"Signed Multiply Accumulate Cross Halfword with Saturation.","page":"https://instructionsets.com/powerisa/macchws/","api":"https://instructionsets.com/api/v1/powerisa/macchws.json"},{"mnemonic":"macchwsu","slug":"macchwsu","records":1,"summary":"Mixed Sign Multiply Accumulate Cross Halfword with Saturation.","page":"https://instructionsets.com/powerisa/macchwsu/","api":"https://instructionsets.com/api/v1/powerisa/macchwsu.json"},{"mnemonic":"macchwu","slug":"macchwu","records":1,"summary":"Unsigned Multiply Accumulate Cross Halfword.","page":"https://instructionsets.com/powerisa/macchwu/","api":"https://instructionsets.com/api/v1/powerisa/macchwu.json"},{"mnemonic":"machhw","slug":"machhw","records":1,"summary":"Multiply top half of RA by top half of RB, add to RT.","page":"https://instructionsets.com/powerisa/machhw/","api":"https://instructionsets.com/api/v1/powerisa/machhw.json"},{"mnemonic":"machhws","slug":"machhws","records":1,"summary":"Signed Multiply Accumulate High Halfword with Saturation.","page":"https://instructionsets.com/powerisa/machhws/","api":"https://instructionsets.com/api/v1/powerisa/machhws.json"},{"mnemonic":"machhwsu","slug":"machhwsu","records":1,"summary":"Mixed Sign Multiply Accumulate High Halfword with Saturation.","page":"https://instructionsets.com/powerisa/machhwsu/","api":"https://instructionsets.com/api/v1/powerisa/machhwsu.json"},{"mnemonic":"machhwu","slug":"machhwu","records":1,"summary":"Unsigned Multiply Accumulate High Halfword.","page":"https://instructionsets.com/powerisa/machhwu/","api":"https://instructionsets.com/api/v1/powerisa/machhwu.json"},{"mnemonic":"maclhw","slug":"maclhw","records":1,"summary":"Multiply bottom half of RA by bottom half of RB, add to RT.","page":"https://instructionsets.com/powerisa/maclhw/","api":"https://instructionsets.com/api/v1/powerisa/maclhw.json"},{"mnemonic":"maclhws","slug":"maclhws","records":1,"summary":"Signed Multiply Accumulate Low Halfword with Saturation.","page":"https://instructionsets.com/powerisa/maclhws/","api":"https://instructionsets.com/api/v1/powerisa/maclhws.json"},{"mnemonic":"maclhwsu","slug":"maclhwsu","records":1,"summary":"Mixed Sign Multiply Accumulate Low Halfword with Saturation.","page":"https://instructionsets.com/powerisa/maclhwsu/","api":"https://instructionsets.com/api/v1/powerisa/maclhwsu.json"},{"mnemonic":"maclhwu","slug":"maclhwu","records":1,"summary":"Unsigned Multiply Accumulate Low Halfword.","page":"https://instructionsets.com/powerisa/maclhwu/","api":"https://instructionsets.com/api/v1/powerisa/maclhwu.json"},{"mnemonic":"maddhd","slug":"maddhd","records":1,"summary":"Multiplies two 64-bit operands and adds the result to a third 64-bit operand, placing the high-order 64 bits of the sum into a target register.","page":"https://instructionsets.com/powerisa/maddhd/","api":"https://instructionsets.com/api/v1/powerisa/maddhd.json"},{"mnemonic":"mcrf","slug":"mcrf","records":1,"summary":"Copies the contents of one Condition Register field to another. Used to save comparison results.","page":"https://instructionsets.com/powerisa/mcrf/","api":"https://instructionsets.com/api/v1/powerisa/mcrf.json"},{"mnemonic":"mcrfs","slug":"mcrfs","records":1,"summary":"Moves a field from the Floating-Point Status and Control Register (FPSCR) to the Condition Register.","page":"https://instructionsets.com/powerisa/mcrfs/","api":"https://instructionsets.com/api/v1/powerisa/mcrfs.json"},{"mnemonic":"mcrxrx","slug":"mcrxrx","records":1,"summary":"Copies the contents of the XER register fields OV, OV32, CA, and CA32 to the specified condition register field.","page":"https://instructionsets.com/powerisa/mcrxrx/","api":"https://instructionsets.com/api/v1/powerisa/mcrxrx.json"},{"mnemonic":"mfbhrbe","slug":"mfbhrbe","records":1,"summary":"Reads a specific entry from the BHRB.","page":"https://instructionsets.com/powerisa/mfbhrbe/","api":"https://instructionsets.com/api/v1/powerisa/mfbhrbe.json"},{"mnemonic":"mfcr","slug":"mfcr","records":1,"summary":"Copies the entire 32-bit Condition Register into a General Purpose Register.","page":"https://instructionsets.com/powerisa/mfcr/","api":"https://instructionsets.com/api/v1/powerisa/mfcr.json"},{"mnemonic":"mfctr","slug":"mfctr","records":1,"summary":"Moves CTR to GPR. (Alias for 'mfspr RT, 9').","page":"https://instructionsets.com/powerisa/mfctr/","api":"https://instructionsets.com/api/v1/powerisa/mfctr.json"},{"mnemonic":"mfdcr","slug":"mfdcr","records":1,"summary":"Reads an on-chip peripheral register (DCR).","page":"https://instructionsets.com/powerisa/mfdcr/","api":"https://instructionsets.com/api/v1/powerisa/mfdcr.json"},{"mnemonic":"mffs","slug":"mffs","records":1,"summary":"Moves the contents of the Floating-Point Status and Control Register (FPSCR) into a floating-point register.","page":"https://instructionsets.com/powerisa/mffs/","api":"https://instructionsets.com/api/v1/powerisa/mffs.json"},{"mnemonic":"mffs.","slug":"mffs_","records":1,"summary":"Moves the contents of the Floating-Point Status and Control Register (FPSCR) into a floating-point register.","page":"https://instructionsets.com/powerisa/mffs_/","api":"https://instructionsets.com/api/v1/powerisa/mffs_.json"},{"mnemonic":"mffscdrn","slug":"mffscdrn","records":1,"summary":"Moves control bits from FPSCR to a register and sets the DRN field.","page":"https://instructionsets.com/powerisa/mffscdrn/","api":"https://instructionsets.com/api/v1/powerisa/mffscdrn.json"},{"mnemonic":"mffsl","slug":"mffsl","records":1,"summary":"Moves the control and non-sticky status bits from the FPSCR to a general-purpose register.","page":"https://instructionsets.com/powerisa/mffsl/","api":"https://instructionsets.com/api/v1/powerisa/mffsl.json"},{"mnemonic":"mflr","slug":"mflr","records":1,"summary":"Moves LR to GPR. (Alias for 'mfspr RT, 8').","page":"https://instructionsets.com/powerisa/mflr/","api":"https://instructionsets.com/api/v1/powerisa/mflr.json"},{"mnemonic":"mfmsr","slug":"mfmsr","records":1,"summary":"Moves the contents of the Machine State Register (MSR) into a general-purpose register.","page":"https://instructionsets.com/powerisa/mfmsr/","api":"https://instructionsets.com/api/v1/powerisa/mfmsr.json"},{"mnemonic":"mfocrf","slug":"mfocrf","records":1,"summary":"Moves a single CR field to a GPR.","page":"https://instructionsets.com/powerisa/mfocrf/","api":"https://instructionsets.com/api/v1/powerisa/mfocrf.json"},{"mnemonic":"mfpmr","slug":"mfpmr","records":1,"summary":"Reads a performance monitor register (Embedded).","page":"https://instructionsets.com/powerisa/mfpmr/","api":"https://instructionsets.com/api/v1/powerisa/mfpmr.json"},{"mnemonic":"mfpvr","slug":"mfpvr","records":1,"summary":"Reads the PVR (Processor ID).","page":"https://instructionsets.com/powerisa/mfpvr/","api":"https://instructionsets.com/api/v1/powerisa/mfpvr.json"},{"mnemonic":"mfspr","slug":"mfspr","records":1,"summary":"Moves the contents of a special purpose register into a general-purpose register.","page":"https://instructionsets.com/powerisa/mfspr/","api":"https://instructionsets.com/api/v1/powerisa/mfspr.json"},{"mnemonic":"mfsr","slug":"mfsr","records":1,"summary":"Legacy 32-bit segment register read.","page":"https://instructionsets.com/powerisa/mfsr/","api":"https://instructionsets.com/api/v1/powerisa/mfsr.json"},{"mnemonic":"mfsrin","slug":"mfsrin","records":1,"summary":"Indirect read of segment register using RB.","page":"https://instructionsets.com/powerisa/mfsrin/","api":"https://instructionsets.com/api/v1/powerisa/mfsrin.json"},{"mnemonic":"mftar","slug":"mftar","records":1,"summary":"Reads the TAR into a GPR.","page":"https://instructionsets.com/powerisa/mftar/","api":"https://instructionsets.com/api/v1/powerisa/mftar.json"},{"mnemonic":"mftb","slug":"mftb","records":1,"summary":"Moves the contents of the Time Base Register (TBR) into a general-purpose register.","page":"https://instructionsets.com/powerisa/mftb/","api":"https://instructionsets.com/api/v1/powerisa/mftb.json"},{"mnemonic":"mftbu","slug":"mftbu","records":1,"summary":"Reads the upper 32 bits of the Timebase (32-bit implementations).","page":"https://instructionsets.com/powerisa/mftbu/","api":"https://instructionsets.com/api/v1/powerisa/mftbu.json"},{"mnemonic":"mfvsrd","slug":"mfvsrd","records":1,"summary":"Moves the contents of a doubleword element from a Vector-Scalar Register (VSR) to a General Purpose Register (GPR).","page":"https://instructionsets.com/powerisa/mfvsrd/","api":"https://instructionsets.com/api/v1/powerisa/mfvsrd.json"},{"mnemonic":"mfvsrld","slug":"mfvsrld","records":1,"summary":"Moves the lower doubleword of a vector register to a general-purpose register.","page":"https://instructionsets.com/powerisa/mfvsrld/","api":"https://instructionsets.com/api/v1/powerisa/mfvsrld.json"},{"mnemonic":"mfvsrwz","slug":"mfvsrwz","records":1,"summary":"Moves the contents of a word element from a vector-scalar register to a general-purpose register, zeroing the upper bits.","page":"https://instructionsets.com/powerisa/mfvsrwz/","api":"https://instructionsets.com/api/v1/powerisa/mfvsrwz.json"},{"mnemonic":"modsd","slug":"modsd","records":1,"summary":"Calculates remainder of signed doubleword division.","page":"https://instructionsets.com/powerisa/modsd/","api":"https://instructionsets.com/api/v1/powerisa/modsd.json"},{"mnemonic":"modsq","slug":"modsq","records":1,"summary":"Computes remainder of 128-bit signed division.","page":"https://instructionsets.com/powerisa/modsq/","api":"https://instructionsets.com/api/v1/powerisa/modsq.json"},{"mnemonic":"modsw","slug":"modsw","records":1,"summary":"Calculates remainder of signed word division.","page":"https://instructionsets.com/powerisa/modsw/","api":"https://instructionsets.com/api/v1/powerisa/modsw.json"},{"mnemonic":"modud","slug":"modud","records":1,"summary":"Calculates remainder of unsigned doubleword division.","page":"https://instructionsets.com/powerisa/modud/","api":"https://instructionsets.com/api/v1/powerisa/modud.json"},{"mnemonic":"moduq","slug":"moduq","records":1,"summary":"Computes remainder of 128-bit unsigned division.","page":"https://instructionsets.com/powerisa/moduq/","api":"https://instructionsets.com/api/v1/powerisa/moduq.json"},{"mnemonic":"moduw","slug":"moduw","records":1,"summary":"Calculates remainder of unsigned word division.","page":"https://instructionsets.com/powerisa/moduw/","api":"https://instructionsets.com/api/v1/powerisa/moduw.json"},{"mnemonic":"mr","slug":"mr","records":1,"summary":"Copies contents of RS to RA. (Alias for 'or RA, RS, RS').","page":"https://instructionsets.com/powerisa/mr/","api":"https://instructionsets.com/api/v1/powerisa/mr.json"},{"mnemonic":"msgclr","slug":"msgclr","records":1,"summary":"Clears a pending doorbell interrupt (Inter-processor comms).","page":"https://instructionsets.com/powerisa/msgclr/","api":"https://instructionsets.com/api/v1/powerisa/msgclr.json"},{"mnemonic":"msgclrp","slug":"msgclrp","records":1,"summary":"Clears a privileged doorbell interrupt.","page":"https://instructionsets.com/powerisa/msgclrp/","api":"https://instructionsets.com/api/v1/powerisa/msgclrp.json"},{"mnemonic":"msgslp","slug":"msgslp","records":1,"summary":"Transitions the processor to a sleep state via message.","page":"https://instructionsets.com/powerisa/msgslp/","api":"https://instructionsets.com/api/v1/powerisa/msgslp.json"},{"mnemonic":"msgsnd","slug":"msgsnd","records":1,"summary":"Sends a doorbell interrupt to another processor.","page":"https://instructionsets.com/powerisa/msgsnd/","api":"https://instructionsets.com/api/v1/powerisa/msgsnd.json"},{"mnemonic":"msgsndp","slug":"msgsndp","records":1,"summary":"Sends a message to other threads on the same processor or sub-processor.","page":"https://instructionsets.com/powerisa/msgsndp/","api":"https://instructionsets.com/api/v1/powerisa/msgsndp.json"},{"mnemonic":"msgsndu","slug":"msgsndu","records":1,"summary":"Sends a message to other threads in the system.","page":"https://instructionsets.com/powerisa/msgsndu/","api":"https://instructionsets.com/api/v1/powerisa/msgsndu.json"},{"mnemonic":"msgsync","slug":"msgsync","records":1,"summary":"Provides an ordering function for stores relative to data accesses by other threads after a Directed Ultravisor Doorbell or Directed Hypervisor Doorbell interrupt.","page":"https://instructionsets.com/powerisa/msgsync/","api":"https://instructionsets.com/api/v1/powerisa/msgsync.json"},{"mnemonic":"msync","slug":"msync","records":1,"summary":"Synchronizes memory accesses (Alias for sync).","page":"https://instructionsets.com/powerisa/msync/","api":"https://instructionsets.com/api/v1/powerisa/msync.json"},{"mnemonic":"mtcrf","slug":"mtcrf","records":1,"summary":"Copies bits from a register into the Condition Register, updated only the fields specified by the mask (FXM).","page":"https://instructionsets.com/powerisa/mtcrf/","api":"https://instructionsets.com/api/v1/powerisa/mtcrf.json"},{"mnemonic":"mtctr","slug":"mtctr","records":1,"summary":"Moves GPR to CTR. (Alias for 'mtspr 9, RS').","page":"https://instructionsets.com/powerisa/mtctr/","api":"https://instructionsets.com/api/v1/powerisa/mtctr.json"},{"mnemonic":"mtdcr","slug":"mtdcr","records":1,"summary":"Writes an on-chip peripheral register (DCR).","page":"https://instructionsets.com/powerisa/mtdcr/","api":"https://instructionsets.com/api/v1/powerisa/mtdcr.json"},{"mnemonic":"mtfsb0","slug":"mtfsb0","records":1,"summary":"Clears a specific bit in the FPSCR.","page":"https://instructionsets.com/powerisa/mtfsb0/","api":"https://instructionsets.com/api/v1/powerisa/mtfsb0.json"},{"mnemonic":"mtfsb1","slug":"mtfsb1","records":1,"summary":"Sets a specific bit in the FPSCR.","page":"https://instructionsets.com/powerisa/mtfsb1/","api":"https://instructionsets.com/api/v1/powerisa/mtfsb1.json"},{"mnemonic":"mtfsf","slug":"mtfsf","records":1,"summary":"Moves the contents of a floating-point register into specified fields of the FPSCR.","page":"https://instructionsets.com/powerisa/mtfsf/","api":"https://instructionsets.com/api/v1/powerisa/mtfsf.json"},{"mnemonic":"mtfsf.","slug":"mtfsf_","records":1,"summary":"Moves the contents of a floating-point register into specified fields of the FPSCR.","page":"https://instructionsets.com/powerisa/mtfsf_/","api":"https://instructionsets.com/api/v1/powerisa/mtfsf_.json"},{"mnemonic":"mtfsfi","slug":"mtfsfi","records":1,"summary":"Writes a 4-bit immediate to a specific FPSCR field.","page":"https://instructionsets.com/powerisa/mtfsfi/","api":"https://instructionsets.com/api/v1/powerisa/mtfsfi.json"},{"mnemonic":"mtlr","slug":"mtlr","records":1,"summary":"Moves GPR to LR. (Alias for 'mtspr 8, RS').","page":"https://instructionsets.com/powerisa/mtlr/","api":"https://instructionsets.com/api/v1/powerisa/mtlr.json"},{"mnemonic":"mtmsr","slug":"mtmsr","records":1,"summary":"Sets the Machine State Register (MSR) based on the contents of a source register and a control bit.","page":"https://instructionsets.com/powerisa/mtmsr/","api":"https://instructionsets.com/api/v1/powerisa/mtmsr.json"},{"mnemonic":"mtmsrd","slug":"mtmsrd","records":1,"summary":"Sets the Machine State Register (MSR) based on the contents of a source register and an L field.","page":"https://instructionsets.com/powerisa/mtmsrd/","api":"https://instructionsets.com/api/v1/powerisa/mtmsrd.json"},{"mnemonic":"mtocrf","slug":"mtocrf","records":1,"summary":"Moves a GPR field to a single CR field.","page":"https://instructionsets.com/powerisa/mtocrf/","api":"https://instructionsets.com/api/v1/powerisa/mtocrf.json"},{"mnemonic":"mtpmr","slug":"mtpmr","records":1,"summary":"Writes a performance monitor register (Embedded).","page":"https://instructionsets.com/powerisa/mtpmr/","api":"https://instructionsets.com/api/v1/powerisa/mtpmr.json"},{"mnemonic":"mtspr","slug":"mtspr","records":1,"summary":"Copies a value from a general-purpose register to a system SPR (e.g., CTR, LR, XER).","page":"https://instructionsets.com/powerisa/mtspr/","api":"https://instructionsets.com/api/v1/powerisa/mtspr.json"},{"mnemonic":"mtsr","slug":"mtsr","records":1,"summary":"Legacy 32-bit segment register write.","page":"https://instructionsets.com/powerisa/mtsr/","api":"https://instructionsets.com/api/v1/powerisa/mtsr.json"},{"mnemonic":"mtsrin","slug":"mtsrin","records":1,"summary":"Indirect write of segment register using RB.","page":"https://instructionsets.com/powerisa/mtsrin/","api":"https://instructionsets.com/api/v1/powerisa/mtsrin.json"},{"mnemonic":"mttar","slug":"mttar","records":1,"summary":"Moves a GPR value to the TAR.","page":"https://instructionsets.com/powerisa/mttar/","api":"https://instructionsets.com/api/v1/powerisa/mttar.json"},{"mnemonic":"mtvscr","slug":"mtvscr","records":1,"summary":"Moves the contents of a vector register word into the VSCR.","page":"https://instructionsets.com/powerisa/mtvscr/","api":"https://instructionsets.com/api/v1/powerisa/mtvscr.json"},{"mnemonic":"mtvsrbm","slug":"mtvsrbm","records":1,"summary":"Moves a byte mask from a GPR to a VSR.","page":"https://instructionsets.com/powerisa/mtvsrbm/","api":"https://instructionsets.com/api/v1/powerisa/mtvsrbm.json"},{"mnemonic":"mtvsrbmi","slug":"mtvsrbmi","records":1,"summary":"Moves a bit mask immediate value into a vector scalar register, setting each byte element based on corresponding bits of the immediate.","page":"https://instructionsets.com/powerisa/mtvsrbmi/","api":"https://instructionsets.com/api/v1/powerisa/mtvsrbmi.json"},{"mnemonic":"mtvsrd","slug":"mtvsrd","records":1,"summary":"Moves 64 bits from a GPR to a VSR.","page":"https://instructionsets.com/powerisa/mtvsrd/","api":"https://instructionsets.com/api/v1/powerisa/mtvsrd.json"},{"mnemonic":"mtvsrdd","slug":"mtvsrdd","records":1,"summary":"Moves the contents of two general-purpose registers into a vector-scalar register (VSR) as doublewords.","page":"https://instructionsets.com/powerisa/mtvsrdd/","api":"https://instructionsets.com/api/v1/powerisa/mtvsrdd.json"},{"mnemonic":"mtvsrqm","slug":"mtvsrqm","records":1,"summary":"Moves a quadword mask from a general-purpose register to a vector scalar register.","page":"https://instructionsets.com/powerisa/mtvsrqm/","api":"https://instructionsets.com/api/v1/powerisa/mtvsrqm.json"},{"mnemonic":"mtvsrwa","slug":"mtvsrwa","records":1,"summary":"Moves the two's-complement integer in bits 32:63 of GPR[RA] to doubleword element 0 of VSR[XT], sign-extended to 64 bits.","page":"https://instructionsets.com/powerisa/mtvsrwa/","api":"https://instructionsets.com/api/v1/powerisa/mtvsrwa.json"},{"mnemonic":"mtvsrwm","slug":"mtvsrwm","records":1,"summary":"Moves a word mask from a general-purpose register to a vector scalar register.","page":"https://instructionsets.com/powerisa/mtvsrwm/","api":"https://instructionsets.com/api/v1/powerisa/mtvsrwm.json"},{"mnemonic":"mtvsrws","slug":"mtvsrws","records":1,"summary":"Moves a 32-bit word from a GPR and replicates it across the vector.","page":"https://instructionsets.com/powerisa/mtvsrws/","api":"https://instructionsets.com/api/v1/powerisa/mtvsrws.json"},{"mnemonic":"mulchw","slug":"mulchw","records":1,"summary":"Multiply bottom half of RA by top half of RB.","page":"https://instructionsets.com/powerisa/mulchw/","api":"https://instructionsets.com/api/v1/powerisa/mulchw.json"},{"mnemonic":"mulchwu","slug":"mulchwu","records":1,"summary":"Unsigned Multiply Cross Halfword.","page":"https://instructionsets.com/powerisa/mulchwu/","api":"https://instructionsets.com/api/v1/powerisa/mulchwu.json"},{"mnemonic":"mulhd","slug":"mulhd","records":1,"summary":"Multiplies two 64-bit integers and returns the upper 64 bits of the 128-bit result (Signed).","page":"https://instructionsets.com/powerisa/mulhd/","api":"https://instructionsets.com/api/v1/powerisa/mulhd.json"},{"mnemonic":"mulhd.","slug":"mulhd_","records":1,"summary":"Multiplies the contents of two registers and places the high-order 64 bits of the product into a target register.","page":"https://instructionsets.com/powerisa/mulhd_/","api":"https://instructionsets.com/api/v1/powerisa/mulhd_.json"},{"mnemonic":"mulhdu","slug":"mulhdu","records":1,"summary":"Multiplies two 64-bit integers and returns the upper 64 bits of the 128-bit result (Unsigned).","page":"https://instructionsets.com/powerisa/mulhdu/","api":"https://instructionsets.com/api/v1/powerisa/mulhdu.json"},{"mnemonic":"mulhhw","slug":"mulhhw","records":1,"summary":"Multiply top half of RA by top half of RB.","page":"https://instructionsets.com/powerisa/mulhhw/","api":"https://instructionsets.com/api/v1/powerisa/mulhhw.json"},{"mnemonic":"mulhhwu","slug":"mulhhwu","records":1,"summary":"Unsigned Multiply High Halfword.","page":"https://instructionsets.com/powerisa/mulhhwu/","api":"https://instructionsets.com/api/v1/powerisa/mulhhwu.json"},{"mnemonic":"mulhw","slug":"mulhw","records":1,"summary":"Multiplies two 32-bit integers and returns the upper 32 bits (Signed).","page":"https://instructionsets.com/powerisa/mulhw/","api":"https://instructionsets.com/api/v1/powerisa/mulhw.json"},{"mnemonic":"mulhwu","slug":"mulhwu","records":1,"summary":"Multiplies two 32-bit integers and returns the upper 32 bits (Unsigned).","page":"https://instructionsets.com/powerisa/mulhwu/","api":"https://instructionsets.com/api/v1/powerisa/mulhwu.json"},{"mnemonic":"mulld","slug":"mulld","records":1,"summary":"Multiplies the contents of two registers and places the low-order 64 bits of the product into a target register.","page":"https://instructionsets.com/powerisa/mulld/","api":"https://instructionsets.com/api/v1/powerisa/mulld.json"},{"mnemonic":"mulldo","slug":"mulldo","records":1,"summary":"Multiplies the contents of two registers and places the low-order 64 bits of the product into a target register.","page":"https://instructionsets.com/powerisa/mulldo/","api":"https://instructionsets.com/api/v1/powerisa/mulldo.json"},{"mnemonic":"mullhw","slug":"mullhw","records":1,"summary":"Multiply bottom half of RA by bottom half of RB.","page":"https://instructionsets.com/powerisa/mullhw/","api":"https://instructionsets.com/api/v1/powerisa/mullhw.json"},{"mnemonic":"mullhwu","slug":"mullhwu","records":1,"summary":"Unsigned Multiply Low Halfword.","page":"https://instructionsets.com/powerisa/mullhwu/","api":"https://instructionsets.com/api/v1/powerisa/mullhwu.json"},{"mnemonic":"mulli","slug":"mulli","records":1,"summary":"Multiplies the contents of a register by an immediate value and places the low-order 32 bits of the product into another register.","page":"https://instructionsets.com/powerisa/mulli/","api":"https://instructionsets.com/api/v1/powerisa/mulli.json"},{"mnemonic":"mullw","slug":"mullw","records":1,"summary":"Multiplies two 32-bit integers and stores the lower 32 bits of the 64-bit result.","page":"https://instructionsets.com/powerisa/mullw/","api":"https://instructionsets.com/api/v1/powerisa/mullw.json"},{"mnemonic":"nand","slug":"nand","records":1,"summary":"Bitwise NAND. RA = ~(RS & RB).","page":"https://instructionsets.com/powerisa/nand/","api":"https://instructionsets.com/api/v1/powerisa/nand.json"},{"mnemonic":"neg","slug":"neg","records":1,"summary":"Computes the two's complement negation of a register (0 - RT).","page":"https://instructionsets.com/powerisa/neg/","api":"https://instructionsets.com/api/v1/powerisa/neg.json"},{"mnemonic":"nmacchw","slug":"nmacchw","records":1,"summary":"Negate product of cross halfwords and add to accumulator.","page":"https://instructionsets.com/powerisa/nmacchw/","api":"https://instructionsets.com/api/v1/powerisa/nmacchw.json"},{"mnemonic":"nmacchws","slug":"nmacchws","records":1,"summary":"Negate product of cross halfwords and add to accumulator (Signed Saturation).","page":"https://instructionsets.com/powerisa/nmacchws/","api":"https://instructionsets.com/api/v1/powerisa/nmacchws.json"},{"mnemonic":"nmachhw","slug":"nmachhw","records":1,"summary":"Negate product of high halfwords and add to accumulator.","page":"https://instructionsets.com/powerisa/nmachhw/","api":"https://instructionsets.com/api/v1/powerisa/nmachhw.json"},{"mnemonic":"nmachhws","slug":"nmachhws","records":1,"summary":"Negate product of high halfwords and add to accumulator (Signed Saturation).","page":"https://instructionsets.com/powerisa/nmachhws/","api":"https://instructionsets.com/api/v1/powerisa/nmachhws.json"},{"mnemonic":"nmaclhw","slug":"nmaclhw","records":1,"summary":"Negate product of low halfwords and add to accumulator.","page":"https://instructionsets.com/powerisa/nmaclhw/","api":"https://instructionsets.com/api/v1/powerisa/nmaclhw.json"},{"mnemonic":"nmaclhws","slug":"nmaclhws","records":1,"summary":"Negate product of low halfwords and add to accumulator (Signed Saturation).","page":"https://instructionsets.com/powerisa/nmaclhws/","api":"https://instructionsets.com/api/v1/powerisa/nmaclhws.json"},{"mnemonic":"nop","slug":"nop","records":1,"summary":"Does nothing. (Alias for 'ori 0, 0, 0').","page":"https://instructionsets.com/powerisa/nop/","api":"https://instructionsets.com/api/v1/powerisa/nop.json"},{"mnemonic":"nor","slug":"nor","records":1,"summary":"Bitwise NOR. RA = ~(RS | RB).","page":"https://instructionsets.com/powerisa/nor/","api":"https://instructionsets.com/api/v1/powerisa/nor.json"},{"mnemonic":"not","slug":"not","records":1,"summary":"Complements the contents of one register and places the result into another register.","page":"https://instructionsets.com/powerisa/not/","api":"https://instructionsets.com/api/v1/powerisa/not.json"},{"mnemonic":"not.","slug":"not_","records":1,"summary":"Complements the contents of one register and places the result into another register.","page":"https://instructionsets.com/powerisa/not_/","api":"https://instructionsets.com/api/v1/powerisa/not_.json"},{"mnemonic":"or","slug":"or","records":1,"summary":"Performs a bitwise OR operation on the contents of two registers and places the result in a third register.","page":"https://instructionsets.com/powerisa/or/","api":"https://instructionsets.com/api/v1/powerisa/or.json"},{"mnemonic":"or.","slug":"or_","records":1,"summary":"Performs a bitwise OR operation on the contents of two registers and updates the condition register.","page":"https://instructionsets.com/powerisa/or_/","api":"https://instructionsets.com/api/v1/powerisa/or_.json"},{"mnemonic":"orc","slug":"orc","records":1,"summary":"Performs a bitwise OR operation between the contents of two registers and the complement of the third register.","page":"https://instructionsets.com/powerisa/orc/","api":"https://instructionsets.com/api/v1/powerisa/orc.json"},{"mnemonic":"orc.","slug":"orc_","records":1,"summary":"Performs a bitwise OR operation between the contents of two registers and the complement of the third register.","page":"https://instructionsets.com/powerisa/orc_/","api":"https://instructionsets.com/api/v1/powerisa/orc_.json"},{"mnemonic":"ori","slug":"ori","records":1,"summary":"Performs a bitwise OR operation between the contents of a register and an immediate value, placing the result in another register.","page":"https://instructionsets.com/powerisa/ori/","api":"https://instructionsets.com/api/v1/powerisa/ori.json"},{"mnemonic":"oris","slug":"oris","records":1,"summary":"Performs a bitwise OR with a 16-bit immediate shifted left by 16 bits.","page":"https://instructionsets.com/powerisa/oris/","api":"https://instructionsets.com/api/v1/powerisa/oris.json"},{"mnemonic":"paddi","slug":"paddi","records":1,"summary":"Adds 34-bit immediate.","page":"https://instructionsets.com/powerisa/paddi/","api":"https://instructionsets.com/api/v1/powerisa/paddi.json"},{"mnemonic":"paste","slug":"paste","records":1,"summary":"Transfers data from the copy buffer to a specified memory location.","page":"https://instructionsets.com/powerisa/paste/","api":"https://instructionsets.com/api/v1/powerisa/paste.json"},{"mnemonic":"paste.","slug":"paste_","records":1,"summary":"Paste operation that updates CR0 to indicate success/fail.","page":"https://instructionsets.com/powerisa/paste_/","api":"https://instructionsets.com/api/v1/powerisa/paste_.json"},{"mnemonic":"pdepd","slug":"pdepd","records":1,"summary":"Deposits bits from RS to RA under control of mask RB (Scalar).","page":"https://instructionsets.com/powerisa/pdepd/","api":"https://instructionsets.com/api/v1/powerisa/pdepd.json"},{"mnemonic":"pextd","slug":"pextd","records":1,"summary":"Extracts bits from a source register based on a mask and places them into the target register.","page":"https://instructionsets.com/powerisa/pextd/","api":"https://instructionsets.com/api/v1/powerisa/pextd.json"},{"mnemonic":"pla","slug":"pla","records":1,"summary":"Pseudo-instruction for paddi with R=1. Loads the address of a label.","page":"https://instructionsets.com/powerisa/pla/","api":"https://instructionsets.com/api/v1/powerisa/pla.json"},{"mnemonic":"plbz","slug":"plbz","records":1,"summary":"Loads a byte and zero-extends it, using a 34-bit offset.","page":"https://instructionsets.com/powerisa/plbz/","api":"https://instructionsets.com/api/v1/powerisa/plbz.json"},{"mnemonic":"pld","slug":"pld","records":1,"summary":"Loads a 64-bit value from memory using a 34-bit immediate offset (PC-relative or absolute).","page":"https://instructionsets.com/powerisa/pld/","api":"https://instructionsets.com/api/v1/powerisa/pld.json"},{"mnemonic":"plfd","slug":"plfd","records":1,"summary":"Loads a double-precision floating-point value from memory into a VSX register.","page":"https://instructionsets.com/powerisa/plfd/","api":"https://instructionsets.com/api/v1/powerisa/plfd.json"},{"mnemonic":"plh","slug":"plh","records":1,"summary":"Loads 16-bit halfword using 34-bit offset.","page":"https://instructionsets.com/powerisa/plh/","api":"https://instructionsets.com/api/v1/powerisa/plh.json"},{"mnemonic":"plha","slug":"plha","records":1,"summary":"Loads 16-bit halfword (Sign Extended) using 34-bit offset.","page":"https://instructionsets.com/powerisa/plha/","api":"https://instructionsets.com/api/v1/powerisa/plha.json"},{"mnemonic":"pli","slug":"pli","records":1,"summary":"Loads a 34-bit signed immediate into a register. (Replaces multiple 'lis/ori' instructions).","page":"https://instructionsets.com/powerisa/pli/","api":"https://instructionsets.com/api/v1/powerisa/pli.json"},{"mnemonic":"plq","slug":"plq","records":1,"summary":"Loads 128 bits into two GPRs using a 34-bit offset.","page":"https://instructionsets.com/powerisa/plq/","api":"https://instructionsets.com/api/v1/powerisa/plq.json"},{"mnemonic":"plwa","slug":"plwa","records":1,"summary":"Loads 32-bit word (Sign Extended) using 34-bit offset.","page":"https://instructionsets.com/powerisa/plwa/","api":"https://instructionsets.com/api/v1/powerisa/plwa.json"},{"mnemonic":"plwz","slug":"plwz","records":1,"summary":"Loads a 32-bit word and zero-extends it to 64 bits, using a 34-bit offset.","page":"https://instructionsets.com/powerisa/plwz/","api":"https://instructionsets.com/api/v1/powerisa/plwz.json"},{"mnemonic":"plxv","slug":"plxv","records":1,"summary":"Loads a 128-bit VSX vector from memory into a VSX register using a prefixed instruction with a large displacement.","page":"https://instructionsets.com/powerisa/plxv/","api":"https://instructionsets.com/api/v1/powerisa/plxv.json"},{"mnemonic":"plxvp","slug":"plxvp","records":1,"summary":"Loads a 256-bit vector pair with 34-bit offset.","page":"https://instructionsets.com/powerisa/plxvp/","api":"https://instructionsets.com/api/v1/powerisa/plxvp.json"},{"mnemonic":"pmxvbf16ger2","slug":"pmxvbf16ger2","records":1,"summary":"Matrix Multiply Assist (MMA) instruction. Computes ACC <- ACC + (A * B) using BF16 inputs.","page":"https://instructionsets.com/powerisa/pmxvbf16ger2/","api":"https://instructionsets.com/api/v1/powerisa/pmxvbf16ger2.json"},{"mnemonic":"pmxvbf16ger2np","slug":"pmxvbf16ger2np","records":1,"summary":"Performs a masked vector operation with bfloat16 elements using negative multiplication and positive accumulation.","page":"https://instructionsets.com/powerisa/pmxvbf16ger2np/","api":"https://instructionsets.com/api/v1/powerisa/pmxvbf16ger2np.json"},{"mnemonic":"pmxvf16ger2np","slug":"pmxvf16ger2np","records":1,"summary":"Performs a masked vector operation with negative multiplication and positive accumulation.","page":"https://instructionsets.com/powerisa/pmxvf16ger2np/","api":"https://instructionsets.com/api/v1/powerisa/pmxvf16ger2np.json"},{"mnemonic":"pmxvf16ger2pp","slug":"pmxvf16ger2pp","records":1,"summary":"Performs a prefixed masked VSX vector 16-bit floating-point GER rank-2 update with positive multiply and positive accumulate.","page":"https://instructionsets.com/powerisa/pmxvf16ger2pp/","api":"https://instructionsets.com/api/v1/powerisa/pmxvf16ger2pp.json"},{"mnemonic":"pmxvf32gernp","slug":"pmxvf32gernp","records":1,"summary":"Performs a masked vector operation with negative multiplication and positive accumulation.","page":"https://instructionsets.com/powerisa/pmxvf32gernp/","api":"https://instructionsets.com/api/v1/powerisa/pmxvf32gernp.json"},{"mnemonic":"pmxvf32gerpp","slug":"pmxvf32gerpp","records":1,"summary":"Performs a prefixed masked VSX vector 32-bit floating-point GER rank-1 update with positive multiply and positive accumulate.","page":"https://instructionsets.com/powerisa/pmxvf32gerpp/","api":"https://instructionsets.com/api/v1/powerisa/pmxvf32gerpp.json"},{"mnemonic":"pmxvf64ger","slug":"pmxvf64ger","records":1,"summary":"Masked version of Double-Precision MMA.","page":"https://instructionsets.com/powerisa/pmxvf64ger/","api":"https://instructionsets.com/api/v1/powerisa/pmxvf64ger.json"},{"mnemonic":"pmxvf64gernn","slug":"pmxvf64gernn","records":1,"summary":"Performs a prefixed masked VSX vector 64-bit floating-point GER (rank-1 update) with negative multiply and negative accumulate.","page":"https://instructionsets.com/powerisa/pmxvf64gernn/","api":"https://instructionsets.com/api/v1/powerisa/pmxvf64gernn.json"},{"mnemonic":"pmxvf64gernp","slug":"pmxvf64gernp","records":1,"summary":"Performs a masked vector floating-point operation with negative multiplication and positive accumulation.","page":"https://instructionsets.com/powerisa/pmxvf64gernp/","api":"https://instructionsets.com/api/v1/powerisa/pmxvf64gernp.json"},{"mnemonic":"pmxvi4ger8","slug":"pmxvi4ger8","records":1,"summary":"Masked 4-bit integer matrix multiply.","page":"https://instructionsets.com/powerisa/pmxvi4ger8/","api":"https://instructionsets.com/api/v1/powerisa/pmxvi4ger8.json"},{"mnemonic":"pmxvi4ger8pp","slug":"pmxvi4ger8pp","records":1,"summary":"Masked unsigned 4-bit integer matrix multiply.","page":"https://instructionsets.com/powerisa/pmxvi4ger8pp/","api":"https://instructionsets.com/api/v1/powerisa/pmxvi4ger8pp.json"},{"mnemonic":"pmxvi8ger4","slug":"pmxvi8ger4","records":1,"summary":"Masked version of 8-bit integer MMA.","page":"https://instructionsets.com/powerisa/pmxvi8ger4/","api":"https://instructionsets.com/api/v1/powerisa/pmxvi8ger4.json"},{"mnemonic":"pmxvi8ger4pp","slug":"pmxvi8ger4pp","records":1,"summary":"Performs a prefixed masked VSX vector 8-bit signed/unsigned integer GER rank-4 update with positive multiply and positive accumulate, adding the result to the accumulator.","page":"https://instructionsets.com/powerisa/pmxvi8ger4pp/","api":"https://instructionsets.com/api/v1/powerisa/pmxvi8ger4pp.json"},{"mnemonic":"pnop","slug":"pnop","records":1,"summary":"No operation is performed.","page":"https://instructionsets.com/powerisa/pnop/","api":"https://instructionsets.com/api/v1/powerisa/pnop.json"},{"mnemonic":"popcntb","slug":"popcntb","records":1,"summary":"Counts the number of one bits in each byte of a register.","page":"https://instructionsets.com/powerisa/popcntb/","api":"https://instructionsets.com/api/v1/powerisa/popcntb.json"},{"mnemonic":"popcntd","slug":"popcntd","records":1,"summary":"Counts the number of set bits (1s) in a 64-bit register.","page":"https://instructionsets.com/powerisa/popcntd/","api":"https://instructionsets.com/api/v1/powerisa/popcntd.json"},{"mnemonic":"popcntw","slug":"popcntw","records":1,"summary":"Counts the number of set bits (1s) in the lower 32 bits of a register.","page":"https://instructionsets.com/powerisa/popcntw/","api":"https://instructionsets.com/api/v1/powerisa/popcntw.json"},{"mnemonic":"prtyd","slug":"prtyd","records":1,"summary":"Calculates parity of a doubleword (Scalar).","page":"https://instructionsets.com/powerisa/prtyd/","api":"https://instructionsets.com/api/v1/powerisa/prtyd.json"},{"mnemonic":"prtyw","slug":"prtyw","records":1,"summary":"Calculates parity of a word (Scalar).","page":"https://instructionsets.com/powerisa/prtyw/","api":"https://instructionsets.com/api/v1/powerisa/prtyw.json"},{"mnemonic":"ps_add","slug":"ps_add","records":1,"summary":"Adds two paired singles.","page":"https://instructionsets.com/powerisa/ps_add/","api":"https://instructionsets.com/api/v1/powerisa/ps_add.json"},{"mnemonic":"ps_madd","slug":"ps_madd","records":1,"summary":"Multiply-Add on paired singles.","page":"https://instructionsets.com/powerisa/ps_madd/","api":"https://instructionsets.com/api/v1/powerisa/ps_madd.json"},{"mnemonic":"ps_mul","slug":"ps_mul","records":1,"summary":"Multiplies two paired singles.","page":"https://instructionsets.com/powerisa/ps_mul/","api":"https://instructionsets.com/api/v1/powerisa/ps_mul.json"},{"mnemonic":"ps_sub","slug":"ps_sub","records":1,"summary":"Subtracts two paired singles.","page":"https://instructionsets.com/powerisa/ps_sub/","api":"https://instructionsets.com/api/v1/powerisa/ps_sub.json"},{"mnemonic":"psq_l","slug":"psq_l","records":1,"summary":"Loads a paired single from memory (Embedded/Legacy).","page":"https://instructionsets.com/powerisa/psq_l/","api":"https://instructionsets.com/api/v1/powerisa/psq_l.json"},{"mnemonic":"psq_st","slug":"psq_st","records":1,"summary":"Stores a paired single to memory (Embedded/Legacy).","page":"https://instructionsets.com/powerisa/psq_st/","api":"https://instructionsets.com/api/v1/powerisa/psq_st.json"},{"mnemonic":"pstb","slug":"pstb","records":1,"summary":"Stores byte using 34-bit offset.","page":"https://instructionsets.com/powerisa/pstb/","api":"https://instructionsets.com/api/v1/powerisa/pstb.json"},{"mnemonic":"pstfd","slug":"pstfd","records":1,"summary":"Stores a double-precision floating-point value from a register to memory.","page":"https://instructionsets.com/powerisa/pstfd/","api":"https://instructionsets.com/api/v1/powerisa/pstfd.json"},{"mnemonic":"pstfs","slug":"pstfs","records":1,"summary":"Stores a single-precision floating-point value from a register to memory.","page":"https://instructionsets.com/powerisa/pstfs/","api":"https://instructionsets.com/api/v1/powerisa/pstfs.json"},{"mnemonic":"psth","slug":"psth","records":1,"summary":"Stores halfword using 34-bit offset.","page":"https://instructionsets.com/powerisa/psth/","api":"https://instructionsets.com/api/v1/powerisa/psth.json"},{"mnemonic":"pstq","slug":"pstq","records":1,"summary":"Stores 128 bits from two GPRs using a 34-bit offset.","page":"https://instructionsets.com/powerisa/pstq/","api":"https://instructionsets.com/api/v1/powerisa/pstq.json"},{"mnemonic":"pststd","slug":"pststd","records":1,"summary":"Stores a 64-bit value to memory using a 34-bit immediate offset.","page":"https://instructionsets.com/powerisa/pststd/","api":"https://instructionsets.com/api/v1/powerisa/pststd.json"},{"mnemonic":"pstw","slug":"pstw","records":1,"summary":"Stores word using 34-bit offset.","page":"https://instructionsets.com/powerisa/pstw/","api":"https://instructionsets.com/api/v1/powerisa/pstw.json"},{"mnemonic":"pstxvp","slug":"pstxvp","records":1,"summary":"Stores a 256-bit vector pair with 34-bit offset.","page":"https://instructionsets.com/powerisa/pstxvp/","api":"https://instructionsets.com/api/v1/powerisa/pstxvp.json"},{"mnemonic":"rfebb","slug":"rfebb","records":1,"summary":"Returns control to the address specified by EBBRR0:61 || 0b00 or 320 || EBBRR32:61 || 0b00, depending on MSRSF.","page":"https://instructionsets.com/powerisa/rfebb/","api":"https://instructionsets.com/api/v1/powerisa/rfebb.json"},{"mnemonic":"rfid","slug":"rfid","records":1,"summary":"Returns from an interrupt handler. Restores PC from SRR0 and MSR from SRR1.","page":"https://instructionsets.com/powerisa/rfid/","api":"https://instructionsets.com/api/v1/powerisa/rfid.json"},{"mnemonic":"rfscv","slug":"rfscv","records":1,"summary":"Returns from a vectored system call.","page":"https://instructionsets.com/powerisa/rfscv/","api":"https://instructionsets.com/api/v1/powerisa/rfscv.json"},{"mnemonic":"rldcr","slug":"rldcr","records":1,"summary":"Rotates the contents of register RS left by a variable number of bits specified by (RB)58:63, and clears the rightmost bits.","page":"https://instructionsets.com/powerisa/rldcr/","api":"https://instructionsets.com/api/v1/powerisa/rldcr.json"},{"mnemonic":"rldcr.","slug":"rldcr_","records":1,"summary":"Rotates the contents of register RS left by a variable number of bits specified by (RB)58:63, and clears the rightmost bits.","page":"https://instructionsets.com/powerisa/rldcr_/","api":"https://instructionsets.com/api/v1/powerisa/rldcr_.json"},{"mnemonic":"rldic","slug":"rldic","records":1,"summary":"Rotates a 64-bit register left, then clears bits based on a mask. 64-bit equivalent of rlwinm.","page":"https://instructionsets.com/powerisa/rldic/","api":"https://instructionsets.com/api/v1/powerisa/rldic.json"},{"mnemonic":"rldic.","slug":"rldic_","records":1,"summary":"Rotates a 64-bit register left, then clears bits based on a mask. 64-bit equivalent of rlwinm.","page":"https://instructionsets.com/powerisa/rldic_/","api":"https://instructionsets.com/api/v1/powerisa/rldic_.json"},{"mnemonic":"rldicl","slug":"rldicl","records":1,"summary":"Rotates the contents of a register left by a specified number of bits and clears higher-order bits.","page":"https://instructionsets.com/powerisa/rldicl/","api":"https://instructionsets.com/api/v1/powerisa/rldicl.json"},{"mnemonic":"rldicr","slug":"rldicr","records":1,"summary":"Rotates 64-bit RS left by SH, then clears the low-order bits (ME+1 to 63).","page":"https://instructionsets.com/powerisa/rldicr/","api":"https://instructionsets.com/api/v1/powerisa/rldicr.json"},{"mnemonic":"rldimi","slug":"rldimi","records":1,"summary":"Rotates 64-bit value and inserts into target under mask.","page":"https://instructionsets.com/powerisa/rldimi/","api":"https://instructionsets.com/api/v1/powerisa/rldimi.json"},{"mnemonic":"rlwimi","slug":"rlwimi","records":1,"summary":"Rotates a word left, then inserts bits into the target under a mask. Used for inserting bitfields.","page":"https://instructionsets.com/powerisa/rlwimi/","api":"https://instructionsets.com/api/v1/powerisa/rlwimi.json"},{"mnemonic":"rlwinm","slug":"rlwinm","records":1,"summary":"Rotates the low-order 32 bits of a register left by a specified number of bit positions, generates a mask, and performs an AND operation.","page":"https://instructionsets.com/powerisa/rlwinm/","api":"https://instructionsets.com/api/v1/powerisa/rlwinm.json"},{"mnemonic":"rlwinm.","slug":"rlwinm_","records":1,"summary":"Rotates the low-order 32 bits of a register left by a specified number of bit positions, generates a mask, and performs an AND operation.","page":"https://instructionsets.com/powerisa/rlwinm_/","api":"https://instructionsets.com/api/v1/powerisa/rlwinm_.json"},{"mnemonic":"rlwnm","slug":"rlwnm","records":1,"summary":"Rotates the contents of register RS left by the number of bits specified by (RB)59:63, and then performs a bitwise AND operation with a mask.","page":"https://instructionsets.com/powerisa/rlwnm/","api":"https://instructionsets.com/api/v1/powerisa/rlwnm.json"},{"mnemonic":"rlwnm.","slug":"rlwnm_","records":1,"summary":"Rotates the contents of register RS left by the number of bits specified by (RB)59:63, and then performs a bitwise AND operation with a mask.","page":"https://instructionsets.com/powerisa/rlwnm_/","api":"https://instructionsets.com/api/v1/powerisa/rlwnm_.json"},{"mnemonic":"sc","slug":"sc","records":1,"summary":"Provides the means by which a program can call upon the system to perform a service.","page":"https://instructionsets.com/powerisa/sc/","api":"https://instructionsets.com/api/v1/powerisa/sc.json"},{"mnemonic":"scv","slug":"scv","records":1,"summary":"Performs a system call to a fixed vector address (Faster than 'sc').","page":"https://instructionsets.com/powerisa/scv/","api":"https://instructionsets.com/api/v1/powerisa/scv.json"},{"mnemonic":"setb","slug":"setb","records":1,"summary":"Sets the target register based on the condition register field BFA.","page":"https://instructionsets.com/powerisa/setb/","api":"https://instructionsets.com/api/v1/powerisa/setb.json"},{"mnemonic":"setbc","slug":"setbc","records":1,"summary":"Sets RT to 1 if CR bit is set, else 0. (Branchless logic).","page":"https://instructionsets.com/powerisa/setbc/","api":"https://instructionsets.com/api/v1/powerisa/setbc.json"},{"mnemonic":"setbcr","slug":"setbcr","records":1,"summary":"Sets RT to 1 if CR bit is clear, else 0.","page":"https://instructionsets.com/powerisa/setbcr/","api":"https://instructionsets.com/api/v1/powerisa/setbcr.json"},{"mnemonic":"setnbc","slug":"setnbc","records":1,"summary":"Sets RT to -1 if CR bit is set, else 0.","page":"https://instructionsets.com/powerisa/setnbc/","api":"https://instructionsets.com/api/v1/powerisa/setnbc.json"},{"mnemonic":"setnbcr","slug":"setnbcr","records":1,"summary":"Sets RT to -1 if CR bit is clear, else 0.","page":"https://instructionsets.com/powerisa/setnbcr/","api":"https://instructionsets.com/api/v1/powerisa/setnbcr.json"},{"mnemonic":"slbfee.","slug":"slbfee_","records":1,"summary":"Searches the SLB for an entry that matches the effective address specified by register RB.","page":"https://instructionsets.com/powerisa/slbfee_/","api":"https://instructionsets.com/api/v1/powerisa/slbfee_.json"},{"mnemonic":"slbia","slug":"slbia","records":1,"summary":"Invalidates all Segment Lookaside Buffer entries (OS Management).","page":"https://instructionsets.com/powerisa/slbia/","api":"https://instructionsets.com/api/v1/powerisa/slbia.json"},{"mnemonic":"slbiag","slug":"slbiag","records":1,"summary":"Invalidates all SLBs for a specified LPID and PID.","page":"https://instructionsets.com/powerisa/slbiag/","api":"https://instructionsets.com/api/v1/powerisa/slbiag.json"},{"mnemonic":"slbie","slug":"slbie","records":1,"summary":"Invalidates an SLB entry. Critical for memory management on Power systems.","page":"https://instructionsets.com/powerisa/slbie/","api":"https://instructionsets.com/api/v1/powerisa/slbie.json"},{"mnemonic":"slbieg","slug":"slbieg","records":1,"summary":"Invalidates SLB entries based on the contents of registers RS and RB.","page":"https://instructionsets.com/powerisa/slbieg/","api":"https://instructionsets.com/api/v1/powerisa/slbieg.json"},{"mnemonic":"slbmfee","slug":"slbmfee","records":1,"summary":"Reads the ESID part of an SLB entry.","page":"https://instructionsets.com/powerisa/slbmfee/","api":"https://instructionsets.com/api/v1/powerisa/slbmfee.json"},{"mnemonic":"slbmfev","slug":"slbmfev","records":1,"summary":"Reads software-loaded SLB entries and places the contents of the B, VSID, Ks, Kp, N, L, C, and LP fields into register RT.","page":"https://instructionsets.com/powerisa/slbmfev/","api":"https://instructionsets.com/api/v1/powerisa/slbmfev.json"},{"mnemonic":"slbmte","slug":"slbmte","records":1,"summary":"Writes an SLB entry (Mapping effective to virtual address).","page":"https://instructionsets.com/powerisa/slbmte/","api":"https://instructionsets.com/api/v1/powerisa/slbmte.json"},{"mnemonic":"slbsync","slug":"slbsync","records":1,"summary":"Provides an ordering function for the effects of all slbieg and slbiag instructions executed by the thread executing the slbsync instruction.","page":"https://instructionsets.com/powerisa/slbsync/","api":"https://instructionsets.com/api/v1/powerisa/slbsync.json"},{"mnemonic":"sld","slug":"sld","records":1,"summary":"Shifts a 64-bit register left by the amount specified in RB.","page":"https://instructionsets.com/powerisa/sld/","api":"https://instructionsets.com/api/v1/powerisa/sld.json"},{"mnemonic":"slw","slug":"slw","records":1,"summary":"Shifts a 32-bit register left by the amount specified in RB.","page":"https://instructionsets.com/powerisa/slw/","api":"https://instructionsets.com/api/v1/powerisa/slw.json"},{"mnemonic":"slw.","slug":"slw_","records":1,"summary":"Shifts the contents of a register left by a specified number of bits and updates the condition register.","page":"https://instructionsets.com/powerisa/slw_/","api":"https://instructionsets.com/api/v1/powerisa/slw_.json"},{"mnemonic":"srad","slug":"srad","records":1,"summary":"Arithmetic right shift of 64-bit value (preserves sign).","page":"https://instructionsets.com/powerisa/srad/","api":"https://instructionsets.com/api/v1/powerisa/srad.json"},{"mnemonic":"srad.","slug":"srad_","records":1,"summary":"Shifts the contents of a doubleword register right algebraically, shifting in sign bits.","page":"https://instructionsets.com/powerisa/srad_/","api":"https://instructionsets.com/api/v1/powerisa/srad_.json"},{"mnemonic":"sradi","slug":"sradi","records":1,"summary":"Performs an arithmetic right shift on a 64-bit doubleword by a constant amount.","page":"https://instructionsets.com/powerisa/sradi/","api":"https://instructionsets.com/api/v1/powerisa/sradi.json"},{"mnemonic":"sraw","slug":"sraw","records":1,"summary":"Performs an arithmetic right shift (sign bit replicated) on a 32-bit word. Updates Carry (CA) if bits are shifted out.","page":"https://instructionsets.com/powerisa/sraw/","api":"https://instructionsets.com/api/v1/powerisa/sraw.json"},{"mnemonic":"srawi","slug":"srawi","records":1,"summary":"Shifts the contents of a register right by an immediate value and replicates the sign bit.","page":"https://instructionsets.com/powerisa/srawi/","api":"https://instructionsets.com/api/v1/powerisa/srawi.json"},{"mnemonic":"srd","slug":"srd","records":1,"summary":"Logical right shift of 64-bit value.","page":"https://instructionsets.com/powerisa/srd/","api":"https://instructionsets.com/api/v1/powerisa/srd.json"},{"mnemonic":"srw","slug":"srw","records":1,"summary":"Performs a logical right shift (zeros shifted in) on a 32-bit word.","page":"https://instructionsets.com/powerisa/srw/","api":"https://instructionsets.com/api/v1/powerisa/srw.json"},{"mnemonic":"stb","slug":"stb","records":1,"summary":"Stores the low 8 bits of a register to memory.","page":"https://instructionsets.com/powerisa/stb/","api":"https://instructionsets.com/api/v1/powerisa/stb.json"},{"mnemonic":"stbci","slug":"stbci","records":1,"summary":"Stores a byte bypassing the cache.","page":"https://instructionsets.com/powerisa/stbci/","api":"https://instructionsets.com/api/v1/powerisa/stbci.json"},{"mnemonic":"stbcix","slug":"stbcix","records":1,"summary":"Stores a byte from a register to memory with caching inhibited and guarded.","page":"https://instructionsets.com/powerisa/stbcix/","api":"https://instructionsets.com/api/v1/powerisa/stbcix.json"},{"mnemonic":"stbcx.","slug":"stbcx_","records":1,"summary":"Stores a byte from a register to memory if the reservation is valid and matches the address.","page":"https://instructionsets.com/powerisa/stbcx_/","api":"https://instructionsets.com/api/v1/powerisa/stbcx_.json"},{"mnemonic":"stbepx","slug":"stbepx","records":1,"summary":"Stores a byte using the External PID.","page":"https://instructionsets.com/powerisa/stbepx/","api":"https://instructionsets.com/api/v1/powerisa/stbepx.json"},{"mnemonic":"std","slug":"std","records":1,"summary":"Stores a 64-bit doubleword to memory.","page":"https://instructionsets.com/powerisa/std/","api":"https://instructionsets.com/api/v1/powerisa/std.json"},{"mnemonic":"stdbrx","slug":"stdbrx","records":1,"summary":"Swaps bytes and stores 64 bits.","page":"https://instructionsets.com/powerisa/stdbrx/","api":"https://instructionsets.com/api/v1/powerisa/stdbrx.json"},{"mnemonic":"stdci","slug":"stdci","records":1,"summary":"Stores a doubleword bypassing the cache.","page":"https://instructionsets.com/powerisa/stdci/","api":"https://instructionsets.com/api/v1/powerisa/stdci.json"},{"mnemonic":"stdcx.","slug":"stdcx_","records":1,"summary":"Stores a doubleword from a register to memory if the reservation is valid and matches the address used for the reservation.","page":"https://instructionsets.com/powerisa/stdcx_/","api":"https://instructionsets.com/api/v1/powerisa/stdcx_.json"},{"mnemonic":"stdi","slug":"stdi","records":1,"summary":"Stores a word and sends decoration sideband signals.","page":"https://instructionsets.com/powerisa/stdi/","api":"https://instructionsets.com/api/v1/powerisa/stdi.json"},{"mnemonic":"stdu","slug":"stdu","records":1,"summary":"Stores a doubleword from a register to memory and updates the base address register.","page":"https://instructionsets.com/powerisa/stdu/","api":"https://instructionsets.com/api/v1/powerisa/stdu.json"},{"mnemonic":"stdx","slug":"stdx","records":1,"summary":"Stores a doubleword from a register to memory using an indexed address.","page":"https://instructionsets.com/powerisa/stdx/","api":"https://instructionsets.com/api/v1/powerisa/stdx.json"},{"mnemonic":"stfd","slug":"stfd","records":1,"summary":"Stores a double-precision floating-point value from a register to memory.","page":"https://instructionsets.com/powerisa/stfd/","api":"https://instructionsets.com/api/v1/powerisa/stfd.json"},{"mnemonic":"stfdp","slug":"stfdp","records":1,"summary":"Stores the contents of two floating-point registers into memory as a doubleword pair.","page":"https://instructionsets.com/powerisa/stfdp/","api":"https://instructionsets.com/api/v1/powerisa/stfdp.json"},{"mnemonic":"stfdux","slug":"stfdux","records":1,"summary":"Stores the contents of a floating-point register into memory and updates the base address register.","page":"https://instructionsets.com/powerisa/stfdux/","api":"https://instructionsets.com/api/v1/powerisa/stfdux.json"},{"mnemonic":"stfs","slug":"stfs","records":1,"summary":"Stores a single-precision floating-point value from an FPR to memory.","page":"https://instructionsets.com/powerisa/stfs/","api":"https://instructionsets.com/api/v1/powerisa/stfs.json"},{"mnemonic":"stfsx","slug":"stfsx","records":1,"summary":"Stores a single-precision floating-point value from a register to memory using an indexed address.","page":"https://instructionsets.com/powerisa/stfsx/","api":"https://instructionsets.com/api/v1/powerisa/stfsx.json"},{"mnemonic":"sth","slug":"sth","records":1,"summary":"Stores the high half of a doubleword from a register to memory.","page":"https://instructionsets.com/powerisa/sth/","api":"https://instructionsets.com/api/v1/powerisa/sth.json"},{"mnemonic":"sthbrx","slug":"sthbrx","records":1,"summary":"Swaps bytes and stores a halfword.","page":"https://instructionsets.com/powerisa/sthbrx/","api":"https://instructionsets.com/api/v1/powerisa/sthbrx.json"},{"mnemonic":"sthci","slug":"sthci","records":1,"summary":"Stores a halfword bypassing the cache.","page":"https://instructionsets.com/powerisa/sthci/","api":"https://instructionsets.com/api/v1/powerisa/sthci.json"},{"mnemonic":"sthcix","slug":"sthcix","records":1,"summary":"Stores a halfword from a general-purpose register to memory, with caching inhibited.","page":"https://instructionsets.com/powerisa/sthcix/","api":"https://instructionsets.com/api/v1/powerisa/sthcix.json"},{"mnemonic":"sthcx.","slug":"sthcx_","records":1,"summary":"Stores a halfword from a register to memory conditionally based on a reservation.","page":"https://instructionsets.com/powerisa/sthcx_/","api":"https://instructionsets.com/api/v1/powerisa/sthcx_.json"},{"mnemonic":"sthep","slug":"sthep","records":1,"summary":"Stores a halfword using the External PID.","page":"https://instructionsets.com/powerisa/sthep/","api":"https://instructionsets.com/api/v1/powerisa/sthep.json"},{"mnemonic":"stmw","slug":"stmw","records":1,"summary":"Stores words from registers RT through R31 to memory (Context Switch).","page":"https://instructionsets.com/powerisa/stmw/","api":"https://instructionsets.com/api/v1/powerisa/stmw.json"},{"mnemonic":"stop","slug":"stop","records":1,"summary":"Stops instruction execution and enters a power-saving state (replaces nap/doze on P9+).","page":"https://instructionsets.com/powerisa/stop/","api":"https://instructionsets.com/api/v1/powerisa/stop.json"},{"mnemonic":"stq","slug":"stq","records":1,"summary":"Stores a quadword from two general-purpose registers into memory.","page":"https://instructionsets.com/powerisa/stq/","api":"https://instructionsets.com/api/v1/powerisa/stq.json"},{"mnemonic":"stqcx.","slug":"stqcx_","records":1,"summary":"Stores a quadword from a register to memory if a reservation exists and the conditions are met.","page":"https://instructionsets.com/powerisa/stqcx_/","api":"https://instructionsets.com/api/v1/powerisa/stqcx_.json"},{"mnemonic":"stswi","slug":"stswi","records":1,"summary":"Stores a string of words from general-purpose registers to memory, starting at the address in RA and using an immediate byte count.","page":"https://instructionsets.com/powerisa/stswi/","api":"https://instructionsets.com/api/v1/powerisa/stswi.json"},{"mnemonic":"stswx","slug":"stswx","records":1,"summary":"Stores N bytes to memory (N in XER).","page":"https://instructionsets.com/powerisa/stswx/","api":"https://instructionsets.com/api/v1/powerisa/stswx.json"},{"mnemonic":"stvebx","slug":"stvebx","records":1,"summary":"Stores a byte element from a vector register into memory.","page":"https://instructionsets.com/powerisa/stvebx/","api":"https://instructionsets.com/api/v1/powerisa/stvebx.json"},{"mnemonic":"stvehx","slug":"stvehx","records":1,"summary":"Stores a halfword element from a vector register to memory.","page":"https://instructionsets.com/powerisa/stvehx/","api":"https://instructionsets.com/api/v1/powerisa/stvehx.json"},{"mnemonic":"stvx","slug":"stvx","records":1,"summary":"Stores a quadword from a vector register to memory at an address formed by adding two general-purpose registers.","page":"https://instructionsets.com/powerisa/stvx/","api":"https://instructionsets.com/api/v1/powerisa/stvx.json"},{"mnemonic":"stvxl","slug":"stvxl","records":1,"summary":"Stores a vector element to memory, with the last element being stored if the index is out of bounds.","page":"https://instructionsets.com/powerisa/stvxl/","api":"https://instructionsets.com/api/v1/powerisa/stvxl.json"},{"mnemonic":"stw","slug":"stw","records":1,"summary":"Stores the low 32 bits of a register to memory.","page":"https://instructionsets.com/powerisa/stw/","api":"https://instructionsets.com/api/v1/powerisa/stw.json"},{"mnemonic":"stwat","slug":"stwat","records":1,"summary":"Stores a word atomically to memory.","page":"https://instructionsets.com/powerisa/stwat/","api":"https://instructionsets.com/api/v1/powerisa/stwat.json"},{"mnemonic":"stwbrx","slug":"stwbrx","records":1,"summary":"Swaps bytes and stores a word.","page":"https://instructionsets.com/powerisa/stwbrx/","api":"https://instructionsets.com/api/v1/powerisa/stwbrx.json"},{"mnemonic":"stwci","slug":"stwci","records":1,"summary":"Stores a word bypassing the cache.","page":"https://instructionsets.com/powerisa/stwci/","api":"https://instructionsets.com/api/v1/powerisa/stwci.json"},{"mnemonic":"stwcix","slug":"stwcix","records":1,"summary":"Stores a word from a source register to memory with caching inhibited.","page":"https://instructionsets.com/powerisa/stwcix/","api":"https://instructionsets.com/api/v1/powerisa/stwcix.json"},{"mnemonic":"stwcx.","slug":"stwcx_","records":1,"summary":"Stores a word from a register to memory if the reservation is valid and matches the address used in the corresponding lwarx instruction.","page":"https://instructionsets.com/powerisa/stwcx_/","api":"https://instructionsets.com/api/v1/powerisa/stwcx_.json"},{"mnemonic":"stwepx","slug":"stwepx","records":1,"summary":"Stores a word using the External PID.","page":"https://instructionsets.com/powerisa/stwepx/","api":"https://instructionsets.com/api/v1/powerisa/stwepx.json"},{"mnemonic":"stxsd","slug":"stxsd","records":1,"summary":"Stores the contents of doubleword element 0 of VSR[XS] to memory.","page":"https://instructionsets.com/powerisa/stxsd/","api":"https://instructionsets.com/api/v1/powerisa/stxsd.json"},{"mnemonic":"stxsdx","slug":"stxsdx","records":1,"summary":"Stores a doubleword from a VSX scalar register to memory.","page":"https://instructionsets.com/powerisa/stxsdx/","api":"https://instructionsets.com/api/v1/powerisa/stxsdx.json"},{"mnemonic":"stxsibx","slug":"stxsibx","records":1,"summary":"Stores a byte from a VSX scalar register into memory at an address formed by adding two general-purpose registers.","page":"https://instructionsets.com/powerisa/stxsibx/","api":"https://instructionsets.com/api/v1/powerisa/stxsibx.json"},{"mnemonic":"stxsiwx","slug":"stxsiwx","records":1,"summary":"Stores a single-precision floating-point value from a VSX register into memory, indexed by another register.","page":"https://instructionsets.com/powerisa/stxsiwx/","api":"https://instructionsets.com/api/v1/powerisa/stxsiwx.json"},{"mnemonic":"stxssp","slug":"stxssp","records":1,"summary":"Stores a single-precision floating-point value from a VSX register to memory.","page":"https://instructionsets.com/powerisa/stxssp/","api":"https://instructionsets.com/api/v1/powerisa/stxssp.json"},{"mnemonic":"stxsspx","slug":"stxsspx","records":1,"summary":"Stores a single-precision floating-point value from a VSX register to memory.","page":"https://instructionsets.com/powerisa/stxsspx/","api":"https://instructionsets.com/api/v1/powerisa/stxsspx.json"},{"mnemonic":"stxv","slug":"stxv","records":1,"summary":"Stores a 128-bit vector to memory (VSX aligned offset).","page":"https://instructionsets.com/powerisa/stxv/","api":"https://instructionsets.com/api/v1/powerisa/stxv.json"},{"mnemonic":"stxvb16x","slug":"stxvb16x","records":1,"summary":"Stores a vector of 16 byte elements from VSR[XS] into Big-Endian storage using stxvb16x, retaining left-to-right element ordering.","page":"https://instructionsets.com/powerisa/stxvb16x/","api":"https://instructionsets.com/api/v1/powerisa/stxvb16x.json"},{"mnemonic":"stxvd2x","slug":"stxvd2x","records":1,"summary":"Stores a 128-bit VSX register to memory. Does NOT require alignment.","page":"https://instructionsets.com/powerisa/stxvd2x/","api":"https://instructionsets.com/api/v1/powerisa/stxvd2x.json"},{"mnemonic":"stxvh8x","slug":"stxvh8x","records":1,"summary":"Stores a vector of 8 halfword elements from VSR[X] into memory using indexed addressing.","page":"https://instructionsets.com/powerisa/stxvh8x/","api":"https://instructionsets.com/api/v1/powerisa/stxvh8x.json"},{"mnemonic":"stxvl","slug":"stxvl","records":1,"summary":"Stores a specified number of bytes from a VSX vector register to memory.","page":"https://instructionsets.com/powerisa/stxvl/","api":"https://instructionsets.com/api/v1/powerisa/stxvl.json"},{"mnemonic":"stxvll","slug":"stxvll","records":1,"summary":"Stores a left-justified vector from a VSX register to memory.","page":"https://instructionsets.com/powerisa/stxvll/","api":"https://instructionsets.com/api/v1/powerisa/stxvll.json"},{"mnemonic":"stxvp","slug":"stxvp","records":1,"summary":"Stores a pair of VSX vector registers to memory.","page":"https://instructionsets.com/powerisa/stxvp/","api":"https://instructionsets.com/api/v1/powerisa/stxvp.json"},{"mnemonic":"stxvpx","slug":"stxvpx","records":1,"summary":"Stores a vector from two VSR registers into memory at the effective address.","page":"https://instructionsets.com/powerisa/stxvpx/","api":"https://instructionsets.com/api/v1/powerisa/stxvpx.json"},{"mnemonic":"stxvrbx","slug":"stxvrbx","records":1,"summary":"Stores the rightmost byte of a VSX vector element to memory.","page":"https://instructionsets.com/powerisa/stxvrbx/","api":"https://instructionsets.com/api/v1/powerisa/stxvrbx.json"},{"mnemonic":"stxvrdx","slug":"stxvrdx","records":1,"summary":"Stores the rightmost doubleword of a VSX vector register to memory.","page":"https://instructionsets.com/powerisa/stxvrdx/","api":"https://instructionsets.com/api/v1/powerisa/stxvrdx.json"},{"mnemonic":"stxvrhx","slug":"stxvrhx","records":1,"summary":"Stores the rightmost halfword of a VSX vector element to memory.","page":"https://instructionsets.com/powerisa/stxvrhx/","api":"https://instructionsets.com/api/v1/powerisa/stxvrhx.json"},{"mnemonic":"stxvw4x","slug":"stxvw4x","records":1,"summary":"Stores four words from a vector (unaligned).","page":"https://instructionsets.com/powerisa/stxvw4x/","api":"https://instructionsets.com/api/v1/powerisa/stxvw4x.json"},{"mnemonic":"stxvx","slug":"stxvx","records":1,"summary":"Stores a vector element from the VSX register file to memory.","page":"https://instructionsets.com/powerisa/stxvx/","api":"https://instructionsets.com/api/v1/powerisa/stxvx.json"},{"mnemonic":"subf","slug":"subf","records":1,"summary":"Subtracts the contents of register RA from register RB and places the result in RT.","page":"https://instructionsets.com/powerisa/subf/","api":"https://instructionsets.com/api/v1/powerisa/subf.json"},{"mnemonic":"subf.","slug":"subf_","records":1,"summary":"Subtracts the contents of register RA from register RB and places the result in RT.","page":"https://instructionsets.com/powerisa/subf_/","api":"https://instructionsets.com/api/v1/powerisa/subf_.json"},{"mnemonic":"subfc.","slug":"subfc_","records":1,"summary":"Subtracts the contents of one register from the complement of another and updates the carry-out flag.","page":"https://instructionsets.com/powerisa/subfc_/","api":"https://instructionsets.com/api/v1/powerisa/subfc_.json"},{"mnemonic":"subfo","slug":"subfo","records":1,"summary":"Subtracts the contents of register RA from register RB and places the result in RT.","page":"https://instructionsets.com/powerisa/subfo/","api":"https://instructionsets.com/api/v1/powerisa/subfo.json"},{"mnemonic":"subfo.","slug":"subfo_","records":1,"summary":"Subtracts the contents of register RA from register RB and places the result in RT.","page":"https://instructionsets.com/powerisa/subfo_/","api":"https://instructionsets.com/api/v1/powerisa/subfo_.json"},{"mnemonic":"sync","slug":"sync","records":1,"summary":"Ensures that all instructions preceding the sync instruction have completed before the sync instruction completes, and no subsequent instructions are initiated until after the sync instruction completes.","page":"https://instructionsets.com/powerisa/sync/","api":"https://instructionsets.com/api/v1/powerisa/sync.json"},{"mnemonic":"tabort.","slug":"tabort_","records":1,"summary":"Forces a transaction failure and rollback.","page":"https://instructionsets.com/powerisa/tabort_/","api":"https://instructionsets.com/api/v1/powerisa/tabort_.json"},{"mnemonic":"tabortdc","slug":"tabortdc","records":1,"summary":"Aborts a transaction if the condition is met (Doubleword comparison).","page":"https://instructionsets.com/powerisa/tabortdc/","api":"https://instructionsets.com/api/v1/powerisa/tabortdc.json"},{"mnemonic":"tabortdci","slug":"tabortdci","records":1,"summary":"Aborts transaction if doubleword condition (Immediate) is met.","page":"https://instructionsets.com/powerisa/tabortdci/","api":"https://instructionsets.com/api/v1/powerisa/tabortdci.json"},{"mnemonic":"tabortwc","slug":"tabortwc","records":1,"summary":"Aborts a transaction if the condition is met (Word comparison).","page":"https://instructionsets.com/powerisa/tabortwc/","api":"https://instructionsets.com/api/v1/powerisa/tabortwc.json"},{"mnemonic":"tabortwci","slug":"tabortwci","records":1,"summary":"Aborts transaction if word condition (Immediate) is met.","page":"https://instructionsets.com/powerisa/tabortwci/","api":"https://instructionsets.com/api/v1/powerisa/tabortwci.json"},{"mnemonic":"tbegin.","slug":"tbegin_","records":1,"summary":"Initiates a hardware transaction. If the transaction fails, execution rolls back to this point. Sets CR0 based on success/failure.","page":"https://instructionsets.com/powerisa/tbegin_/","api":"https://instructionsets.com/api/v1/powerisa/tbegin_.json"},{"mnemonic":"tcheck","slug":"tcheck","records":1,"summary":"Checks transaction status and updates CR.","page":"https://instructionsets.com/powerisa/tcheck/","api":"https://instructionsets.com/api/v1/powerisa/tcheck.json"},{"mnemonic":"td","slug":"td","records":1,"summary":"Traps if condition (comparison of doublewords) is met.","page":"https://instructionsets.com/powerisa/td/","api":"https://instructionsets.com/api/v1/powerisa/td.json"},{"mnemonic":"tdi","slug":"tdi","records":1,"summary":"Compares the contents of a register with an immediate value and invokes a trap handler if specified conditions are met.","page":"https://instructionsets.com/powerisa/tdi/","api":"https://instructionsets.com/api/v1/powerisa/tdi.json"},{"mnemonic":"tend.","slug":"tend_","records":1,"summary":"Commits the current hardware transaction. If successful, memory changes become visible atomically.","page":"https://instructionsets.com/powerisa/tend_/","api":"https://instructionsets.com/api/v1/powerisa/tend_.json"},{"mnemonic":"tlbia","slug":"tlbia","records":1,"summary":"Invalidates the entire Translation Lookaside Buffer.","page":"https://instructionsets.com/powerisa/tlbia/","api":"https://instructionsets.com/api/v1/powerisa/tlbia.json"},{"mnemonic":"tlbie","slug":"tlbie","records":1,"summary":"Invalidates a TLB entry corresponding to the address in RB.","page":"https://instructionsets.com/powerisa/tlbie/","api":"https://instructionsets.com/api/v1/powerisa/tlbie.json"},{"mnemonic":"tlbiel","slug":"tlbiel","records":1,"summary":"Invalidates a TLB entry on the current processor only.","page":"https://instructionsets.com/powerisa/tlbiel/","api":"https://instructionsets.com/api/v1/powerisa/tlbiel.json"},{"mnemonic":"tlbilx","slug":"tlbilx","records":1,"summary":"Invalidates TLB entries on the local processor based on Process ID (PID).","page":"https://instructionsets.com/powerisa/tlbilx/","api":"https://instructionsets.com/api/v1/powerisa/tlbilx.json"},{"mnemonic":"tlbivax","slug":"tlbivax","records":1,"summary":"Invalidates a TLB entry by virtual address.","page":"https://instructionsets.com/powerisa/tlbivax/","api":"https://instructionsets.com/api/v1/powerisa/tlbivax.json"},{"mnemonic":"tlbre","slug":"tlbre","records":1,"summary":"Reads a TLB entry into MAS registers.","page":"https://instructionsets.com/powerisa/tlbre/","api":"https://instructionsets.com/api/v1/powerisa/tlbre.json"},{"mnemonic":"tlbsx","slug":"tlbsx","records":1,"summary":"Searches the TLB for an address.","page":"https://instructionsets.com/powerisa/tlbsx/","api":"https://instructionsets.com/api/v1/powerisa/tlbsx.json"},{"mnemonic":"tlbsync","slug":"tlbsync","records":1,"summary":"Provides an ordering function for the effects of all tlbie instructions executed by the thread executing the tlbsync instruction.","page":"https://instructionsets.com/powerisa/tlbsync/","api":"https://instructionsets.com/api/v1/powerisa/tlbsync.json"},{"mnemonic":"tlbwe","slug":"tlbwe","records":1,"summary":"Writes a TLB entry from MAS registers.","page":"https://instructionsets.com/powerisa/tlbwe/","api":"https://instructionsets.com/api/v1/powerisa/tlbwe.json"},{"mnemonic":"trap","slug":"trap","records":1,"summary":"Unconditional trap. Forces an exception. (Encoded as tw 31, 0, 0).","page":"https://instructionsets.com/powerisa/trap/","api":"https://instructionsets.com/api/v1/powerisa/trap.json"},{"mnemonic":"trechkpt","slug":"trechkpt","records":1,"summary":"Updates the transaction checkpoint.","page":"https://instructionsets.com/powerisa/trechkpt/","api":"https://instructionsets.com/api/v1/powerisa/trechkpt.json"},{"mnemonic":"tresume","slug":"tresume","records":1,"summary":"Resumes a suspended transaction.","page":"https://instructionsets.com/powerisa/tresume/","api":"https://instructionsets.com/api/v1/powerisa/tresume.json"},{"mnemonic":"tsr","slug":"tsr","records":1,"summary":"Suspends or resumes a transaction based on L.","page":"https://instructionsets.com/powerisa/tsr/","api":"https://instructionsets.com/api/v1/powerisa/tsr.json"},{"mnemonic":"tsuspend","slug":"tsuspend","records":1,"summary":"Suspends the current transaction.","page":"https://instructionsets.com/powerisa/tsuspend/","api":"https://instructionsets.com/api/v1/powerisa/tsuspend.json"},{"mnemonic":"tw","slug":"tw","records":1,"summary":"Traps if condition (comparison of words) is met.","page":"https://instructionsets.com/powerisa/tw/","api":"https://instructionsets.com/api/v1/powerisa/tw.json"},{"mnemonic":"twi","slug":"twi","records":1,"summary":"Compares the contents of register RA with an immediate value and invokes the system trap handler if any specified condition is met.","page":"https://instructionsets.com/powerisa/twi/","api":"https://instructionsets.com/api/v1/powerisa/twi.json"},{"mnemonic":"urfid","slug":"urfid","records":1,"summary":"Returns from an ultravisor interrupt.","page":"https://instructionsets.com/powerisa/urfid/","api":"https://instructionsets.com/api/v1/powerisa/urfid.json"},{"mnemonic":"vabsdub","slug":"vabsdub","records":1,"summary":"Returns the absolute value of the difference of integer values in byte elements.","page":"https://instructionsets.com/powerisa/vabsdub/","api":"https://instructionsets.com/api/v1/powerisa/vabsdub.json"},{"mnemonic":"vabsduh","slug":"vabsduh","records":1,"summary":"Computes |A - B| for halfwords.","page":"https://instructionsets.com/powerisa/vabsduh/","api":"https://instructionsets.com/api/v1/powerisa/vabsduh.json"},{"mnemonic":"vabsduw","slug":"vabsduw","records":1,"summary":"Calculates the absolute difference of unsigned words from two vector registers and stores the result in another vector register.","page":"https://instructionsets.com/powerisa/vabsduw/","api":"https://instructionsets.com/api/v1/powerisa/vabsduw.json"},{"mnemonic":"vaddcuq","slug":"vaddcuq","records":1,"summary":"Adds the contents of two vector registers and writes the carry-out to another register.","page":"https://instructionsets.com/powerisa/vaddcuq/","api":"https://instructionsets.com/api/v1/powerisa/vaddcuq.json"},{"mnemonic":"vaddcuw","slug":"vaddcuw","records":1,"summary":"Adds the contents of two vector registers and writes the carry-out to another vector register.","page":"https://instructionsets.com/powerisa/vaddcuw/","api":"https://instructionsets.com/api/v1/powerisa/vaddcuw.json"},{"mnemonic":"vaddfp","slug":"vaddfp","records":1,"summary":"Adds the contents of two vector registers and places the result in another vector register.","page":"https://instructionsets.com/powerisa/vaddfp/","api":"https://instructionsets.com/api/v1/powerisa/vaddfp.json"},{"mnemonic":"vaddsbs","slug":"vaddsbs","records":1,"summary":"Adds 16 signed bytes with saturation (-128..127).","page":"https://instructionsets.com/powerisa/vaddsbs/","api":"https://instructionsets.com/api/v1/powerisa/vaddsbs.json"},{"mnemonic":"vaddshs","slug":"vaddshs","records":1,"summary":"Adds the contents of two vector registers and saturates the result if it overflows.","page":"https://instructionsets.com/powerisa/vaddshs/","api":"https://instructionsets.com/api/v1/powerisa/vaddshs.json"},{"mnemonic":"vaddsws","slug":"vaddsws","records":1,"summary":"Adds 4 signed words with saturation.","page":"https://instructionsets.com/powerisa/vaddsws/","api":"https://instructionsets.com/api/v1/powerisa/vaddsws.json"},{"mnemonic":"vaddubm","slug":"vaddubm","records":1,"summary":"Adds the contents of two vector registers and updates the result in another vector register, modulo operation for bytes.","page":"https://instructionsets.com/powerisa/vaddubm/","api":"https://instructionsets.com/api/v1/powerisa/vaddubm.json"},{"mnemonic":"vaddubs","slug":"vaddubs","records":1,"summary":"Adds the contents of two vector registers and saturates the result if it overflows.","page":"https://instructionsets.com/powerisa/vaddubs/","api":"https://instructionsets.com/api/v1/powerisa/vaddubs.json"},{"mnemonic":"vaddudm","slug":"vaddudm","records":1,"summary":"Adds 2 doublewords modulo 2^64.","page":"https://instructionsets.com/powerisa/vaddudm/","api":"https://instructionsets.com/api/v1/powerisa/vaddudm.json"},{"mnemonic":"vadduhm","slug":"vadduhm","records":1,"summary":"Adds 8 halfwords modulo 65536.","page":"https://instructionsets.com/powerisa/vadduhm/","api":"https://instructionsets.com/api/v1/powerisa/vadduhm.json"},{"mnemonic":"vadduhs","slug":"vadduhs","records":1,"summary":"Adds the contents of two vector registers and saturates the result.","page":"https://instructionsets.com/powerisa/vadduhs/","api":"https://instructionsets.com/api/v1/powerisa/vadduhs.json"},{"mnemonic":"vadduqm","slug":"vadduqm","records":1,"summary":"Adds the contents of two vector registers and updates the destination register with the result modulo 2^128.","page":"https://instructionsets.com/powerisa/vadduqm/","api":"https://instructionsets.com/api/v1/powerisa/vadduqm.json"},{"mnemonic":"vadduwm","slug":"vadduwm","records":1,"summary":"Adds 4 words modulo 2^32.","page":"https://instructionsets.com/powerisa/vadduwm/","api":"https://instructionsets.com/api/v1/powerisa/vadduwm.json"},{"mnemonic":"vadduws","slug":"vadduws","records":1,"summary":"Adds the contents of two vector registers and saturates the result if it exceeds 32 bits.","page":"https://instructionsets.com/powerisa/vadduws/","api":"https://instructionsets.com/api/v1/powerisa/vadduws.json"},{"mnemonic":"vand","slug":"vand","records":1,"summary":"Performs a bitwise AND operation on the contents of two vector registers and stores the result in another vector register.","page":"https://instructionsets.com/powerisa/vand/","api":"https://instructionsets.com/api/v1/powerisa/vand.json"},{"mnemonic":"vandc","slug":"vandc","records":1,"summary":"Bitwise AND of vA with the ones' complement of vB (vA & ~vB).","page":"https://instructionsets.com/powerisa/vandc/","api":"https://instructionsets.com/api/v1/powerisa/vandc.json"},{"mnemonic":"vavgsb","slug":"vavgsb","records":1,"summary":"Performs a signed byte-wise average of two vector registers and stores the result in another vector register.","page":"https://instructionsets.com/powerisa/vavgsb/","api":"https://instructionsets.com/api/v1/powerisa/vavgsb.json"},{"mnemonic":"vavgsh","slug":"vavgsh","records":1,"summary":"Performs a signed halfword average operation on vector elements.","page":"https://instructionsets.com/powerisa/vavgsh/","api":"https://instructionsets.com/api/v1/powerisa/vavgsh.json"},{"mnemonic":"vavgsw","slug":"vavgsw","records":1,"summary":"Performs a vector average of signed words from two source vectors and stores the result in a destination vector.","page":"https://instructionsets.com/powerisa/vavgsw/","api":"https://instructionsets.com/api/v1/powerisa/vavgsw.json"},{"mnemonic":"vavgub","slug":"vavgub","records":1,"summary":"Computes (a+b+1)/2 for bytes.","page":"https://instructionsets.com/powerisa/vavgub/","api":"https://instructionsets.com/api/v1/powerisa/vavgub.json"},{"mnemonic":"vavguh","slug":"vavguh","records":1,"summary":"Computes (a+b+1)/2 for halfwords.","page":"https://instructionsets.com/powerisa/vavguh/","api":"https://instructionsets.com/api/v1/powerisa/vavguh.json"},{"mnemonic":"vavguw","slug":"vavguw","records":1,"summary":"Computes (a+b+1)/2 for words.","page":"https://instructionsets.com/powerisa/vavguw/","api":"https://instructionsets.com/api/v1/powerisa/vavguw.json"},{"mnemonic":"vbcdadd","slug":"vbcdadd","records":1,"summary":"Adds two BCD (Binary Coded Decimal) vectors.","page":"https://instructionsets.com/powerisa/vbcdadd/","api":"https://instructionsets.com/api/v1/powerisa/vbcdadd.json"},{"mnemonic":"vbpermd","slug":"vbpermd","records":1,"summary":"Performs a bit permute operation on doublewords of two vector registers and stores the result in another vector register.","page":"https://instructionsets.com/powerisa/vbpermd/","api":"https://instructionsets.com/api/v1/powerisa/vbpermd.json"},{"mnemonic":"vbpermq","slug":"vbpermq","records":1,"summary":"Performs a bit permutation on two vector registers and stores the result in another vector register.","page":"https://instructionsets.com/powerisa/vbpermq/","api":"https://instructionsets.com/api/v1/powerisa/vbpermq.json"},{"mnemonic":"vbrd","slug":"vbrd","records":1,"summary":"Reverses bytes within each doubleword.","page":"https://instructionsets.com/powerisa/vbrd/","api":"https://instructionsets.com/api/v1/powerisa/vbrd.json"},{"mnemonic":"vbrh","slug":"vbrh","records":1,"summary":"Reverses bytes within each halfword (Endian Swap).","page":"https://instructionsets.com/powerisa/vbrh/","api":"https://instructionsets.com/api/v1/powerisa/vbrh.json"},{"mnemonic":"vbrq","slug":"vbrq","records":1,"summary":"Reverses bytes within the entire 128-bit quadword.","page":"https://instructionsets.com/powerisa/vbrq/","api":"https://instructionsets.com/api/v1/powerisa/vbrq.json"},{"mnemonic":"vbrw","slug":"vbrw","records":1,"summary":"Reverses bytes within each word.","page":"https://instructionsets.com/powerisa/vbrw/","api":"https://instructionsets.com/api/v1/powerisa/vbrw.json"},{"mnemonic":"vcfsx","slug":"vcfsx","records":1,"summary":"Converts signed fixed-point values in a vector register to single-precision floating-point values.","page":"https://instructionsets.com/powerisa/vcfsx/","api":"https://instructionsets.com/api/v1/powerisa/vcfsx.json"},{"mnemonic":"vcfuged","slug":"vcfuged","records":1,"summary":"Separates bits of source into two groups based on mask (Power10).","page":"https://instructionsets.com/powerisa/vcfuged/","api":"https://instructionsets.com/api/v1/powerisa/vcfuged.json"},{"mnemonic":"vcfux","slug":"vcfux","records":1,"summary":"Converts 4 unsigned 32-bit integers to floats.","page":"https://instructionsets.com/powerisa/vcfux/","api":"https://instructionsets.com/api/v1/powerisa/vcfux.json"},{"mnemonic":"vcipher","slug":"vcipher","records":1,"summary":"Performs one round of AES encryption (SubBytes, ShiftRows, MixColumns, AddRoundKey).","page":"https://instructionsets.com/powerisa/vcipher/","api":"https://instructionsets.com/api/v1/powerisa/vcipher.json"},{"mnemonic":"vcipherlast","slug":"vcipherlast","records":1,"summary":"Performs the final round of AES encryption (SubBytes, ShiftRows, AddRoundKey). No MixColumns.","page":"https://instructionsets.com/powerisa/vcipherlast/","api":"https://instructionsets.com/api/v1/powerisa/vcipherlast.json"},{"mnemonic":"vclrlb","slug":"vclrlb","records":1,"summary":"Clears the leftmost bytes in a vector register based on the value in a general-purpose register.","page":"https://instructionsets.com/powerisa/vclrlb/","api":"https://instructionsets.com/api/v1/powerisa/vclrlb.json"},{"mnemonic":"vclrrb","slug":"vclrrb","records":1,"summary":"Clears the N rightmost bytes of a vector.","page":"https://instructionsets.com/powerisa/vclrrb/","api":"https://instructionsets.com/api/v1/powerisa/vclrrb.json"},{"mnemonic":"vclzb","slug":"vclzb","records":1,"summary":"Counts the number of leading zero bits in each byte element of a vector register.","page":"https://instructionsets.com/powerisa/vclzb/","api":"https://instructionsets.com/api/v1/powerisa/vclzb.json"},{"mnemonic":"vclzd","slug":"vclzd","records":1,"summary":"Counts the number of leading zero bits in each doubleword element of a vector register.","page":"https://instructionsets.com/powerisa/vclzd/","api":"https://instructionsets.com/api/v1/powerisa/vclzd.json"},{"mnemonic":"vclzdm","slug":"vclzdm","records":1,"summary":"Counts the number of leading zeros in each doubleword element of a vector, considering a mask.","page":"https://instructionsets.com/powerisa/vclzdm/","api":"https://instructionsets.com/api/v1/powerisa/vclzdm.json"},{"mnemonic":"vclzh","slug":"vclzh","records":1,"summary":"Counts leading zeros in each halfword.","page":"https://instructionsets.com/powerisa/vclzh/","api":"https://instructionsets.com/api/v1/powerisa/vclzh.json"},{"mnemonic":"vclzlsbb","slug":"vclzlsbb","records":1,"summary":"Counts the number of contiguous leading byte elements in VSR[VRB+32] having a zero least-significant bit.","page":"https://instructionsets.com/powerisa/vclzlsbb/","api":"https://instructionsets.com/api/v1/powerisa/vclzlsbb.json"},{"mnemonic":"vclzw","slug":"vclzw","records":1,"summary":"Counts the number of leading zero bits in each word element of a vector register.","page":"https://instructionsets.com/powerisa/vclzw/","api":"https://instructionsets.com/api/v1/powerisa/vclzw.json"},{"mnemonic":"vcmpbfp","slug":"vcmpbfp","records":1,"summary":"Compares two VSRs word element by word and sets the target VSR if Rc=1.","page":"https://instructionsets.com/powerisa/vcmpbfp/","api":"https://instructionsets.com/api/v1/powerisa/vcmpbfp.json"},{"mnemonic":"vcmpbfp.","slug":"vcmpbfp_","records":1,"summary":"Compares two VSRs word element by word and sets the target VSR if Rc=1.","page":"https://instructionsets.com/powerisa/vcmpbfp_/","api":"https://instructionsets.com/api/v1/powerisa/vcmpbfp_.json"},{"mnemonic":"vcmpeqfp","slug":"vcmpeqfp","records":1,"summary":"Compares the elements of two vector registers for equality and stores the result in a third vector register.","page":"https://instructionsets.com/powerisa/vcmpeqfp/","api":"https://instructionsets.com/api/v1/powerisa/vcmpeqfp.json"},{"mnemonic":"vcmpeqfp.","slug":"vcmpeqfp_","records":1,"summary":"Compares the elements of two vector registers for equality and stores the result in a third vector register.","page":"https://instructionsets.com/powerisa/vcmpeqfp_/","api":"https://instructionsets.com/api/v1/powerisa/vcmpeqfp_.json"},{"mnemonic":"vcmpequb","slug":"vcmpequb","records":1,"summary":"Compares two vector registers element by element as unsigned bytes and sets the target vector register based on the comparison.","page":"https://instructionsets.com/powerisa/vcmpequb/","api":"https://instructionsets.com/api/v1/powerisa/vcmpequb.json"},{"mnemonic":"vcmpequb.","slug":"vcmpequb_","records":1,"summary":"Compares two vector registers element by element as unsigned bytes and sets the target vector register based on the comparison.","page":"https://instructionsets.com/powerisa/vcmpequb_/","api":"https://instructionsets.com/api/v1/powerisa/vcmpequb_.json"},{"mnemonic":"vcmpequd","slug":"vcmpequd","records":1,"summary":"Compares two vector registers for equality on an unsigned doubleword basis and stores the result in a third vector register.","page":"https://instructionsets.com/powerisa/vcmpequd/","api":"https://instructionsets.com/api/v1/powerisa/vcmpequd.json"},{"mnemonic":"vcmpequd.","slug":"vcmpequd_","records":1,"summary":"Compares two vector registers for equality on an unsigned doubleword basis and stores the result in a third vector register.","page":"https://instructionsets.com/powerisa/vcmpequd_/","api":"https://instructionsets.com/api/v1/powerisa/vcmpequd_.json"},{"mnemonic":"vcmpequh","slug":"vcmpequh","records":1,"summary":"Compares each halfword of two vector registers and sets the corresponding halfword in the target register to all 1s if they are equal, otherwise all 0s.","page":"https://instructionsets.com/powerisa/vcmpequh/","api":"https://instructionsets.com/api/v1/powerisa/vcmpequh.json"},{"mnemonic":"vcmpequh.","slug":"vcmpequh_","records":1,"summary":"Compares each halfword of two vector registers and sets the corresponding halfword in the target register to all 1s if they are equal, otherwise all 0s.","page":"https://instructionsets.com/powerisa/vcmpequh_/","api":"https://instructionsets.com/api/v1/powerisa/vcmpequh_.json"},{"mnemonic":"vcmpequq","slug":"vcmpequq","records":1,"summary":"Compares two quadwords and sets the result to all ones if they are equal, otherwise all zeros.","page":"https://instructionsets.com/powerisa/vcmpequq/","api":"https://instructionsets.com/api/v1/powerisa/vcmpequq.json"},{"mnemonic":"vcmpequq.","slug":"vcmpequq_","records":1,"summary":"Compares two quadwords and sets the result to all ones if they are equal, otherwise all zeros.","page":"https://instructionsets.com/powerisa/vcmpequq_/","api":"https://instructionsets.com/api/v1/powerisa/vcmpequq_.json"},{"mnemonic":"vcmpequw","slug":"vcmpequw","records":1,"summary":"Compares each word of two vector registers and sets the corresponding word in the target register to all 1s if they are equal, otherwise all 0s.","page":"https://instructionsets.com/powerisa/vcmpequw/","api":"https://instructionsets.com/api/v1/powerisa/vcmpequw.json"},{"mnemonic":"vcmpequw.","slug":"vcmpequw_","records":1,"summary":"Compares each word of two vector registers and sets the corresponding word in the target register to all 1s if they are equal, otherwise all 0s.","page":"https://instructionsets.com/powerisa/vcmpequw_/","api":"https://instructionsets.com/api/v1/powerisa/vcmpequw_.json"},{"mnemonic":"vcmpgefp","slug":"vcmpgefp","records":1,"summary":"Compares 4 floats (A >= B).","page":"https://instructionsets.com/powerisa/vcmpgefp/","api":"https://instructionsets.com/api/v1/powerisa/vcmpgefp.json"},{"mnemonic":"vcmpgefp.","slug":"vcmpgefp_","records":1,"summary":"Compares the elements of two vector registers and sets the result in a third vector register based on whether each element is greater than or equal to the corresponding element in the other vector.","page":"https://instructionsets.com/powerisa/vcmpgefp_/","api":"https://instructionsets.com/api/v1/powerisa/vcmpgefp_.json"},{"mnemonic":"vcmpgtfp","slug":"vcmpgtfp","records":1,"summary":"Compares the contents of two vector registers and sets the target vector register based on whether each element is greater than the corresponding element in the other vector.","page":"https://instructionsets.com/powerisa/vcmpgtfp/","api":"https://instructionsets.com/api/v1/powerisa/vcmpgtfp.json"},{"mnemonic":"vcmpgtfp.","slug":"vcmpgtfp_","records":1,"summary":"Compares the contents of two vector registers and sets the target vector register based on whether each element is greater than the corresponding element in the other vector.","page":"https://instructionsets.com/powerisa/vcmpgtfp_/","api":"https://instructionsets.com/api/v1/powerisa/vcmpgtfp_.json"},{"mnemonic":"vcmpgtsb","slug":"vcmpgtsb","records":1,"summary":"Compares each byte of two vector registers and sets the corresponding result byte to all 1s if the signed byte in the first source register is greater than the signed byte in the second source register, otherwise sets it to all 0s.","page":"https://instructionsets.com/powerisa/vcmpgtsb/","api":"https://instructionsets.com/api/v1/powerisa/vcmpgtsb.json"},{"mnemonic":"vcmpgtsb.","slug":"vcmpgtsb_","records":1,"summary":"Compares each byte of two vector registers and sets the corresponding result byte to all 1s if the signed byte in the first source register is greater than the signed byte in the second source register, otherwise sets it to all 0s.","page":"https://instructionsets.com/powerisa/vcmpgtsb_/","api":"https://instructionsets.com/api/v1/powerisa/vcmpgtsb_.json"},{"mnemonic":"vcmpgtsd","slug":"vcmpgtsd","records":1,"summary":"Compares two doublewords of signed integers and sets the result vector based on the comparison.","page":"https://instructionsets.com/powerisa/vcmpgtsd/","api":"https://instructionsets.com/api/v1/powerisa/vcmpgtsd.json"},{"mnemonic":"vcmpgtsd.","slug":"vcmpgtsd_","records":1,"summary":"Compares two doublewords of signed integers and sets the result vector based on the comparison.","page":"https://instructionsets.com/powerisa/vcmpgtsd_/","api":"https://instructionsets.com/api/v1/powerisa/vcmpgtsd_.json"},{"mnemonic":"vcmpgtsh","slug":"vcmpgtsh","records":1,"summary":"Compares each halfword of two vector registers and sets the corresponding result element to all 1s if the first operand is greater than the second, otherwise all 0s.","page":"https://instructionsets.com/powerisa/vcmpgtsh/","api":"https://instructionsets.com/api/v1/powerisa/vcmpgtsh.json"},{"mnemonic":"vcmpgtsh.","slug":"vcmpgtsh_","records":1,"summary":"Compares each halfword of two vector registers and sets the corresponding result element to all 1s if the first operand is greater than the second, otherwise all 0s.","page":"https://instructionsets.com/powerisa/vcmpgtsh_/","api":"https://instructionsets.com/api/v1/powerisa/vcmpgtsh_.json"},{"mnemonic":"vcmpgtsq","slug":"vcmpgtsq","records":1,"summary":"Compares two signed quadwords and sets the result based on whether the first is greater than the second.","page":"https://instructionsets.com/powerisa/vcmpgtsq/","api":"https://instructionsets.com/api/v1/powerisa/vcmpgtsq.json"},{"mnemonic":"vcmpgtsq.","slug":"vcmpgtsq_","records":1,"summary":"Compares two signed quadwords and sets the result based on whether the first is greater than the second.","page":"https://instructionsets.com/powerisa/vcmpgtsq_/","api":"https://instructionsets.com/api/v1/powerisa/vcmpgtsq_.json"},{"mnemonic":"vcmpgtsw","slug":"vcmpgtsw","records":1,"summary":"Compares each word of two vector registers and sets the corresponding word in the target vector register to all 1s if the first operand is greater than the second, otherwise to all 0s.","page":"https://instructionsets.com/powerisa/vcmpgtsw/","api":"https://instructionsets.com/api/v1/powerisa/vcmpgtsw.json"},{"mnemonic":"vcmpgtsw.","slug":"vcmpgtsw_","records":1,"summary":"Compares each word of two vector registers and sets the corresponding word in the target vector register to all 1s if the first operand is greater than the second, otherwise to all 0s.","page":"https://instructionsets.com/powerisa/vcmpgtsw_/","api":"https://instructionsets.com/api/v1/powerisa/vcmpgtsw_.json"},{"mnemonic":"vcmpgtub","slug":"vcmpgtub","records":1,"summary":"Unsigned > comparison for 16 bytes.","page":"https://instructionsets.com/powerisa/vcmpgtub/","api":"https://instructionsets.com/api/v1/powerisa/vcmpgtub.json"},{"mnemonic":"vcmpgtud","slug":"vcmpgtud","records":1,"summary":"Compares the contents of two vector registers and sets a result based on whether each element in the first register is greater than the corresponding element in the second register.","page":"https://instructionsets.com/powerisa/vcmpgtud/","api":"https://instructionsets.com/api/v1/powerisa/vcmpgtud.json"},{"mnemonic":"vcmpgtuh","slug":"vcmpgtuh","records":1,"summary":"Unsigned > comparison for 8 halfwords.","page":"https://instructionsets.com/powerisa/vcmpgtuh/","api":"https://instructionsets.com/api/v1/powerisa/vcmpgtuh.json"},{"mnemonic":"vcmpgtuw","slug":"vcmpgtuw","records":1,"summary":"Unsigned > comparison for 4 words.","page":"https://instructionsets.com/powerisa/vcmpgtuw/","api":"https://instructionsets.com/api/v1/powerisa/vcmpgtuw.json"},{"mnemonic":"vcmpneb","slug":"vcmpneb","records":1,"summary":"Compares each byte of two vector registers and sets the result register to all 1s if the bytes are not equal, otherwise all 0s.","page":"https://instructionsets.com/powerisa/vcmpneb/","api":"https://instructionsets.com/api/v1/powerisa/vcmpneb.json"},{"mnemonic":"vcmpneb.","slug":"vcmpneb_","records":1,"summary":"Compares each byte of two vector registers and sets the result register to all 1s if the bytes are not equal, otherwise all 0s.","page":"https://instructionsets.com/powerisa/vcmpneb_/","api":"https://instructionsets.com/api/v1/powerisa/vcmpneb_.json"},{"mnemonic":"vcmpneh","slug":"vcmpneh","records":1,"summary":"Compares the contents of two vector registers and sets the result register to all 1s if the elements are not equal, otherwise all 0s.","page":"https://instructionsets.com/powerisa/vcmpneh/","api":"https://instructionsets.com/api/v1/powerisa/vcmpneh.json"},{"mnemonic":"vcmpneh.","slug":"vcmpneh_","records":1,"summary":"Compares the contents of two vector registers and sets the result register to all 1s if the elements are not equal, otherwise all 0s.","page":"https://instructionsets.com/powerisa/vcmpneh_/","api":"https://instructionsets.com/api/v1/powerisa/vcmpneh_.json"},{"mnemonic":"vcmpnew","slug":"vcmpnew","records":1,"summary":"Compares each word of two vector registers and sets the corresponding word in the target vector register to all 1s if the words are not equal, otherwise to all 0s.","page":"https://instructionsets.com/powerisa/vcmpnew/","api":"https://instructionsets.com/api/v1/powerisa/vcmpnew.json"},{"mnemonic":"vcmpnew.","slug":"vcmpnew_","records":1,"summary":"Compares each word of two vector registers and sets the corresponding word in the target vector register to all 1s if the words are not equal, otherwise to all 0s.","page":"https://instructionsets.com/powerisa/vcmpnew_/","api":"https://instructionsets.com/api/v1/powerisa/vcmpnew_.json"},{"mnemonic":"vcmpsq","slug":"vcmpsq","records":1,"summary":"Compares the signed integer values in two vector registers and updates the condition register.","page":"https://instructionsets.com/powerisa/vcmpsq/","api":"https://instructionsets.com/api/v1/powerisa/vcmpsq.json"},{"mnemonic":"vcntmbb","slug":"vcntmbb","records":1,"summary":"Counts the number of true (or false) mask bits in a VSR and places the count in the leftmost byte of a GPR.","page":"https://instructionsets.com/powerisa/vcntmbb/","api":"https://instructionsets.com/api/v1/powerisa/vcntmbb.json"},{"mnemonic":"vcntmbw","slug":"vcntmbw","records":1,"summary":"Counts the number of word elements in a vector register that have bit 0 set to a specified value.","page":"https://instructionsets.com/powerisa/vcntmbw/","api":"https://instructionsets.com/api/v1/powerisa/vcntmbw.json"},{"mnemonic":"vctsxs","slug":"vctsxs","records":1,"summary":"Converts a vector of floating-point values to signed fixed-point integers with rounding towards zero and saturation.","page":"https://instructionsets.com/powerisa/vctsxs/","api":"https://instructionsets.com/api/v1/powerisa/vctsxs.json"},{"mnemonic":"vctuxs","slug":"vctuxs","records":1,"summary":"Converts 4 floats to 4 unsigned 32-bit integers.","page":"https://instructionsets.com/powerisa/vctuxs/","api":"https://instructionsets.com/api/v1/powerisa/vctuxs.json"},{"mnemonic":"vctzb","slug":"vctzb","records":1,"summary":"Counts the number of trailing zero bits in each byte element of a vector register.","page":"https://instructionsets.com/powerisa/vctzb/","api":"https://instructionsets.com/api/v1/powerisa/vctzb.json"},{"mnemonic":"vctzd","slug":"vctzd","records":1,"summary":"Counts the number of consecutive zero bits starting at bit 63 of each doubleword element in VSR[VRB+32] and places the result into VSR[VRT+32].","page":"https://instructionsets.com/powerisa/vctzd/","api":"https://instructionsets.com/api/v1/powerisa/vctzd.json"},{"mnemonic":"vctzh","slug":"vctzh","records":1,"summary":"Counts trailing zeros in each halfword.","page":"https://instructionsets.com/powerisa/vctzh/","api":"https://instructionsets.com/api/v1/powerisa/vctzh.json"},{"mnemonic":"vctzlsbb","slug":"vctzlsbb","records":1,"summary":"Counts the number of trailing zero bits in each byte element of a vector.","page":"https://instructionsets.com/powerisa/vctzlsbb/","api":"https://instructionsets.com/api/v1/powerisa/vctzlsbb.json"},{"mnemonic":"vctzw","slug":"vctzw","records":1,"summary":"Counts the number of trailing zero bits in each word element of a vector register.","page":"https://instructionsets.com/powerisa/vctzw/","api":"https://instructionsets.com/api/v1/powerisa/vctzw.json"},{"mnemonic":"vdivesd","slug":"vdivesd","records":1,"summary":"Performs extended signed doubleword division on vector elements.","page":"https://instructionsets.com/powerisa/vdivesd/","api":"https://instructionsets.com/api/v1/powerisa/vdivesd.json"},{"mnemonic":"vdivesq","slug":"vdivesq","records":1,"summary":"Divides the contents of two vector registers and updates the destination register with the quotient.","page":"https://instructionsets.com/powerisa/vdivesq/","api":"https://instructionsets.com/api/v1/powerisa/vdivesq.json"},{"mnemonic":"vdivesw","slug":"vdivesw","records":1,"summary":"Divides the contents of two vector registers and updates the result in another vector register.","page":"https://instructionsets.com/powerisa/vdivesw/","api":"https://instructionsets.com/api/v1/powerisa/vdivesw.json"},{"mnemonic":"vdivsd","slug":"vdivsd","records":1,"summary":"Divides the contents of two vector registers and updates the result in another vector register.","page":"https://instructionsets.com/powerisa/vdivsd/","api":"https://instructionsets.com/api/v1/powerisa/vdivsd.json"},{"mnemonic":"vdivsq","slug":"vdivsq","records":1,"summary":"Divides the contents of two vector registers and updates the destination register with the quotient.","page":"https://instructionsets.com/powerisa/vdivsq/","api":"https://instructionsets.com/api/v1/powerisa/vdivsq.json"},{"mnemonic":"vdivsw","slug":"vdivsw","records":1,"summary":"Divides the contents of two vector registers and updates the result in another vector register.","page":"https://instructionsets.com/powerisa/vdivsw/","api":"https://instructionsets.com/api/v1/powerisa/vdivsw.json"},{"mnemonic":"veqv","slug":"veqv","records":1,"summary":"Performs a logical equivalence operation on the contents of two vector registers and stores the result in another vector register.","page":"https://instructionsets.com/powerisa/veqv/","api":"https://instructionsets.com/api/v1/powerisa/veqv.json"},{"mnemonic":"vexpandbm","slug":"vexpandbm","records":1,"summary":"Expands the mask from bit 0 of each byte element in the source VSR to all bits in the corresponding element in the target VSR.","page":"https://instructionsets.com/powerisa/vexpandbm/","api":"https://instructionsets.com/api/v1/powerisa/vexpandbm.json"},{"mnemonic":"vexpanddm","slug":"vexpanddm","records":1,"summary":"Expands bits from a GPR mask into a doubleword-element vector.","page":"https://instructionsets.com/powerisa/vexpanddm/","api":"https://instructionsets.com/api/v1/powerisa/vexpanddm.json"},{"mnemonic":"vexpandhm","slug":"vexpandhm","records":1,"summary":"Expands bits from a GPR mask into a halfword-element vector.","page":"https://instructionsets.com/powerisa/vexpandhm/","api":"https://instructionsets.com/api/v1/powerisa/vexpandhm.json"},{"mnemonic":"vexpandqm","slug":"vexpandqm","records":1,"summary":"Expands bits from a GPR mask into a quadword-element vector.","page":"https://instructionsets.com/powerisa/vexpandqm/","api":"https://instructionsets.com/api/v1/powerisa/vexpandqm.json"},{"mnemonic":"vexpandwm","slug":"vexpandwm","records":1,"summary":"Expands bits from a GPR mask into a word-element vector.","page":"https://instructionsets.com/powerisa/vexpandwm/","api":"https://instructionsets.com/api/v1/powerisa/vexpandwm.json"},{"mnemonic":"vexptefp","slug":"vexptefp","records":1,"summary":"Estimates the result of raising 2 to the power of each element in a vector.","page":"https://instructionsets.com/powerisa/vexptefp/","api":"https://instructionsets.com/api/v1/powerisa/vexptefp.json"},{"mnemonic":"vextddvlx","slug":"vextddvlx","records":1,"summary":"Extracts a doubleword from the concatenation of two vector registers based on an index specified in a general-purpose register.","page":"https://instructionsets.com/powerisa/vextddvlx/","api":"https://instructionsets.com/api/v1/powerisa/vextddvlx.json"},{"mnemonic":"vextdubvlx","slug":"vextdubvlx","records":1,"summary":"Extracts a double unsigned byte from two vector registers using a left-index specified by a general-purpose register and places it into another vector register.","page":"https://instructionsets.com/powerisa/vextdubvlx/","api":"https://instructionsets.com/api/v1/powerisa/vextdubvlx.json"},{"mnemonic":"vextduhvlx","slug":"vextduhvlx","records":1,"summary":"Extracts a double unsigned halfword from two vector registers and places it into another vector register based on the index specified in a general-purpose register.","page":"https://instructionsets.com/powerisa/vextduhvlx/","api":"https://instructionsets.com/api/v1/powerisa/vextduhvlx.json"},{"mnemonic":"vextduwvlx","slug":"vextduwvlx","records":1,"summary":"Extracts a doubleword from the concatenation of two vector registers based on an index specified in a general-purpose register.","page":"https://instructionsets.com/powerisa/vextduwvlx/","api":"https://instructionsets.com/api/v1/powerisa/vextduwvlx.json"},{"mnemonic":"vextractbm","slug":"vextractbm","records":1,"summary":"Extracts bit 0 of each byte element from a VSR into a GPR.","page":"https://instructionsets.com/powerisa/vextractbm/","api":"https://instructionsets.com/api/v1/powerisa/vextractbm.json"},{"mnemonic":"vextractd","slug":"vextractd","records":1,"summary":"Extracts a doubleword from a vector into a GPR.","page":"https://instructionsets.com/powerisa/vextractd/","api":"https://instructionsets.com/api/v1/powerisa/vextractd.json"},{"mnemonic":"vextractdm","slug":"vextractdm","records":1,"summary":"Extracts MSB of each doubleword into a GPR mask.","page":"https://instructionsets.com/powerisa/vextractdm/","api":"https://instructionsets.com/api/v1/powerisa/vextractdm.json"},{"mnemonic":"vextracthm","slug":"vextracthm","records":1,"summary":"Extracts MSB of each halfword into a GPR mask.","page":"https://instructionsets.com/powerisa/vextracthm/","api":"https://instructionsets.com/api/v1/powerisa/vextracthm.json"},{"mnemonic":"vextractqm","slug":"vextractqm","records":1,"summary":"Extracts the least significant bit of a vector register and places it into a general-purpose register.","page":"https://instructionsets.com/powerisa/vextractqm/","api":"https://instructionsets.com/api/v1/powerisa/vextractqm.json"},{"mnemonic":"vextractub","slug":"vextractub","records":1,"summary":"Extracts an unsigned byte from a vector register and places it into the upper byte of another vector register.","page":"https://instructionsets.com/powerisa/vextractub/","api":"https://instructionsets.com/api/v1/powerisa/vextractub.json"},{"mnemonic":"vextractuh","slug":"vextractuh","records":1,"summary":"Extracts a halfword from a vector into a GPR.","page":"https://instructionsets.com/powerisa/vextractuh/","api":"https://instructionsets.com/api/v1/powerisa/vextractuh.json"},{"mnemonic":"vextractuw","slug":"vextractuw","records":1,"summary":"Extracts an unsigned word from a vector register and places it into another vector register using an immediate-specified index.","page":"https://instructionsets.com/powerisa/vextractuw/","api":"https://instructionsets.com/api/v1/powerisa/vextractuw.json"},{"mnemonic":"vextractwm","slug":"vextractwm","records":1,"summary":"Extracts the least significant bit of each word element from a vector register and places them into a general-purpose register.","page":"https://instructionsets.com/powerisa/vextractwm/","api":"https://instructionsets.com/api/v1/powerisa/vextractwm.json"},{"mnemonic":"vextsb2d","slug":"vextsb2d","records":1,"summary":"Sign-extends the byte elements of a vector register to doublewords.","page":"https://instructionsets.com/powerisa/vextsb2d/","api":"https://instructionsets.com/api/v1/powerisa/vextsb2d.json"},{"mnemonic":"vextsb2w","slug":"vextsb2w","records":1,"summary":"Sign-extends each byte in a vector to a word.","page":"https://instructionsets.com/powerisa/vextsb2w/","api":"https://instructionsets.com/api/v1/powerisa/vextsb2w.json"},{"mnemonic":"vextsh2d","slug":"vextsh2d","records":1,"summary":"Extends the sign of each halfword in a vector to doubleword.","page":"https://instructionsets.com/powerisa/vextsh2d/","api":"https://instructionsets.com/api/v1/powerisa/vextsh2d.json"},{"mnemonic":"vextsh2w","slug":"vextsh2w","records":1,"summary":"Sign-extends halfwords to words.","page":"https://instructionsets.com/powerisa/vextsh2w/","api":"https://instructionsets.com/api/v1/powerisa/vextsh2w.json"},{"mnemonic":"vextsw2d","slug":"vextsw2d","records":1,"summary":"Extends the sign of each word in a vector to doubleword.","page":"https://instructionsets.com/powerisa/vextsw2d/","api":"https://instructionsets.com/api/v1/powerisa/vextsw2d.json"},{"mnemonic":"vextublx","slug":"vextublx","records":1,"summary":"Extracts an unsigned byte from a vector register and places it into a general-purpose register using the left-index specified in another general-purpose register.","page":"https://instructionsets.com/powerisa/vextublx/","api":"https://instructionsets.com/api/v1/powerisa/vextublx.json"},{"mnemonic":"vextuhlx","slug":"vextuhlx","records":1,"summary":"Extracts an unsigned halfword from a vector register and places it into a general-purpose register using the left index specified in another general-purpose register.","page":"https://instructionsets.com/powerisa/vextuhlx/","api":"https://instructionsets.com/api/v1/powerisa/vextuhlx.json"},{"mnemonic":"vextuwlx","slug":"vextuwlx","records":1,"summary":"Extracts an unsigned word from a vector register and places it into a general-purpose register.","page":"https://instructionsets.com/powerisa/vextuwlx/","api":"https://instructionsets.com/api/v1/powerisa/vextuwlx.json"},{"mnemonic":"vextuwrx","slug":"vextuwrx","records":1,"summary":"Extracts an unsigned word from a vector register and places it into a general-purpose register.","page":"https://instructionsets.com/powerisa/vextuwrx/","api":"https://instructionsets.com/api/v1/powerisa/vextuwrx.json"},{"mnemonic":"vgbbd","slug":"vgbbd","records":1,"summary":"The contents of bit j of each byte of doubleword element i of VSR[VRB+32] are concatenated and placed into byte j of doubleword element i of VSR[VRT+32].","page":"https://instructionsets.com/powerisa/vgbbd/","api":"https://instructionsets.com/api/v1/powerisa/vgbbd.json"},{"mnemonic":"vgnb","slug":"vgnb","records":1,"summary":"Gathers every Nth bit from a vector register and places it into a general-purpose register.","page":"https://instructionsets.com/powerisa/vgnb/","api":"https://instructionsets.com/api/v1/powerisa/vgnb.json"},{"mnemonic":"vinsblx","slug":"vinsblx","records":1,"summary":"Inserts a byte from a general-purpose register into a vector register at an index specified by another general-purpose register.","page":"https://instructionsets.com/powerisa/vinsblx/","api":"https://instructionsets.com/api/v1/powerisa/vinsblx.json"},{"mnemonic":"vinsbvlx","slug":"vinsbvlx","records":1,"summary":"Inserts a byte from one vector register into another based on an index specified in a general-purpose register.","page":"https://instructionsets.com/powerisa/vinsbvlx/","api":"https://instructionsets.com/api/v1/powerisa/vinsbvlx.json"},{"mnemonic":"vinsdlx","slug":"vinsdlx","records":1,"summary":"Inserts a doubleword from a general-purpose register into a vector register at a position specified by another general-purpose register.","page":"https://instructionsets.com/powerisa/vinsdlx/","api":"https://instructionsets.com/api/v1/powerisa/vinsdlx.json"},{"mnemonic":"vinsertb","slug":"vinsertb","records":1,"summary":"Inserts a byte element from one vector register into another at an immediate-specified index.","page":"https://instructionsets.com/powerisa/vinsertb/","api":"https://instructionsets.com/api/v1/powerisa/vinsertb.json"},{"mnemonic":"vinsertd","slug":"vinsertd","records":1,"summary":"Inserts a doubleword from a GPR into a vector.","page":"https://instructionsets.com/powerisa/vinsertd/","api":"https://instructionsets.com/api/v1/powerisa/vinsertd.json"},{"mnemonic":"vinserth","slug":"vinserth","records":1,"summary":"Inserts a halfword from a GPR into a vector.","page":"https://instructionsets.com/powerisa/vinserth/","api":"https://instructionsets.com/api/v1/powerisa/vinserth.json"},{"mnemonic":"vinsertw","slug":"vinsertw","records":1,"summary":"Inserts a word element from one vector register into another vector register at an immediate-specified index.","page":"https://instructionsets.com/powerisa/vinsertw/","api":"https://instructionsets.com/api/v1/powerisa/vinsertw.json"},{"mnemonic":"vinshlx","slug":"vinshlx","records":1,"summary":"Inserts the high halfword of a general-purpose register into a vector register at a position specified by another general-purpose register.","page":"https://instructionsets.com/powerisa/vinshlx/","api":"https://instructionsets.com/api/v1/powerisa/vinshlx.json"},{"mnemonic":"vinshvlx","slug":"vinshvlx","records":1,"summary":"Inserts halfword from a vector register into another vector register at a position specified by a general-purpose register.","page":"https://instructionsets.com/powerisa/vinshvlx/","api":"https://instructionsets.com/api/v1/powerisa/vinshvlx.json"},{"mnemonic":"vinshvrx","slug":"vinshvrx","records":1,"summary":"Inserts a halfword from a vector register into another vector register at a position specified by a general-purpose register.","page":"https://instructionsets.com/powerisa/vinshvrx/","api":"https://instructionsets.com/api/v1/powerisa/vinshvrx.json"},{"mnemonic":"vinsw","slug":"vinsw","records":1,"summary":"Inserts the contents of a word from a general-purpose register into a vector register at an immediate-specified index.","page":"https://instructionsets.com/powerisa/vinsw/","api":"https://instructionsets.com/api/v1/powerisa/vinsw.json"},{"mnemonic":"vinswlx","slug":"vinswlx","records":1,"summary":"Inserts the contents of bits 32:63 of a general-purpose register into byte elements of a vector register based on an index specified in another general-purpose register.","page":"https://instructionsets.com/powerisa/vinswlx/","api":"https://instructionsets.com/api/v1/powerisa/vinswlx.json"},{"mnemonic":"vinswvlx","slug":"vinswvlx","records":1,"summary":"Inserts a word from a vector register into another vector register at a position specified by a general-purpose register.","page":"https://instructionsets.com/powerisa/vinswvlx/","api":"https://instructionsets.com/api/v1/powerisa/vinswvlx.json"},{"mnemonic":"vlogefp","slug":"vlogefp","records":1,"summary":"Estimates the base 2 logarithm of single-precision floating-point elements in a vector register.","page":"https://instructionsets.com/powerisa/vlogefp/","api":"https://instructionsets.com/api/v1/powerisa/vlogefp.json"},{"mnemonic":"vmaddfp","slug":"vmaddfp","records":1,"summary":"Performs a multiply-add operation on vector elements.","page":"https://instructionsets.com/powerisa/vmaddfp/","api":"https://instructionsets.com/api/v1/powerisa/vmaddfp.json"},{"mnemonic":"vmaxfp","slug":"vmaxfp","records":1,"summary":"Performs element-wise maximum of two vector registers and stores the result in a third vector register.","page":"https://instructionsets.com/powerisa/vmaxfp/","api":"https://instructionsets.com/api/v1/powerisa/vmaxfp.json"},{"mnemonic":"vmaxsb","slug":"vmaxsb","records":1,"summary":"Performs a signed byte-wise maximum operation on two vector registers and stores the result in another vector register.","page":"https://instructionsets.com/powerisa/vmaxsb/","api":"https://instructionsets.com/api/v1/powerisa/vmaxsb.json"},{"mnemonic":"vmaxsd","slug":"vmaxsd","records":1,"summary":"Compares the signed doublewords of two vector registers and stores the maximum value in a third vector register.","page":"https://instructionsets.com/powerisa/vmaxsd/","api":"https://instructionsets.com/api/v1/powerisa/vmaxsd.json"},{"mnemonic":"vmaxsh","slug":"vmaxsh","records":1,"summary":"Compares the signed halfwords of two vector registers and stores the maximum values in a third vector register.","page":"https://instructionsets.com/powerisa/vmaxsh/","api":"https://instructionsets.com/api/v1/powerisa/vmaxsh.json"},{"mnemonic":"vmaxsw","slug":"vmaxsw","records":1,"summary":"Compares the signed integer values in each word element of two vector registers and stores the larger value into a third vector register.","page":"https://instructionsets.com/powerisa/vmaxsw/","api":"https://instructionsets.com/api/v1/powerisa/vmaxsw.json"},{"mnemonic":"vmaxub","slug":"vmaxub","records":1,"summary":"Selects maximum value per byte (unsigned).","page":"https://instructionsets.com/powerisa/vmaxub/","api":"https://instructionsets.com/api/v1/powerisa/vmaxub.json"},{"mnemonic":"vmaxuh","slug":"vmaxuh","records":1,"summary":"Selects maximum value per halfword (unsigned).","page":"https://instructionsets.com/powerisa/vmaxuh/","api":"https://instructionsets.com/api/v1/powerisa/vmaxuh.json"},{"mnemonic":"vmaxuw","slug":"vmaxuw","records":1,"summary":"Selects maximum value per word (unsigned).","page":"https://instructionsets.com/powerisa/vmaxuw/","api":"https://instructionsets.com/api/v1/powerisa/vmaxuw.json"},{"mnemonic":"vmhaddshs","slug":"vmhaddshs","records":1,"summary":"Performs a vector multiply-high-add signed halfword operation with saturation.","page":"https://instructionsets.com/powerisa/vmhaddshs/","api":"https://instructionsets.com/api/v1/powerisa/vmhaddshs.json"},{"mnemonic":"vminsb","slug":"vminsb","records":1,"summary":"Compares the signed byte elements of two vector registers and stores the minimum values in a third vector register.","page":"https://instructionsets.com/powerisa/vminsb/","api":"https://instructionsets.com/api/v1/powerisa/vminsb.json"},{"mnemonic":"vminsd","slug":"vminsd","records":1,"summary":"Compares the signed doublewords of two vector registers and stores the minimum values in a third vector register.","page":"https://instructionsets.com/powerisa/vminsd/","api":"https://instructionsets.com/api/v1/powerisa/vminsd.json"},{"mnemonic":"vminsh","slug":"vminsh","records":1,"summary":"Compares the signed halfwords of two vector registers and selects the minimum value for each corresponding pair.","page":"https://instructionsets.com/powerisa/vminsh/","api":"https://instructionsets.com/api/v1/powerisa/vminsh.json"},{"mnemonic":"vminsw","slug":"vminsw","records":1,"summary":"Compares the signed integer values in each word element of two vector registers and stores the smaller value into a target vector register.","page":"https://instructionsets.com/powerisa/vminsw/","api":"https://instructionsets.com/api/v1/powerisa/vminsw.json"},{"mnemonic":"vminub","slug":"vminub","records":1,"summary":"Selects minimum value per byte (unsigned).","page":"https://instructionsets.com/powerisa/vminub/","api":"https://instructionsets.com/api/v1/powerisa/vminub.json"},{"mnemonic":"vminuh","slug":"vminuh","records":1,"summary":"Selects minimum value per halfword (unsigned).","page":"https://instructionsets.com/powerisa/vminuh/","api":"https://instructionsets.com/api/v1/powerisa/vminuh.json"},{"mnemonic":"vminuw","slug":"vminuw","records":1,"summary":"Selects minimum value per word (unsigned).","page":"https://instructionsets.com/powerisa/vminuw/","api":"https://instructionsets.com/api/v1/powerisa/vminuw.json"},{"mnemonic":"vmladduhm","slug":"vmladduhm","records":1,"summary":"Performs a vector multiply-low-add unsigned halfword modulo operation.","page":"https://instructionsets.com/powerisa/vmladduhm/","api":"https://instructionsets.com/api/v1/powerisa/vmladduhm.json"},{"mnemonic":"vmodsd","slug":"vmodsd","records":1,"summary":"Performs vector modulo signed doubleword operation.","page":"https://instructionsets.com/powerisa/vmodsd/","api":"https://instructionsets.com/api/v1/powerisa/vmodsd.json"},{"mnemonic":"vmodsq","slug":"vmodsq","records":1,"summary":"Performs signed modulo operation on quadword elements of two vector registers and stores the result in another vector register.","page":"https://instructionsets.com/powerisa/vmodsq/","api":"https://instructionsets.com/api/v1/powerisa/vmodsq.json"},{"mnemonic":"vmodsw","slug":"vmodsw","records":1,"summary":"Performs modulo operation on signed integers in vector registers.","page":"https://instructionsets.com/powerisa/vmodsw/","api":"https://instructionsets.com/api/v1/powerisa/vmodsw.json"},{"mnemonic":"vmrgew","slug":"vmrgew","records":1,"summary":"Merges even word elements from two vector registers into a third.","page":"https://instructionsets.com/powerisa/vmrgew/","api":"https://instructionsets.com/api/v1/powerisa/vmrgew.json"},{"mnemonic":"vmrghb","slug":"vmrghb","records":1,"summary":"Interleaves high-order bytes from two vectors (Permutation).","page":"https://instructionsets.com/powerisa/vmrghb/","api":"https://instructionsets.com/api/v1/powerisa/vmrghb.json"},{"mnemonic":"vmrghh","slug":"vmrghh","records":1,"summary":"Merges the high halfwords of two vector registers into a target vector register.","page":"https://instructionsets.com/powerisa/vmrghh/","api":"https://instructionsets.com/api/v1/powerisa/vmrghh.json"},{"mnemonic":"vmrghw","slug":"vmrghw","records":1,"summary":"Merges the high words of two vector registers into a target vector register.","page":"https://instructionsets.com/powerisa/vmrghw/","api":"https://instructionsets.com/api/v1/powerisa/vmrghw.json"},{"mnemonic":"vmrglb","slug":"vmrglb","records":1,"summary":"Interleaves low-order bytes.","page":"https://instructionsets.com/powerisa/vmrglb/","api":"https://instructionsets.com/api/v1/powerisa/vmrglb.json"},{"mnemonic":"vmrglh","slug":"vmrglh","records":1,"summary":"Interleaves low-order halfwords.","page":"https://instructionsets.com/powerisa/vmrglh/","api":"https://instructionsets.com/api/v1/powerisa/vmrglh.json"},{"mnemonic":"vmrglw","slug":"vmrglw","records":1,"summary":"Interleaves low-order words.","page":"https://instructionsets.com/powerisa/vmrglw/","api":"https://instructionsets.com/api/v1/powerisa/vmrglw.json"},{"mnemonic":"vmrgow","slug":"vmrgow","records":1,"summary":"Merges odd words from two vectors.","page":"https://instructionsets.com/powerisa/vmrgow/","api":"https://instructionsets.com/api/v1/powerisa/vmrgow.json"},{"mnemonic":"vmsumcud","slug":"vmsumcud","records":1,"summary":"Performs vector multiply-sum and writes the carry-out of the low-order 128 bits to a destination register.","page":"https://instructionsets.com/powerisa/vmsumcud/","api":"https://instructionsets.com/api/v1/powerisa/vmsumcud.json"},{"mnemonic":"vmsummbm","slug":"vmsummbm","records":1,"summary":"Performs a vector multiply-sum operation with mixed byte elements.","page":"https://instructionsets.com/powerisa/vmsummbm/","api":"https://instructionsets.com/api/v1/powerisa/vmsummbm.json"},{"mnemonic":"vmsumshm","slug":"vmsumshm","records":1,"summary":"Multiplies halfwords and sums adjacent results into words.","page":"https://instructionsets.com/powerisa/vmsumshm/","api":"https://instructionsets.com/api/v1/powerisa/vmsumshm.json"},{"mnemonic":"vmsumshs","slug":"vmsumshs","records":1,"summary":"Performs a vector multiply-sum operation on signed halfwords and saturates the result.","page":"https://instructionsets.com/powerisa/vmsumshs/","api":"https://instructionsets.com/api/v1/powerisa/vmsumshs.json"},{"mnemonic":"vmsumubm","slug":"vmsumubm","records":1,"summary":"Multiplies bytes and sums adjacent results into words.","page":"https://instructionsets.com/powerisa/vmsumubm/","api":"https://instructionsets.com/api/v1/powerisa/vmsumubm.json"},{"mnemonic":"vmsumudm","slug":"vmsumudm","records":1,"summary":"Performs a horizontal add of the doubleword elements in VSR[VRA+32] using vmsumudm.","page":"https://instructionsets.com/powerisa/vmsumudm/","api":"https://instructionsets.com/api/v1/powerisa/vmsumudm.json"},{"mnemonic":"vmsumuhs","slug":"vmsumuhs","records":1,"summary":"Performs a vector multiply-sum operation on unsigned halfwords and saturates the result.","page":"https://instructionsets.com/powerisa/vmsumuhs/","api":"https://instructionsets.com/api/v1/powerisa/vmsumuhs.json"},{"mnemonic":"vmul10ecuq","slug":"vmul10ecuq","records":1,"summary":"Multiplies the unsigned quadword integer in vector register VA by 10, adds the least-significant bit of VB as a carry-in digit, and writes the carry-out of the result to vector register VX.","page":"https://instructionsets.com/powerisa/vmul10ecuq/","api":"https://instructionsets.com/api/v1/powerisa/vmul10ecuq.json"},{"mnemonic":"vmul10euq","slug":"vmul10euq","records":1,"summary":"Multiplies the contents of two vector registers by 10 and extends the result.","page":"https://instructionsets.com/powerisa/vmul10euq/","api":"https://instructionsets.com/api/v1/powerisa/vmul10euq.json"},{"mnemonic":"vmul10uq","slug":"vmul10uq","records":1,"summary":"Multiplies the contents of a vector register by 10 and places the result in another vector register.","page":"https://instructionsets.com/powerisa/vmul10uq/","api":"https://instructionsets.com/api/v1/powerisa/vmul10uq.json"},{"mnemonic":"vmulesb","slug":"vmulesb","records":1,"summary":"Multiplies the even-indexed bytes of two vector registers and stores the results in a destination vector register.","page":"https://instructionsets.com/powerisa/vmulesb/","api":"https://instructionsets.com/api/v1/powerisa/vmulesb.json"},{"mnemonic":"vmulesd","slug":"vmulesd","records":1,"summary":"Multiplies the even doublewords of two vector registers and places the result in another vector register.","page":"https://instructionsets.com/powerisa/vmulesd/","api":"https://instructionsets.com/api/v1/powerisa/vmulesd.json"},{"mnemonic":"vmulesh","slug":"vmulesh","records":1,"summary":"Multiplies the even-numbered halfwords of two vector registers and places the results into a destination vector register.","page":"https://instructionsets.com/powerisa/vmulesh/","api":"https://instructionsets.com/api/v1/powerisa/vmulesh.json"},{"mnemonic":"vmulesw","slug":"vmulesw","records":1,"summary":"Multiplies even-indexed signed words from two vector registers and stores the results in a destination vector register.","page":"https://instructionsets.com/powerisa/vmulesw/","api":"https://instructionsets.com/api/v1/powerisa/vmulesw.json"},{"mnemonic":"vmuleub","slug":"vmuleub","records":1,"summary":"Multiplies even-indexed bytes of two vector registers and stores the results in a destination vector register.","page":"https://instructionsets.com/powerisa/vmuleub/","api":"https://instructionsets.com/api/v1/powerisa/vmuleub.json"},{"mnemonic":"vmuleud","slug":"vmuleud","records":1,"summary":"Multiplies the even doublewords of two vector registers and places the result in another vector register.","page":"https://instructionsets.com/powerisa/vmuleud/","api":"https://instructionsets.com/api/v1/powerisa/vmuleud.json"},{"mnemonic":"vmuleuh","slug":"vmuleuh","records":1,"summary":"Multiplies the even-numbered halfwords of two vector registers and places the results into a destination vector register.","page":"https://instructionsets.com/powerisa/vmuleuh/","api":"https://instructionsets.com/api/v1/powerisa/vmuleuh.json"},{"mnemonic":"vmuleuw","slug":"vmuleuw","records":1,"summary":"Multiplies the even-numbered words of two vector registers and places the results in a destination vector register.","page":"https://instructionsets.com/powerisa/vmuleuw/","api":"https://instructionsets.com/api/v1/powerisa/vmuleuw.json"},{"mnemonic":"vmulhsd","slug":"vmulhsd","records":1,"summary":"Multiplies the signed doublewords of two vector registers and stores the high-order 64 bits of each product in a result vector register.","page":"https://instructionsets.com/powerisa/vmulhsd/","api":"https://instructionsets.com/api/v1/powerisa/vmulhsd.json"},{"mnemonic":"vmulhsw","slug":"vmulhsw","records":1,"summary":"Multiplies the signed integer values in each word element of two vector registers and places the high-order 32 bits of the 64-bit product into the corresponding word element of a third vector register.","page":"https://instructionsets.com/powerisa/vmulhsw/","api":"https://instructionsets.com/api/v1/powerisa/vmulhsw.json"},{"mnemonic":"vmulhud","slug":"vmulhud","records":1,"summary":"Multiplies unsigned doublewords, returning the high 64 bits.","page":"https://instructionsets.com/powerisa/vmulhud/","api":"https://instructionsets.com/api/v1/powerisa/vmulhud.json"},{"mnemonic":"vmulhuw","slug":"vmulhuw","records":1,"summary":"Multiplies unsigned words, returning the high 32 bits.","page":"https://instructionsets.com/powerisa/vmulhuw/","api":"https://instructionsets.com/api/v1/powerisa/vmulhuw.json"},{"mnemonic":"vmulld","slug":"vmulld","records":1,"summary":"Multiplies the contents of two vector registers and places the low-order 64 bits of each product into a target vector register.","page":"https://instructionsets.com/powerisa/vmulld/","api":"https://instructionsets.com/api/v1/powerisa/vmulld.json"},{"mnemonic":"vmulosb","slug":"vmulosb","records":1,"summary":"Multiplies odd signed bytes to halfwords.","page":"https://instructionsets.com/powerisa/vmulosb/","api":"https://instructionsets.com/api/v1/powerisa/vmulosb.json"},{"mnemonic":"vmulosh","slug":"vmulosh","records":1,"summary":"Multiplies odd signed halfwords to words.","page":"https://instructionsets.com/powerisa/vmulosh/","api":"https://instructionsets.com/api/v1/powerisa/vmulosh.json"},{"mnemonic":"vmulosw","slug":"vmulosw","records":1,"summary":"Multiplies odd words (1,3) to 64-bit signed result.","page":"https://instructionsets.com/powerisa/vmulosw/","api":"https://instructionsets.com/api/v1/powerisa/vmulosw.json"},{"mnemonic":"vmuloub","slug":"vmuloub","records":1,"summary":"Multiplies odd unsigned bytes to halfwords.","page":"https://instructionsets.com/powerisa/vmuloub/","api":"https://instructionsets.com/api/v1/powerisa/vmuloub.json"},{"mnemonic":"vmulouh","slug":"vmulouh","records":1,"summary":"Multiplies odd unsigned halfwords to words.","page":"https://instructionsets.com/powerisa/vmulouh/","api":"https://instructionsets.com/api/v1/powerisa/vmulouh.json"},{"mnemonic":"vmulouw","slug":"vmulouw","records":1,"summary":"Multiplies the 1st and 3rd words of the source vectors to produce two 64-bit results.","page":"https://instructionsets.com/powerisa/vmulouw/","api":"https://instructionsets.com/api/v1/powerisa/vmulouw.json"},{"mnemonic":"vmuluwm","slug":"vmuluwm","records":1,"summary":"Multiplies the contents of two vector registers and places the low-order 32 bits of each product into a target vector register.","page":"https://instructionsets.com/powerisa/vmuluwm/","api":"https://instructionsets.com/api/v1/powerisa/vmuluwm.json"},{"mnemonic":"vncipher","slug":"vncipher","records":1,"summary":"Performs one round of an AES inverse cipher operation on the intermediate state array.","page":"https://instructionsets.com/powerisa/vncipher/","api":"https://instructionsets.com/api/v1/powerisa/vncipher.json"},{"mnemonic":"vncipherlast","slug":"vncipherlast","records":1,"summary":"Performs the final round of AES decryption.","page":"https://instructionsets.com/powerisa/vncipherlast/","api":"https://instructionsets.com/api/v1/powerisa/vncipherlast.json"},{"mnemonic":"vnegd","slug":"vnegd","records":1,"summary":"Negates each doubleword integer.","page":"https://instructionsets.com/powerisa/vnegd/","api":"https://instructionsets.com/api/v1/powerisa/vnegd.json"},{"mnemonic":"vnegw","slug":"vnegw","records":1,"summary":"Negates the contents of each word element in a vector register.","page":"https://instructionsets.com/powerisa/vnegw/","api":"https://instructionsets.com/api/v1/powerisa/vnegw.json"},{"mnemonic":"vnor","slug":"vnor","records":1,"summary":"Performs a logical NOR operation on the contents of two vector registers and stores the result in another vector register.","page":"https://instructionsets.com/powerisa/vnor/","api":"https://instructionsets.com/api/v1/powerisa/vnor.json"},{"mnemonic":"vor","slug":"vor","records":1,"summary":"Bitwise OR of two 128-bit vectors.","page":"https://instructionsets.com/powerisa/vor/","api":"https://instructionsets.com/api/v1/powerisa/vor.json"},{"mnemonic":"vpdepd","slug":"vpdepd","records":1,"summary":"Deposits bits from source to target under control of a mask (Power10).","page":"https://instructionsets.com/powerisa/vpdepd/","api":"https://instructionsets.com/api/v1/powerisa/vpdepd.json"},{"mnemonic":"vperm","slug":"vperm","records":1,"summary":"The signature AltiVec instruction. Constructs a new vector by selecting bytes from two source vectors based on a permute control vector.","page":"https://instructionsets.com/powerisa/vperm/","api":"https://instructionsets.com/api/v1/powerisa/vperm.json"},{"mnemonic":"vpermr","slug":"vpermr","records":1,"summary":"Bitwise byte shuffle similar to vperm but for little-endian access optimization.","page":"https://instructionsets.com/powerisa/vpermr/","api":"https://instructionsets.com/api/v1/powerisa/vpermr.json"},{"mnemonic":"vpermxor","slug":"vpermxor","records":1,"summary":"Permutes bytes from vA and vB, then XORs with vC. Used for finite field arithmetic.","page":"https://instructionsets.com/powerisa/vpermxor/","api":"https://instructionsets.com/api/v1/powerisa/vpermxor.json"},{"mnemonic":"vpextd","slug":"vpextd","records":1,"summary":"Extracts bits from one vector register based on the bit positions specified in another vector register and places them into a third vector register.","page":"https://instructionsets.com/powerisa/vpextd/","api":"https://instructionsets.com/api/v1/powerisa/vpextd.json"},{"mnemonic":"vpkpx","slug":"vpkpx","records":1,"summary":"Packs the contents of two vector registers into a single vector register, with each source word being considered as a 32-bit pixel and each target halfword as a 16-bit pixel.","page":"https://instructionsets.com/powerisa/vpkpx/","api":"https://instructionsets.com/api/v1/powerisa/vpkpx.json"},{"mnemonic":"vpksdss","slug":"vpksdss","records":1,"summary":"Packs signed doublewords from two vector registers into a single vector register with signed saturation.","page":"https://instructionsets.com/powerisa/vpksdss/","api":"https://instructionsets.com/api/v1/powerisa/vpksdss.json"},{"mnemonic":"vpkshss","slug":"vpkshss","records":1,"summary":"Packs signed halfwords from two vector registers into a single vector register with signed saturation.","page":"https://instructionsets.com/powerisa/vpkshss/","api":"https://instructionsets.com/api/v1/powerisa/vpkshss.json"},{"mnemonic":"vpkswss","slug":"vpkswss","records":1,"summary":"Packs signed words from two vector registers into a single vector register with signed saturation.","page":"https://instructionsets.com/powerisa/vpkswss/","api":"https://instructionsets.com/api/v1/powerisa/vpkswss.json"},{"mnemonic":"vpkswus","slug":"vpkswus","records":1,"summary":"Packs signed words from two source vectors into one destination vector with unsigned saturation.","page":"https://instructionsets.com/powerisa/vpkswus/","api":"https://instructionsets.com/api/v1/powerisa/vpkswus.json"},{"mnemonic":"vpkudum","slug":"vpkudum","records":1,"summary":"Packs the upper halves of doublewords from two source vectors into a destination vector.","page":"https://instructionsets.com/powerisa/vpkudum/","api":"https://instructionsets.com/api/v1/powerisa/vpkudum.json"},{"mnemonic":"vpkuhum","slug":"vpkuhum","records":1,"summary":"Packs the upper half of each 16-bit element from two vector registers into a single byte in another vector register.","page":"https://instructionsets.com/powerisa/vpkuhum/","api":"https://instructionsets.com/api/v1/powerisa/vpkuhum.json"},{"mnemonic":"vpkuhus","slug":"vpkuhus","records":1,"summary":"Saturates 8 halfwords to 16 unsigned bytes.","page":"https://instructionsets.com/powerisa/vpkuhus/","api":"https://instructionsets.com/api/v1/powerisa/vpkuhus.json"},{"mnemonic":"vpkuwum","slug":"vpkuwum","records":1,"summary":"Packs the upper half of each word from two vector registers into a single vector register using modulo arithmetic.","page":"https://instructionsets.com/powerisa/vpkuwum/","api":"https://instructionsets.com/api/v1/powerisa/vpkuwum.json"},{"mnemonic":"vpmsumb","slug":"vpmsumb","records":1,"summary":"Performs GF(2) polynomial arithmetic (Carryless Multiply) on bytes.","page":"https://instructionsets.com/powerisa/vpmsumb/","api":"https://instructionsets.com/api/v1/powerisa/vpmsumb.json"},{"mnemonic":"vpmsumd","slug":"vpmsumd","records":1,"summary":"Performs GF(2) polynomial arithmetic on doublewords.","page":"https://instructionsets.com/powerisa/vpmsumd/","api":"https://instructionsets.com/api/v1/powerisa/vpmsumd.json"},{"mnemonic":"vpmsumh","slug":"vpmsumh","records":1,"summary":"Performs GF(2) polynomial arithmetic on halfwords.","page":"https://instructionsets.com/powerisa/vpmsumh/","api":"https://instructionsets.com/api/v1/powerisa/vpmsumh.json"},{"mnemonic":"vpmsumw","slug":"vpmsumw","records":1,"summary":"Performs a polynomial multiply-sum operation on word elements of two vector registers and stores the result in another vector register.","page":"https://instructionsets.com/powerisa/vpmsumw/","api":"https://instructionsets.com/api/v1/powerisa/vpmsumw.json"},{"mnemonic":"vpopcntb","slug":"vpopcntb","records":1,"summary":"Counts the number of bits set to 1 in each byte of a vector register.","page":"https://instructionsets.com/powerisa/vpopcntb/","api":"https://instructionsets.com/api/v1/powerisa/vpopcntb.json"},{"mnemonic":"vpopcntd","slug":"vpopcntd","records":1,"summary":"Counts set bits in each doubleword.","page":"https://instructionsets.com/powerisa/vpopcntd/","api":"https://instructionsets.com/api/v1/powerisa/vpopcntd.json"},{"mnemonic":"vpopcnth","slug":"vpopcnth","records":1,"summary":"Counts set bits in each halfword.","page":"https://instructionsets.com/powerisa/vpopcnth/","api":"https://instructionsets.com/api/v1/powerisa/vpopcnth.json"},{"mnemonic":"vpopcntw","slug":"vpopcntw","records":1,"summary":"Counts the number of bits set to 1 in each word element of a vector register.","page":"https://instructionsets.com/powerisa/vpopcntw/","api":"https://instructionsets.com/api/v1/powerisa/vpopcntw.json"},{"mnemonic":"vprtybd","slug":"vprtybd","records":1,"summary":"Computes parity of bytes within doublewords.","page":"https://instructionsets.com/powerisa/vprtybd/","api":"https://instructionsets.com/api/v1/powerisa/vprtybd.json"},{"mnemonic":"vprtybq","slug":"vprtybq","records":1,"summary":"Calculates the parity of each byte in a vector register and stores the result in another vector register.","page":"https://instructionsets.com/powerisa/vprtybq/","api":"https://instructionsets.com/api/v1/powerisa/vprtybq.json"},{"mnemonic":"vprtybw","slug":"vprtybw","records":1,"summary":"Calculates the parity of each byte in a vector word and stores the result.","page":"https://instructionsets.com/powerisa/vprtybw/","api":"https://instructionsets.com/api/v1/powerisa/vprtybw.json"},{"mnemonic":"vrefp","slug":"vrefp","records":1,"summary":"Estimates the reciprocal of single-precision floating-point elements in a vector.","page":"https://instructionsets.com/powerisa/vrefp/","api":"https://instructionsets.com/api/v1/powerisa/vrefp.json"},{"mnemonic":"vrfim","slug":"vrfim","records":1,"summary":"Rounds each element of a vector toward negative infinity.","page":"https://instructionsets.com/powerisa/vrfim/","api":"https://instructionsets.com/api/v1/powerisa/vrfim.json"},{"mnemonic":"vrfin","slug":"vrfin","records":1,"summary":"Rounds 4 floats to nearest integer.","page":"https://instructionsets.com/powerisa/vrfin/","api":"https://instructionsets.com/api/v1/powerisa/vrfin.json"},{"mnemonic":"vrfip","slug":"vrfip","records":1,"summary":"Rounds each element of a vector to the nearest integer towards positive infinity.","page":"https://instructionsets.com/powerisa/vrfip/","api":"https://instructionsets.com/api/v1/powerisa/vrfip.json"},{"mnemonic":"vrfiz","slug":"vrfiz","records":1,"summary":"Rounds 4 floats to integer (trunc).","page":"https://instructionsets.com/powerisa/vrfiz/","api":"https://instructionsets.com/api/v1/powerisa/vrfiz.json"},{"mnemonic":"vrlb","slug":"vrlb","records":1,"summary":"Rotates each byte of the source vector left by a specified number of bits.","page":"https://instructionsets.com/powerisa/vrlb/","api":"https://instructionsets.com/api/v1/powerisa/vrlb.json"},{"mnemonic":"vrld","slug":"vrld","records":1,"summary":"Rotates each doubleword left.","page":"https://instructionsets.com/powerisa/vrld/","api":"https://instructionsets.com/api/v1/powerisa/vrld.json"},{"mnemonic":"vrldmi","slug":"vrldmi","records":1,"summary":"Rotates the contents of a vector register left by a specified number of bits and inserts the result into another vector register under control of a mask.","page":"https://instructionsets.com/powerisa/vrldmi/","api":"https://instructionsets.com/api/v1/powerisa/vrldmi.json"},{"mnemonic":"vrlh","slug":"vrlh","records":1,"summary":"Rotates each halfword left.","page":"https://instructionsets.com/powerisa/vrlh/","api":"https://instructionsets.com/api/v1/powerisa/vrlh.json"},{"mnemonic":"vrlq","slug":"vrlq","records":1,"summary":"Rotates the contents of a vector register left by a specified number of bits.","page":"https://instructionsets.com/powerisa/vrlq/","api":"https://instructionsets.com/api/v1/powerisa/vrlq.json"},{"mnemonic":"vrlqnm","slug":"vrlqnm","records":1,"summary":"Rotates the contents of a vector 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vector register.","page":"https://instructionsets.com/powerisa/vspltisw/","api":"https://instructionsets.com/api/v1/powerisa/vspltisw.json"},{"mnemonic":"vspltw","slug":"vspltw","records":1,"summary":"Copies a single word element from the source vector into all four word elements of the destination.","page":"https://instructionsets.com/powerisa/vspltw/","api":"https://instructionsets.com/api/v1/powerisa/vspltw.json"},{"mnemonic":"vsr","slug":"vsr","records":1,"summary":"Shifts vector right by octet count in vB.","page":"https://instructionsets.com/powerisa/vsr/","api":"https://instructionsets.com/api/v1/powerisa/vsr.json"},{"mnemonic":"vsrab","slug":"vsrab","records":1,"summary":"Shifts each byte of the source vector right by a specified number of bits, filling vacated bits with copies of the sign bit.","page":"https://instructionsets.com/powerisa/vsrab/","api":"https://instructionsets.com/api/v1/powerisa/vsrab.json"},{"mnemonic":"vsrah","slug":"vsrah","records":1,"summary":"Arithmetic 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bits.","page":"https://instructionsets.com/powerisa/vsrb/","api":"https://instructionsets.com/api/v1/powerisa/vsrb.json"},{"mnemonic":"vsrh","slug":"vsrh","records":1,"summary":"Shifts the contents of each element in a vector right by a specified number of bits.","page":"https://instructionsets.com/powerisa/vsrh/","api":"https://instructionsets.com/api/v1/powerisa/vsrh.json"},{"mnemonic":"vsro","slug":"vsro","records":1,"summary":"Shifts vector right by byte count.","page":"https://instructionsets.com/powerisa/vsro/","api":"https://instructionsets.com/api/v1/powerisa/vsro.json"},{"mnemonic":"vsrq","slug":"vsrq","records":1,"summary":"Shifts the contents of a vector register right by a specified number of bits.","page":"https://instructionsets.com/powerisa/vsrq/","api":"https://instructionsets.com/api/v1/powerisa/vsrq.json"},{"mnemonic":"vsrv","slug":"vsrv","records":1,"summary":"Shifts each element of the source vector right by a variable amount specified in another vector.","page":"https://instructionsets.com/powerisa/vsrv/","api":"https://instructionsets.com/api/v1/powerisa/vsrv.json"},{"mnemonic":"vsrw","slug":"vsrw","records":1,"summary":"Shifts each word element of the source vector right by a specified number of bits.","page":"https://instructionsets.com/powerisa/vsrw/","api":"https://instructionsets.com/api/v1/powerisa/vsrw.json"},{"mnemonic":"vstribl","slug":"vstribl","records":1,"summary":"Stores the leftmost byte of each element in a vector register to memory.","page":"https://instructionsets.com/powerisa/vstribl/","api":"https://instructionsets.com/api/v1/powerisa/vstribl.json"},{"mnemonic":"vstribr","slug":"vstribr","records":1,"summary":"Isolates the rightmost non-zero byte in a vector string and shifts it to the left.","page":"https://instructionsets.com/powerisa/vstribr/","api":"https://instructionsets.com/api/v1/powerisa/vstribr.json"},{"mnemonic":"vstribr.","slug":"vstribr_","records":1,"summary":"Isolates the rightmost non-zero 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65536.","page":"https://instructionsets.com/powerisa/vsubuhm/","api":"https://instructionsets.com/api/v1/powerisa/vsubuhm.json"},{"mnemonic":"vsubuhs","slug":"vsubuhs","records":1,"summary":"Subtracts 8 unsigned halfwords with saturation.","page":"https://instructionsets.com/powerisa/vsubuhs/","api":"https://instructionsets.com/api/v1/powerisa/vsubuhs.json"},{"mnemonic":"vsubuqm","slug":"vsubuqm","records":1,"summary":"Subtracts the contents of two vector registers and places the result in another vector register, modulo operation.","page":"https://instructionsets.com/powerisa/vsubuqm/","api":"https://instructionsets.com/api/v1/powerisa/vsubuqm.json"},{"mnemonic":"vsubuwm","slug":"vsubuwm","records":1,"summary":"Subtracts the contents of two vector registers and updates the result in another vector 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vectors.","page":"https://instructionsets.com/powerisa/vxor/","api":"https://instructionsets.com/api/v1/powerisa/vxor.json"},{"mnemonic":"wait","slug":"wait","records":1,"summary":"Stops instruction execution and places the processor in a lower power state until an interrupt occurs.","page":"https://instructionsets.com/powerisa/wait/","api":"https://instructionsets.com/api/v1/powerisa/wait.json"},{"mnemonic":"waitimpl","slug":"waitimpl","records":1,"summary":"Waits for a specific implementation event.","page":"https://instructionsets.com/powerisa/waitimpl/","api":"https://instructionsets.com/api/v1/powerisa/waitimpl.json"},{"mnemonic":"waitrsv","slug":"waitrsv","records":1,"summary":"Waits until a reservation is lost (Multithreading sync).","page":"https://instructionsets.com/powerisa/waitrsv/","api":"https://instructionsets.com/api/v1/powerisa/waitrsv.json"},{"mnemonic":"wrtee","slug":"wrtee","records":1,"summary":"Updates the EE bit of the MSR from a GPR.","page":"https://instructionsets.com/powerisa/wrtee/","api":"https://instructionsets.com/api/v1/powerisa/wrtee.json"},{"mnemonic":"wrteei","slug":"wrteei","records":1,"summary":"Updates the EE bit of the MSR from an immediate.","page":"https://instructionsets.com/powerisa/wrteei/","api":"https://instructionsets.com/api/v1/powerisa/wrteei.json"},{"mnemonic":"xmsubasp","slug":"xmsubasp","records":1,"summary":"Performs a multiply-subtract operation on single-precision floating-point values.","page":"https://instructionsets.com/powerisa/xmsubasp/","api":"https://instructionsets.com/api/v1/powerisa/xmsubasp.json"},{"mnemonic":"xor","slug":"xor","records":1,"summary":"Performs a bitwise Exclusive OR comparison.","page":"https://instructionsets.com/powerisa/xor/","api":"https://instructionsets.com/api/v1/powerisa/xor.json"},{"mnemonic":"xori","slug":"xori","records":1,"summary":"Performs a bitwise XOR with a 16-bit unsigned immediate.","page":"https://instructionsets.com/powerisa/xori/","api":"https://instructionsets.com/api/v1/powerisa/xori.json"},{"mnemonic":"xoris","slug":"xoris","records":1,"summary":"Performs a bitwise XOR with a 16-bit immediate shifted left by 16 bits.","page":"https://instructionsets.com/powerisa/xoris/","api":"https://instructionsets.com/api/v1/powerisa/xoris.json"},{"mnemonic":"xsabsdp","slug":"xsabsdp","records":1,"summary":"Computes the absolute value of a double-precision floating-point number.","page":"https://instructionsets.com/powerisa/xsabsdp/","api":"https://instructionsets.com/api/v1/powerisa/xsabsdp.json"},{"mnemonic":"xsabsqp","slug":"xsabsqp","records":1,"summary":"Computes the absolute value of a quad-precision floating-point number.","page":"https://instructionsets.com/powerisa/xsabsqp/","api":"https://instructionsets.com/api/v1/powerisa/xsabsqp.json"},{"mnemonic":"xsadddp","slug":"xsadddp","records":1,"summary":"Adds two double-precision floating-point values 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single-precision floating-point vectors and sets the target vector elements to all 1s if the corresponding source elements are greater than or equal, otherwise all 0s.","page":"https://instructionsets.com/powerisa/xvcmpgesp_/","api":"https://instructionsets.com/api/v1/powerisa/xvcmpgesp_.json"},{"mnemonic":"xvcmpgtdp","slug":"xvcmpgtdp","records":1,"summary":"Compares two double-precision floating-point values and sets the target vector register based on the comparison.","page":"https://instructionsets.com/powerisa/xvcmpgtdp/","api":"https://instructionsets.com/api/v1/powerisa/xvcmpgtdp.json"},{"mnemonic":"xvcmpgtdp.","slug":"xvcmpgtdp_","records":1,"summary":"Compares two double-precision floating-point values and sets the target vector register based on the comparison.","page":"https://instructionsets.com/powerisa/xvcmpgtdp_/","api":"https://instructionsets.com/api/v1/powerisa/xvcmpgtdp_.json"},{"mnemonic":"xvcmpgtsp","slug":"xvcmpgtsp","records":1,"summary":"Compares each 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register.","page":"https://instructionsets.com/powerisa/xvi8ger4/","api":"https://instructionsets.com/api/v1/powerisa/xvi8ger4.json"},{"mnemonic":"xvi8ger4pp","slug":"xvi8ger4pp","records":1,"summary":"Signed/Unsigned variations of 8-bit matrix multiply accumulate.","page":"https://instructionsets.com/powerisa/xvi8ger4pp/","api":"https://instructionsets.com/api/v1/powerisa/xvi8ger4pp.json"},{"mnemonic":"xvi8ger4spp","slug":"xvi8ger4spp","records":1,"summary":"Performs a vector-scalar operation on 8-bit signed and unsigned integers with saturation.","page":"https://instructionsets.com/powerisa/xvi8ger4spp/","api":"https://instructionsets.com/api/v1/powerisa/xvi8ger4spp.json"},{"mnemonic":"xviexpdp","slug":"xviexpdp","records":1,"summary":"Inserts the exponent from one vector register into another for double-precision floating-point numbers.","page":"https://instructionsets.com/powerisa/xviexpdp/","api":"https://instructionsets.com/api/v1/powerisa/xviexpdp.json"},{"mnemonic":"xvmaddadp","slug":"xvmaddadp","records":1,"summary":"Performs a double-precision floating-point multiply-add operation on vector elements.","page":"https://instructionsets.com/powerisa/xvmaddadp/","api":"https://instructionsets.com/api/v1/powerisa/xvmaddadp.json"},{"mnemonic":"xvmaddasp","slug":"xvmaddasp","records":1,"summary":"Performs a single-precision floating-point multiply-add operation on vector elements.","page":"https://instructionsets.com/powerisa/xvmaddasp/","api":"https://instructionsets.com/api/v1/powerisa/xvmaddasp.json"},{"mnemonic":"xvmaxdp","slug":"xvmaxdp","records":1,"summary":"Compares two double-precision floating-point values and selects the maximum value for each element.","page":"https://instructionsets.com/powerisa/xvmaxdp/","api":"https://instructionsets.com/api/v1/powerisa/xvmaxdp.json"},{"mnemonic":"xvmaxsp","slug":"xvmaxsp","records":1,"summary":"Computes the maximum of corresponding single-precision floating-point elements in two vector registers and stores the result in a third vector register.","page":"https://instructionsets.com/powerisa/xvmaxsp/","api":"https://instructionsets.com/api/v1/powerisa/xvmaxsp.json"},{"mnemonic":"xvmindp","slug":"xvmindp","records":1,"summary":"Compares two double-precision floating-point values and selects the minimum value for each element.","page":"https://instructionsets.com/powerisa/xvmindp/","api":"https://instructionsets.com/api/v1/powerisa/xvmindp.json"},{"mnemonic":"xvminsp","slug":"xvminsp","records":1,"summary":"Performs a minimum operation on single-precision floating-point values from two vector scalar registers and stores the result in another vector scalar register.","page":"https://instructionsets.com/powerisa/xvminsp/","api":"https://instructionsets.com/api/v1/powerisa/xvminsp.json"},{"mnemonic":"xvmsubadp","slug":"xvmsubadp","records":1,"summary":"Performs a double-precision floating-point multiply-subtract operation on vector elements.","page":"https://instructionsets.com/powerisa/xvmsubadp/","api":"https://instructionsets.com/api/v1/powerisa/xvmsubadp.json"},{"mnemonic":"xvmsubasp","slug":"xvmsubasp","records":1,"summary":"Performs a vector multiply-subtract operation on single-precision floating-point values.","page":"https://instructionsets.com/powerisa/xvmsubasp/","api":"https://instructionsets.com/api/v1/powerisa/xvmsubasp.json"},{"mnemonic":"xvmsubmdp","slug":"xvmsubmdp","records":1,"summary":"Multiplies corresponding double-precision floating-point elements of two VSX registers, subtracts the corresponding element of a third register, and stores the results, using the Type-M (multiplicand) form.","page":"https://instructionsets.com/powerisa/xvmsubmdp/","api":"https://instructionsets.com/api/v1/powerisa/xvmsubmdp.json"},{"mnemonic":"xvmuldp","slug":"xvmuldp","records":1,"summary":"Multiplies two double-precision floating-point numbers in vector registers and stores the result.","page":"https://instructionsets.com/powerisa/xvmuldp/","api":"https://instructionsets.com/api/v1/powerisa/xvmuldp.json"},{"mnemonic":"xvmulsp","slug":"xvmulsp","records":1,"summary":"Multiplies the contents of two single-precision floating-point values and places the result into a vector register.","page":"https://instructionsets.com/powerisa/xvmulsp/","api":"https://instructionsets.com/api/v1/powerisa/xvmulsp.json"},{"mnemonic":"xvnabsdp","slug":"xvnabsdp","records":1,"summary":"Computes the negative absolute value of each double-precision floating-point element in a vector.","page":"https://instructionsets.com/powerisa/xvnabsdp/","api":"https://instructionsets.com/api/v1/powerisa/xvnabsdp.json"},{"mnemonic":"xvnegdp","slug":"xvnegdp","records":1,"summary":"Negates the contents of a double-precision floating-point vector register and stores the result in another vector register.","page":"https://instructionsets.com/powerisa/xvnegdp/","api":"https://instructionsets.com/api/v1/powerisa/xvnegdp.json"},{"mnemonic":"xvnegsp","slug":"xvnegsp","records":1,"summary":"Negates the contents of a single-precision floating-point register.","page":"https://instructionsets.com/powerisa/xvnegsp/","api":"https://instructionsets.com/api/v1/powerisa/xvnegsp.json"},{"mnemonic":"xvnmaddadp","slug":"xvnmaddadp","records":1,"summary":"Performs a negative multiply-add operation on double-precision floating-point elements.","page":"https://instructionsets.com/powerisa/xvnmaddadp/","api":"https://instructionsets.com/api/v1/powerisa/xvnmaddadp.json"},{"mnemonic":"xvnmaddasp","slug":"xvnmaddasp","records":1,"summary":"Performs a negative multiply-add operation on single-precision floating-point elements.","page":"https://instructionsets.com/powerisa/xvnmaddasp/","api":"https://instructionsets.com/api/v1/powerisa/xvnmaddasp.json"},{"mnemonic":"xvnmaddmsp","slug":"xvnmaddmsp","records":1,"summary":"Performs a vector single-precision floating-point negative multiply-add operation (Type-M), computing the negation of (XB * XT + XA) for each single-precision element.","page":"https://instructionsets.com/powerisa/xvnmaddmsp/","api":"https://instructionsets.com/api/v1/powerisa/xvnmaddmsp.json"},{"mnemonic":"xvnmsubadp","slug":"xvnmsubadp","records":1,"summary":"Performs a negative multiply-subtract operation on double-precision floating-point elements.","page":"https://instructionsets.com/powerisa/xvnmsubadp/","api":"https://instructionsets.com/api/v1/powerisa/xvnmsubadp.json"},{"mnemonic":"xvnmsubasp","slug":"xvnmsubasp","records":1,"summary":"Performs a negative multiply-subtract operation on single-precision floating-point elements.","page":"https://instructionsets.com/powerisa/xvnmsubasp/","api":"https://instructionsets.com/api/v1/powerisa/xvnmsubasp.json"},{"mnemonic":"xvnmsubmdp","slug":"xvnmsubmdp","records":1,"summary":"Performs a negative multiply-subtract operation on double-precision floating-point values.","page":"https://instructionsets.com/powerisa/xvnmsubmdp/","api":"https://instructionsets.com/api/v1/powerisa/xvnmsubmdp.json"},{"mnemonic":"xvrdpi","slug":"xvrdpi","records":1,"summary":"Rounds each element of a double-precision floating-point vector to the nearest integer away from zero.","page":"https://instructionsets.com/powerisa/xvrdpi/","api":"https://instructionsets.com/api/v1/powerisa/xvrdpi.json"},{"mnemonic":"xvrdpic","slug":"xvrdpic","records":1,"summary":"Rounds each double-precision floating-point element of a vector to an integer using the current rounding mode.","page":"https://instructionsets.com/powerisa/xvrdpic/","api":"https://instructionsets.com/api/v1/powerisa/xvrdpic.json"},{"mnemonic":"xvrdpim","slug":"xvrdpim","records":1,"summary":"Rounds the contents of a vector register towards negative infinity and stores the result in another vector register.","page":"https://instructionsets.com/powerisa/xvrdpim/","api":"https://instructionsets.com/api/v1/powerisa/xvrdpim.json"},{"mnemonic":"xvrdpiz","slug":"xvrdpiz","records":1,"summary":"Rounds each double-precision floating-point element in a vector towards zero and stores the result as an integer.","page":"https://instructionsets.com/powerisa/xvrdpiz/","api":"https://instructionsets.com/api/v1/powerisa/xvrdpiz.json"},{"mnemonic":"xvredp","slug":"xvredp","records":1,"summary":"A double-precision floating-point estimate of the reciprocal of src is placed into doubleword element i of VSR[XT] in double-precision format.","page":"https://instructionsets.com/powerisa/xvredp/","api":"https://instructionsets.com/api/v1/powerisa/xvredp.json"},{"mnemonic":"xvresp","slug":"xvresp","records":1,"summary":"Estimates the reciprocal of single-precision floating-point values in a vector.","page":"https://instructionsets.com/powerisa/xvresp/","api":"https://instructionsets.com/api/v1/powerisa/xvresp.json"},{"mnemonic":"xvrspi","slug":"xvrspi","records":1,"summary":"Rounds each element of a vector from single-precision floating-point format to an integer using round to Nearest Away.","page":"https://instructionsets.com/powerisa/xvrspi/","api":"https://instructionsets.com/api/v1/powerisa/xvrspi.json"},{"mnemonic":"xvrspic","slug":"xvrspic","records":1,"summary":"Rounds each single-precision floating-point element of a vector to an integer using the current rounding mode.","page":"https://instructionsets.com/powerisa/xvrspic/","api":"https://instructionsets.com/api/v1/powerisa/xvrspic.json"},{"mnemonic":"xvrspim","slug":"xvrspim","records":1,"summary":"Rounds each element of a vector from single-precision floating-point format to integer format, rounding towards negative infinity.","page":"https://instructionsets.com/powerisa/xvrspim/","api":"https://instructionsets.com/api/v1/powerisa/xvrspim.json"},{"mnemonic":"xvrspiz","slug":"xvrspiz","records":1,"summary":"Rounds each single-precision floating-point element of a vector towards zero and stores the result in another vector.","page":"https://instructionsets.com/powerisa/xvrspiz/","api":"https://instructionsets.com/api/v1/powerisa/xvrspiz.json"},{"mnemonic":"xvrsqrtedp","slug":"xvrsqrtedp","records":1,"summary":"Estimates the reciprocal square root of double-precision floating-point values in vector registers.","page":"https://instructionsets.com/powerisa/xvrsqrtedp/","api":"https://instructionsets.com/api/v1/powerisa/xvrsqrtedp.json"},{"mnemonic":"xvrsqrtesp","slug":"xvrsqrtesp","records":1,"summary":"Estimates the reciprocal square root of single-precision floating-point values in a vector.","page":"https://instructionsets.com/powerisa/xvrsqrtesp/","api":"https://instructionsets.com/api/v1/powerisa/xvrsqrtesp.json"},{"mnemonic":"xvsqrtdp","slug":"xvsqrtdp","records":1,"summary":"Computes the square root of each double-precision floating-point element in a vector.","page":"https://instructionsets.com/powerisa/xvsqrtdp/","api":"https://instructionsets.com/api/v1/powerisa/xvsqrtdp.json"},{"mnemonic":"xvsqrtsp","slug":"xvsqrtsp","records":1,"summary":"Computes the square root of each single-precision floating-point element in a vector.","page":"https://instructionsets.com/powerisa/xvsqrtsp/","api":"https://instructionsets.com/api/v1/powerisa/xvsqrtsp.json"},{"mnemonic":"xvsubdp","slug":"xvsubdp","records":1,"summary":"Subtracts the contents of two vector registers and places the result in a target vector register.","page":"https://instructionsets.com/powerisa/xvsubdp/","api":"https://instructionsets.com/api/v1/powerisa/xvsubdp.json"},{"mnemonic":"xvsubsp","slug":"xvsubsp","records":1,"summary":"Subtracts the contents of two vector registers and places the result in another vector register.","page":"https://instructionsets.com/powerisa/xvsubsp/","api":"https://instructionsets.com/api/v1/powerisa/xvsubsp.json"},{"mnemonic":"xvtdivdp","slug":"xvtdivdp","records":1,"summary":"Performs a double-precision floating-point division on vector elements and sets condition flags based on the results.","page":"https://instructionsets.com/powerisa/xvtdivdp/","api":"https://instructionsets.com/api/v1/powerisa/xvtdivdp.json"},{"mnemonic":"xvtdivsp","slug":"xvtdivsp","records":1,"summary":"Performs a vectorized single-precision floating-point division test.","page":"https://instructionsets.com/powerisa/xvtdivsp/","api":"https://instructionsets.com/api/v1/powerisa/xvtdivsp.json"},{"mnemonic":"xvtlsbb","slug":"xvtlsbb","records":1,"summary":"Tests the least-significant bit of each byte in a VSX vector register and sets a condition register field based on the results.","page":"https://instructionsets.com/powerisa/xvtlsbb/","api":"https://instructionsets.com/api/v1/powerisa/xvtlsbb.json"},{"mnemonic":"xvtsqrtdp","slug":"xvtsqrtdp","records":1,"summary":"Tests the double-precision floating-point operands in VSR[XB] and sets condition register field BF based on certain conditions.","page":"https://instructionsets.com/powerisa/xvtsqrtdp/","api":"https://instructionsets.com/api/v1/powerisa/xvtsqrtdp.json"},{"mnemonic":"xvtsqrtsp","slug":"xvtsqrtsp","records":1,"summary":"Tests each element of a vector for conditions related to square root operations.","page":"https://instructionsets.com/powerisa/xvtsqrtsp/","api":"https://instructionsets.com/api/v1/powerisa/xvtsqrtsp.json"},{"mnemonic":"xvtstdcdp","slug":"xvtstdcdp","records":1,"summary":"Tests each double-precision floating-point element in a vector against specified data classes and sets the corresponding elements in another vector to either all ones or all zeros based on the match.","page":"https://instructionsets.com/powerisa/xvtstdcdp/","api":"https://instructionsets.com/api/v1/powerisa/xvtstdcdp.json"},{"mnemonic":"xvtstdcsp","slug":"xvtstdcsp","records":1,"summary":"Tests each single-precision floating-point element in a vector against specified data classes and sets the corresponding elements in another vector based on the match.","page":"https://instructionsets.com/powerisa/xvtstdcsp/","api":"https://instructionsets.com/api/v1/powerisa/xvtstdcsp.json"},{"mnemonic":"xvxexpdp","slug":"xvxexpdp","records":1,"summary":"Extracts the exponent from each double-precision floating-point value in a vector and places it into another vector.","page":"https://instructionsets.com/powerisa/xvxexpdp/","api":"https://instructionsets.com/api/v1/powerisa/xvxexpdp.json"},{"mnemonic":"xvxsigdp","slug":"xvxsigdp","records":1,"summary":"Extracts the significand of double-precision floating-point values from a vector register and places them into another vector register.","page":"https://instructionsets.com/powerisa/xvxsigdp/","api":"https://instructionsets.com/api/v1/powerisa/xvxsigdp.json"},{"mnemonic":"xxblendvb","slug":"xxblendvb","records":1,"summary":"Selects bytes from XA or XB based on the MSB of bytes in XC.","page":"https://instructionsets.com/powerisa/xxblendvb/","api":"https://instructionsets.com/api/v1/powerisa/xxblendvb.json"},{"mnemonic":"xxblendvd","slug":"xxblendvd","records":1,"summary":"Selects doublewords from XA or XB based on the MSB of doublewords in XC.","page":"https://instructionsets.com/powerisa/xxblendvd/","api":"https://instructionsets.com/api/v1/powerisa/xxblendvd.json"},{"mnemonic":"xxblendvh","slug":"xxblendvh","records":1,"summary":"Selects halfwords from XA or XB based on the MSB of halfwords in XC.","page":"https://instructionsets.com/powerisa/xxblendvh/","api":"https://instructionsets.com/api/v1/powerisa/xxblendvh.json"},{"mnemonic":"xxblendvw","slug":"xxblendvw","records":1,"summary":"Selects words from XA or XB based on the MSB of words in XC.","page":"https://instructionsets.com/powerisa/xxblendvw/","api":"https://instructionsets.com/api/v1/powerisa/xxblendvw.json"},{"mnemonic":"xxbrd","slug":"xxbrd","records":1,"summary":"Reverses the bytes of each doubleword element in a vector register.","page":"https://instructionsets.com/powerisa/xxbrd/","api":"https://instructionsets.com/api/v1/powerisa/xxbrd.json"},{"mnemonic":"xxbrh","slug":"xxbrh","records":1,"summary":"Reverses the bytes of each halfword in a vector register.","page":"https://instructionsets.com/powerisa/xxbrh/","api":"https://instructionsets.com/api/v1/powerisa/xxbrh.json"},{"mnemonic":"xxbrw","slug":"xxbrw","records":1,"summary":"Reverses the bytes of each word in a vector register.","page":"https://instructionsets.com/powerisa/xxbrw/","api":"https://instructionsets.com/api/v1/powerisa/xxbrw.json"},{"mnemonic":"xxeval","slug":"xxeval","records":1,"summary":"Performs an arbitrary 3-input boolean logic function (LUT3) on vectors. The 8-bit immediate 'IMM' defines the truth table.","page":"https://instructionsets.com/powerisa/xxeval/","api":"https://instructionsets.com/api/v1/powerisa/xxeval.json"},{"mnemonic":"xxextractuw","slug":"xxextractuw","records":1,"summary":"Extracts an unsigned word from a vector register and places it into another vector register.","page":"https://instructionsets.com/powerisa/xxextractuw/","api":"https://instructionsets.com/api/v1/powerisa/xxextractuw.json"},{"mnemonic":"xxgenpcvbm","slug":"xxgenpcvbm","records":1,"summary":"Generates a permute control vector based on the byte mask in VSR[VRB+32].","page":"https://instructionsets.com/powerisa/xxgenpcvbm/","api":"https://instructionsets.com/api/v1/powerisa/xxgenpcvbm.json"},{"mnemonic":"xxgenpcvdm","slug":"xxgenpcvdm","records":1,"summary":"Generates a permute control vector (PCV) based on the doubleword mask in VSR[VRB+32] and stores it in VSR[XT].","page":"https://instructionsets.com/powerisa/xxgenpcvdm/","api":"https://instructionsets.com/api/v1/powerisa/xxgenpcvdm.json"},{"mnemonic":"xxgenpcvhm","slug":"xxgenpcvhm","records":1,"summary":"Generates a permute control vector (PCV) based on the halfword mask in VSR[VRB+32].","page":"https://instructionsets.com/powerisa/xxgenpcvhm/","api":"https://instructionsets.com/api/v1/powerisa/xxgenpcvhm.json"},{"mnemonic":"xxgenpcvwm","slug":"xxgenpcvwm","records":1,"summary":"Generates a permute control vector (PCV) based on the word mask in VSR[VRB+32] and stores it in VSR[XT].","page":"https://instructionsets.com/powerisa/xxgenpcvwm/","api":"https://instructionsets.com/api/v1/powerisa/xxgenpcvwm.json"},{"mnemonic":"xxinsertw","slug":"xxinsertw","records":1,"summary":"Inserts a 32-bit word from a GPR into a specific element of a VSR.","page":"https://instructionsets.com/powerisa/xxinsertw/","api":"https://instructionsets.com/api/v1/powerisa/xxinsertw.json"},{"mnemonic":"xxland","slug":"xxland","records":1,"summary":"Performs a bitwise AND operation on the contents of two vector registers and stores the result in another vector register.","page":"https://instructionsets.com/powerisa/xxland/","api":"https://instructionsets.com/api/v1/powerisa/xxland.json"},{"mnemonic":"xxlandc","slug":"xxlandc","records":1,"summary":"vD = vA & ~vB","page":"https://instructionsets.com/powerisa/xxlandc/","api":"https://instructionsets.com/api/v1/powerisa/xxlandc.json"},{"mnemonic":"xxleqv","slug":"xxleqv","records":1,"summary":"vD = ~(vA ^ vB) (XNOR)","page":"https://instructionsets.com/powerisa/xxleqv/","api":"https://instructionsets.com/api/v1/powerisa/xxleqv.json"},{"mnemonic":"xxlnand","slug":"xxlnand","records":1,"summary":"vD = ~(vA & vB)","page":"https://instructionsets.com/powerisa/xxlnand/","api":"https://instructionsets.com/api/v1/powerisa/xxlnand.json"},{"mnemonic":"xxlnor","slug":"xxlnor","records":1,"summary":"Performs a logical NOR operation on the contents of two VSX registers and stores the result in another VSX register.","page":"https://instructionsets.com/powerisa/xxlnor/","api":"https://instructionsets.com/api/v1/powerisa/xxlnor.json"},{"mnemonic":"xxlor","slug":"xxlor","records":1,"summary":"Bitwise OR.","page":"https://instructionsets.com/powerisa/xxlor/","api":"https://instructionsets.com/api/v1/powerisa/xxlor.json"},{"mnemonic":"xxlorc","slug":"xxlorc","records":1,"summary":"vD = vA | ~vB","page":"https://instructionsets.com/powerisa/xxlorc/","api":"https://instructionsets.com/api/v1/powerisa/xxlorc.json"},{"mnemonic":"xxlxor","slug":"xxlxor","records":1,"summary":"Bitwise XOR.","page":"https://instructionsets.com/powerisa/xxlxor/","api":"https://instructionsets.com/api/v1/powerisa/xxlxor.json"},{"mnemonic":"xxmfacc","slug":"xxmfacc","records":1,"summary":"Copies data from an Accumulator back to 4 adjacent VSRs.","page":"https://instructionsets.com/powerisa/xxmfacc/","api":"https://instructionsets.com/api/v1/powerisa/xxmfacc.json"},{"mnemonic":"xxmrghd","slug":"xxmrghd","records":1,"summary":"Merges high doublewords from XA and XB.","page":"https://instructionsets.com/powerisa/xxmrghd/","api":"https://instructionsets.com/api/v1/powerisa/xxmrghd.json"},{"mnemonic":"xxmrghw","slug":"xxmrghw","records":1,"summary":"Merges the high words of two VSX registers into a target VSX register.","page":"https://instructionsets.com/powerisa/xxmrghw/","api":"https://instructionsets.com/api/v1/powerisa/xxmrghw.json"},{"mnemonic":"xxmrgld","slug":"xxmrgld","records":1,"summary":"Merges low doublewords from XA and XB.","page":"https://instructionsets.com/powerisa/xxmrgld/","api":"https://instructionsets.com/api/v1/powerisa/xxmrgld.json"},{"mnemonic":"xxmrglw","slug":"xxmrglw","records":1,"summary":"Merges low words from two VSRs.","page":"https://instructionsets.com/powerisa/xxmrglw/","api":"https://instructionsets.com/api/v1/powerisa/xxmrglw.json"},{"mnemonic":"xxmtacc","slug":"xxmtacc","records":1,"summary":"Copies data from 4 adjacent VSRs into an Accumulator.","page":"https://instructionsets.com/powerisa/xxmtacc/","api":"https://instructionsets.com/api/v1/powerisa/xxmtacc.json"},{"mnemonic":"xxperm","slug":"xxperm","records":1,"summary":"Performs a vector permute operation on the contents of three VSX registers.","page":"https://instructionsets.com/powerisa/xxperm/","api":"https://instructionsets.com/api/v1/powerisa/xxperm.json"},{"mnemonic":"xxpermdi","slug":"xxpermdi","records":1,"summary":"Selects two doublewords from the four available in source registers XA and XB based on a 2-bit selector.","page":"https://instructionsets.com/powerisa/xxpermdi/","api":"https://instructionsets.com/api/v1/powerisa/xxpermdi.json"},{"mnemonic":"xxpermr","slug":"xxpermr","records":1,"summary":"Little-endian optimized permute.","page":"https://instructionsets.com/powerisa/xxpermr/","api":"https://instructionsets.com/api/v1/powerisa/xxpermr.json"},{"mnemonic":"xxpermx","slug":"xxpermx","records":1,"summary":"Permutes bytes from two source vectors using a control vector and a 3-bit selector.","page":"https://instructionsets.com/powerisa/xxpermx/","api":"https://instructionsets.com/api/v1/powerisa/xxpermx.json"},{"mnemonic":"xxsel","slug":"xxsel","records":1,"summary":"Selects elements from two source vectors based on a mask vector.","page":"https://instructionsets.com/powerisa/xxsel/","api":"https://instructionsets.com/api/v1/powerisa/xxsel.json"},{"mnemonic":"xxsetaccz","slug":"xxsetaccz","records":1,"summary":"Clears a 512-bit Accumulator register (composed of 4 VSRs) to zero.","page":"https://instructionsets.com/powerisa/xxsetaccz/","api":"https://instructionsets.com/api/v1/powerisa/xxsetaccz.json"},{"mnemonic":"xxsldwi","slug":"xxsldwi","records":1,"summary":"Shifts the contents of two vector registers left by a specified number of words and places the result into another vector register.","page":"https://instructionsets.com/powerisa/xxsldwi/","api":"https://instructionsets.com/api/v1/powerisa/xxsldwi.json"},{"mnemonic":"xxsplti32dx","slug":"xxsplti32dx","records":1,"summary":"Splats a 32-bit immediate into a doubleword index.","page":"https://instructionsets.com/powerisa/xxsplti32dx/","api":"https://instructionsets.com/api/v1/powerisa/xxsplti32dx.json"},{"mnemonic":"xxspltib","slug":"xxspltib","records":1,"summary":"Copies an immediate byte value into each byte element of a vector register.","page":"https://instructionsets.com/powerisa/xxspltib/","api":"https://instructionsets.com/api/v1/powerisa/xxspltib.json"},{"mnemonic":"xxspltidp","slug":"xxspltidp","records":1,"summary":"Spatially duplicates a 32-bit immediate (converted to double) into both double elements.","page":"https://instructionsets.com/powerisa/xxspltidp/","api":"https://instructionsets.com/api/v1/powerisa/xxspltidp.json"},{"mnemonic":"xxspltiw","slug":"xxspltiw","records":1,"summary":"Spatially duplicates a 32-bit immediate into all 4 words of the target.","page":"https://instructionsets.com/powerisa/xxspltiw/","api":"https://instructionsets.com/api/v1/powerisa/xxspltiw.json"},{"mnemonic":"xxspltw","slug":"xxspltw","records":1,"summary":"Replicates a word element from one vector register into all elements of another vector register.","page":"https://instructionsets.com/powerisa/xxspltw/","api":"https://instructionsets.com/api/v1/powerisa/xxspltw.json"},{"mnemonic":"xxswapd","slug":"xxswapd","records":1,"summary":"Swaps the two doublewords in the register.","page":"https://instructionsets.com/powerisa/xxswapd/","api":"https://instructionsets.com/api/v1/powerisa/xxswapd.json"}]}