{"api_version":"1","snapshot":"2026-10-08","licence":"CC0-1.0","architecture":"ARM","records":1145,"mnemonics":[{"mnemonic":"abs","slug":"abs","records":2,"summary":"Calculates absolute value of integers.","page":"https://instructionsets.com/arm/abs/","api":"https://instructionsets.com/api/v1/arm/abs.json"},{"mnemonic":"adc","slug":"adc","records":3,"summary":"Adds two register values and the Carry flag.","page":"https://instructionsets.com/arm/adc/","api":"https://instructionsets.com/api/v1/arm/adc.json"},{"mnemonic":"adc.w","slug":"adc_w","records":1,"summary":"Thumb-2 32-bit add with carry (Access high registers/large constants).","page":"https://instructionsets.com/arm/adc_w/","api":"https://instructionsets.com/api/v1/arm/adc_w.json"},{"mnemonic":"adcs","slug":"adcs","records":2,"summary":"Adds two register values and Carry, updating NZCV flags.","page":"https://instructionsets.com/arm/adcs/","api":"https://instructionsets.com/api/v1/arm/adcs.json"},{"mnemonic":"add","slug":"add","records":9,"summary":"Adds a register value and a sign/zero-extended register value.","page":"https://instructionsets.com/arm/add/#add-extended-register","api":"https://instructionsets.com/api/v1/arm/add.json"},{"mnemonic":"add.w","slug":"add_w","records":1,"summary":"Thumb-2 32-bit add.","page":"https://instructionsets.com/arm/add_w/","api":"https://instructionsets.com/api/v1/arm/add_w.json"},{"mnemonic":"addg","slug":"addg","records":1,"summary":"Adds an immediate to an address, modifying the Allocation Tag (MTE).","page":"https://instructionsets.com/arm/addg/","api":"https://instructionsets.com/api/v1/arm/addg.json"},{"mnemonic":"addp","slug":"addp","records":2,"summary":"Adds two 64-bit values to a 64-bit result (Scalar NEON).","page":"https://instructionsets.com/arm/addp/","api":"https://instructionsets.com/api/v1/arm/addp.json"},{"mnemonic":"adds","slug":"adds","records":6,"summary":"Adds and updates flags (Extended Register).","page":"https://instructionsets.com/arm/adds/","api":"https://instructionsets.com/api/v1/arm/adds.json"},{"mnemonic":"addv","slug":"addv","records":1,"summary":"Adds all elements of the vector into a scalar result.","page":"https://instructionsets.com/arm/addv/","api":"https://instructionsets.com/api/v1/arm/addv.json"},{"mnemonic":"adr","slug":"adr","records":3,"summary":"Calculates the address of a label (PC +/- 1MB range).","page":"https://instructionsets.com/arm/adr/","api":"https://instructionsets.com/api/v1/arm/adr.json"},{"mnemonic":"adr.w","slug":"adr_w","records":1,"summary":"Thumb-2 32-bit ADR.","page":"https://instructionsets.com/arm/adr_w/","api":"https://instructionsets.com/api/v1/arm/adr_w.json"},{"mnemonic":"adrp","slug":"adrp","records":1,"summary":"Calculates page address of a label (PC +/- 4GB range).","page":"https://instructionsets.com/arm/adrp/","api":"https://instructionsets.com/api/v1/arm/adrp.json"},{"mnemonic":"aesd","slug":"aesd","records":3,"summary":"Performs one round of AES decryption (AArch32).","page":"https://instructionsets.com/arm/aesd/","api":"https://instructionsets.com/api/v1/arm/aesd.json"},{"mnemonic":"aese","slug":"aese","records":3,"summary":"Performs one round of AES encryption (AArch32).","page":"https://instructionsets.com/arm/aese/","api":"https://instructionsets.com/api/v1/arm/aese.json"},{"mnemonic":"aesimc","slug":"aesimc","records":2,"summary":"AES Inverse Mix Columns transformation.","page":"https://instructionsets.com/arm/aesimc/","api":"https://instructionsets.com/api/v1/arm/aesimc.json"},{"mnemonic":"aesmc","slug":"aesmc","records":2,"summary":"AES Mix Columns transformation.","page":"https://instructionsets.com/arm/aesmc/","api":"https://instructionsets.com/api/v1/arm/aesmc.json"},{"mnemonic":"and","slug":"and","records":7,"summary":"Bitwise AND with logical immediate.","page":"https://instructionsets.com/arm/and/","api":"https://instructionsets.com/api/v1/arm/and.json"},{"mnemonic":"and.w","slug":"and_w","records":1,"summary":"Thumb-2 32-bit AND.","page":"https://instructionsets.com/arm/and_w/","api":"https://instructionsets.com/api/v1/arm/and_w.json"},{"mnemonic":"ands","slug":"ands","records":4,"summary":"Bitwise AND immediate, updates flags.","page":"https://instructionsets.com/arm/ands/","api":"https://instructionsets.com/api/v1/arm/ands.json"},{"mnemonic":"andv","slug":"andv","records":1,"summary":"ANDs all active elements into a scalar.","page":"https://instructionsets.com/arm/andv/","api":"https://instructionsets.com/api/v1/arm/andv.json"},{"mnemonic":"asr","slug":"asr","records":6,"summary":"Arithmetic shift right by immediate.","page":"https://instructionsets.com/arm/asr/","api":"https://instructionsets.com/api/v1/arm/asr.json"},{"mnemonic":"at","slug":"at","records":3,"summary":"Performs stage 1 address translation for current EL.","page":"https://instructionsets.com/arm/at/","api":"https://instructionsets.com/api/v1/arm/at.json"},{"mnemonic":"autda","slug":"autda","records":1,"summary":"Authenticates a data address signed with Key A.","page":"https://instructionsets.com/arm/autda/","api":"https://instructionsets.com/api/v1/arm/autda.json"},{"mnemonic":"autdb","slug":"autdb","records":1,"summary":"Authenticates a data address signed with Key B.","page":"https://instructionsets.com/arm/autdb/","api":"https://instructionsets.com/api/v1/arm/autdb.json"},{"mnemonic":"autia","slug":"autia","records":2,"summary":"Authenticates a pointer signed with Key A. Corrupts pointer if failed.","page":"https://instructionsets.com/arm/autia/","api":"https://instructionsets.com/api/v1/arm/autia.json"},{"mnemonic":"autib","slug":"autib","records":2,"summary":"Authenticates a pointer signed with Key B.","page":"https://instructionsets.com/arm/autib/","api":"https://instructionsets.com/api/v1/arm/autib.json"},{"mnemonic":"b","slug":"b","records":2,"summary":"Unconditional branch to label.","page":"https://instructionsets.com/arm/b/","api":"https://instructionsets.com/api/v1/arm/b.json"},{"mnemonic":"b.cond","slug":"b_cond","records":1,"summary":"Branch if condition is met (e.g., B.EQ, B.NE).","page":"https://instructionsets.com/arm/b_cond/","api":"https://instructionsets.com/api/v1/arm/b_cond.json"},{"mnemonic":"b.w","slug":"b_w","records":1,"summary":"Thumb-2 32-bit Unconditional Branch (large range).","page":"https://instructionsets.com/arm/b_w/","api":"https://instructionsets.com/api/v1/arm/b_w.json"},{"mnemonic":"bc.cond","slug":"bc_cond","records":1,"summary":"Branch if condition is met, with stronger ordering guarantees.","page":"https://instructionsets.com/arm/bc_cond/","api":"https://instructionsets.com/api/v1/arm/bc_cond.json"},{"mnemonic":"bfadd","slug":"bfadd","records":1,"summary":"Adds BFloat16 elements.","page":"https://instructionsets.com/arm/bfadd/","api":"https://instructionsets.com/api/v1/arm/bfadd.json"},{"mnemonic":"bfc","slug":"bfc","records":2,"summary":"Clears a bitfield in a register.","page":"https://instructionsets.com/arm/bfc/","api":"https://instructionsets.com/api/v1/arm/bfc.json"},{"mnemonic":"bfcvtn","slug":"bfcvtn","records":1,"summary":"Converts Float32 to BFloat16 (Lower Half).","page":"https://instructionsets.com/arm/bfcvtn/","api":"https://instructionsets.com/api/v1/arm/bfcvtn.json"},{"mnemonic":"bfcvtn2","slug":"bfcvtn2","records":1,"summary":"Converts Float32 to BFloat16 (Upper Half).","page":"https://instructionsets.com/arm/bfcvtn2/","api":"https://instructionsets.com/api/v1/arm/bfcvtn2.json"},{"mnemonic":"bfdot","slug":"bfdot","records":1,"summary":"Computes dot product of BFloat16 elements, accumulating to Float32 (NEON).","page":"https://instructionsets.com/arm/bfdot/","api":"https://instructionsets.com/api/v1/arm/bfdot.json"},{"mnemonic":"bfi","slug":"bfi","records":2,"summary":"Inserts a bitfield into a register.","page":"https://instructionsets.com/arm/bfi/","api":"https://instructionsets.com/api/v1/arm/bfi.json"},{"mnemonic":"bfm","slug":"bfm","records":2,"summary":"Moves a bitfield from source to destination.","page":"https://instructionsets.com/arm/bfm/","api":"https://instructionsets.com/api/v1/arm/bfm.json"},{"mnemonic":"bfmax","slug":"bfmax","records":1,"summary":"Calculates maximum of BFloat16 elements.","page":"https://instructionsets.com/arm/bfmax/","api":"https://instructionsets.com/api/v1/arm/bfmax.json"},{"mnemonic":"bfmin","slug":"bfmin","records":1,"summary":"Calculates minimum of BFloat16 elements.","page":"https://instructionsets.com/arm/bfmin/","api":"https://instructionsets.com/api/v1/arm/bfmin.json"},{"mnemonic":"bfmmla","slug":"bfmmla","records":1,"summary":"Performs 2x2 matrix multiplication on BFloat16 tiles (NEON).","page":"https://instructionsets.com/arm/bfmmla/","api":"https://instructionsets.com/api/v1/arm/bfmmla.json"},{"mnemonic":"bfmul","slug":"bfmul","records":1,"summary":"Multiplies BFloat16 elements.","page":"https://instructionsets.com/arm/bfmul/","api":"https://instructionsets.com/api/v1/arm/bfmul.json"},{"mnemonic":"bfsub","slug":"bfsub","records":1,"summary":"Subtracts BFloat16 elements.","page":"https://instructionsets.com/arm/bfsub/","api":"https://instructionsets.com/api/v1/arm/bfsub.json"},{"mnemonic":"bic","slug":"bic","records":5,"summary":"ANDs register with NOT of shifted register (AND NOT).","page":"https://instructionsets.com/arm/bic/","api":"https://instructionsets.com/api/v1/arm/bic.json"},{"mnemonic":"bic.w","slug":"bic_w","records":1,"summary":"Thumb-2 32-bit AND NOT.","page":"https://instructionsets.com/arm/bic_w/","api":"https://instructionsets.com/api/v1/arm/bic_w.json"},{"mnemonic":"bics","slug":"bics","records":2,"summary":"Performs BIC and updates flags.","page":"https://instructionsets.com/arm/bics/","api":"https://instructionsets.com/api/v1/arm/bics.json"},{"mnemonic":"bif","slug":"bif","records":1,"summary":"Inserts bits from Vn into Vd where Vm (mask) is 0.","page":"https://instructionsets.com/arm/bif/","api":"https://instructionsets.com/api/v1/arm/bif.json"},{"mnemonic":"bit","slug":"bit","records":1,"summary":"Inserts bits from Vn into Vd where Vm (mask) is 1.","page":"https://instructionsets.com/arm/bit/","api":"https://instructionsets.com/api/v1/arm/bit.json"},{"mnemonic":"bkpt","slug":"bkpt","records":2,"summary":"Software Breakpoint (Thumb encoding).","page":"https://instructionsets.com/arm/bkpt/","api":"https://instructionsets.com/api/v1/arm/bkpt.json"},{"mnemonic":"bl","slug":"bl","records":2,"summary":"Function call. Branches to label and stores return address in LR (X30).","page":"https://instructionsets.com/arm/bl/","api":"https://instructionsets.com/api/v1/arm/bl.json"},{"mnemonic":"bl.w","slug":"bl_w","records":1,"summary":"Thumb-2 32-bit Branch with Link.","page":"https://instructionsets.com/arm/bl_w/","api":"https://instructionsets.com/api/v1/arm/bl_w.json"},{"mnemonic":"blr","slug":"blr","records":1,"summary":"Indirect function call. Branches to address in Xn and stores return in LR.","page":"https://instructionsets.com/arm/blr/","api":"https://instructionsets.com/api/v1/arm/blr.json"},{"mnemonic":"blx","slug":"blx","records":1,"summary":"Calls subroutine and optionally switches to Thumb state.","page":"https://instructionsets.com/arm/blx/","api":"https://instructionsets.com/api/v1/arm/blx.json"},{"mnemonic":"br","slug":"br","records":1,"summary":"Indirect branch to address in Xn.","page":"https://instructionsets.com/arm/br/","api":"https://instructionsets.com/api/v1/arm/br.json"},{"mnemonic":"brb","slug":"brb","records":1,"summary":"Injects an entry into the Branch Record Buffer (Debug).","page":"https://instructionsets.com/arm/brb/","api":"https://instructionsets.com/api/v1/arm/brb.json"},{"mnemonic":"brk","slug":"brk","records":1,"summary":"Generates a Breakpoint instruction exception.","page":"https://instructionsets.com/arm/brk/","api":"https://instructionsets.com/api/v1/arm/brk.json"},{"mnemonic":"brka","slug":"brka","records":1,"summary":"Sets predicates up to and including the first active element.","page":"https://instructionsets.com/arm/brka/","api":"https://instructionsets.com/api/v1/arm/brka.json"},{"mnemonic":"brkb","slug":"brkb","records":1,"summary":"Sets predicates up to (but excluding) the first active element.","page":"https://instructionsets.com/arm/brkb/","api":"https://instructionsets.com/api/v1/arm/brkb.json"},{"mnemonic":"bsl","slug":"bsl","records":1,"summary":"Selects bits from Vn or Vm based on Vd (mask). (Vd = (Vd & Vn) | (~Vd & Vm)).","page":"https://instructionsets.com/arm/bsl/","api":"https://instructionsets.com/api/v1/arm/bsl.json"},{"mnemonic":"bti","slug":"bti","records":2,"summary":"Marks a valid target for indirect branches (Guard against JOP/ROP).","page":"https://instructionsets.com/arm/bti/","api":"https://instructionsets.com/api/v1/arm/bti.json"},{"mnemonic":"bx","slug":"bx","records":1,"summary":"Branches to address in register, optionally switching ISA.","page":"https://instructionsets.com/arm/bx/","api":"https://instructionsets.com/api/v1/arm/bx.json"},{"mnemonic":"bxj","slug":"bxj","records":1,"summary":"Legacy instruction to enter Jazelle state (Now behaves like BX).","page":"https://instructionsets.com/arm/bxj/","api":"https://instructionsets.com/api/v1/arm/bxj.json"},{"mnemonic":"cas","slug":"cas","records":2,"summary":"Atomic Compare and Swap (32-bit).","page":"https://instructionsets.com/arm/cas/","api":"https://instructionsets.com/api/v1/arm/cas.json"},{"mnemonic":"casa","slug":"casa","records":1,"summary":"Atomic CAS with Acquire semantics.","page":"https://instructionsets.com/arm/casa/","api":"https://instructionsets.com/api/v1/arm/casa.json"},{"mnemonic":"casal","slug":"casal","records":1,"summary":"Atomic CAS with Acquire and Release semantics.","page":"https://instructionsets.com/arm/casal/","api":"https://instructionsets.com/api/v1/arm/casal.json"},{"mnemonic":"casl","slug":"casl","records":1,"summary":"Atomic CAS with Release semantics.","page":"https://instructionsets.com/arm/casl/","api":"https://instructionsets.com/api/v1/arm/casl.json"},{"mnemonic":"casp","slug":"casp","records":1,"summary":"Atomic CAS of a pair of registers (128-bit or 64-bit pair).","page":"https://instructionsets.com/arm/casp/","api":"https://instructionsets.com/api/v1/arm/casp.json"},{"mnemonic":"cbnz","slug":"cbnz","records":3,"summary":"Branches if register is not zero.","page":"https://instructionsets.com/arm/cbnz/","api":"https://instructionsets.com/api/v1/arm/cbnz.json"},{"mnemonic":"cbz","slug":"cbz","records":3,"summary":"Branches if register is zero.","page":"https://instructionsets.com/arm/cbz/","api":"https://instructionsets.com/api/v1/arm/cbz.json"},{"mnemonic":"ccmn","slug":"ccmn","records":3,"summary":"Compares register with negative immediate if condition is true.","page":"https://instructionsets.com/arm/ccmn/","api":"https://instructionsets.com/api/v1/arm/ccmn.json"},{"mnemonic":"ccmp","slug":"ccmp","records":2,"summary":"Compares register with immediate if condition is true.","page":"https://instructionsets.com/arm/ccmp/","api":"https://instructionsets.com/api/v1/arm/ccmp.json"},{"mnemonic":"cdp","slug":"cdp","records":1,"summary":"Initiates a coprocessor data processing operation.","page":"https://instructionsets.com/arm/cdp/","api":"https://instructionsets.com/api/v1/arm/cdp.json"},{"mnemonic":"cdp2","slug":"cdp2","records":1,"summary":"Initiates a coprocessor operation (Extension encoding).","page":"https://instructionsets.com/arm/cdp2/","api":"https://instructionsets.com/api/v1/arm/cdp2.json"},{"mnemonic":"cfinv","slug":"cfinv","records":1,"summary":"Inverts the C (Carry) flag.","page":"https://instructionsets.com/arm/cfinv/","api":"https://instructionsets.com/api/v1/arm/cfinv.json"},{"mnemonic":"chkfeat","slug":"chkfeat","records":1,"summary":"Check feature status (FEAT_CHK).","page":"https://instructionsets.com/arm/chkfeat/","api":"https://instructionsets.com/api/v1/arm/chkfeat.json"},{"mnemonic":"cinc","slug":"cinc","records":1,"summary":"Increment register if condition is true, else copy. (Alias for CSINC)","page":"https://instructionsets.com/arm/cinc/","api":"https://instructionsets.com/api/v1/arm/cinc.json"},{"mnemonic":"cinv","slug":"cinv","records":1,"summary":"Invert register bits if condition is true, else copy. (Alias for CSINV)","page":"https://instructionsets.com/arm/cinv/","api":"https://instructionsets.com/api/v1/arm/cinv.json"},{"mnemonic":"clasta","slug":"clasta","records":1,"summary":"Extracts element after the last active element.","page":"https://instructionsets.com/arm/clasta/","api":"https://instructionsets.com/api/v1/arm/clasta.json"},{"mnemonic":"clastb","slug":"clastb","records":1,"summary":"Extracts the last active element.","page":"https://instructionsets.com/arm/clastb/","api":"https://instructionsets.com/api/v1/arm/clastb.json"},{"mnemonic":"clrex","slug":"clrex","records":3,"summary":"Clears exclusive monitor (Thumb).","page":"https://instructionsets.com/arm/clrex/","api":"https://instructionsets.com/api/v1/arm/clrex.json"},{"mnemonic":"cls","slug":"cls","records":1,"summary":"Counts number of consecutive sign bits.","page":"https://instructionsets.com/arm/cls/","api":"https://instructionsets.com/api/v1/arm/cls.json"},{"mnemonic":"clz","slug":"clz","records":4,"summary":"Counts number of consecutive zeros.","page":"https://instructionsets.com/arm/clz/","api":"https://instructionsets.com/api/v1/arm/clz.json"},{"mnemonic":"cmeq","slug":"cmeq","records":1,"summary":"Compares elements (Vn == Vm) and sets bits to all 1s or 0s.","page":"https://instructionsets.com/arm/cmeq/","api":"https://instructionsets.com/api/v1/arm/cmeq.json"},{"mnemonic":"cmge","slug":"cmge","records":1,"summary":"Compares elements (Vn >= Vm).","page":"https://instructionsets.com/arm/cmge/","api":"https://instructionsets.com/api/v1/arm/cmge.json"},{"mnemonic":"cmgt","slug":"cmgt","records":1,"summary":"Compares elements (Vn > Vm) and sets bits to all 1s or 0s.","page":"https://instructionsets.com/arm/cmgt/","api":"https://instructionsets.com/api/v1/arm/cmgt.json"},{"mnemonic":"cmn","slug":"cmn","records":2,"summary":"Adds register and immediate, updates flags (discard result). (Alias for ADDS)","page":"https://instructionsets.com/arm/cmn/","api":"https://instructionsets.com/api/v1/arm/cmn.json"},{"mnemonic":"cmn.w","slug":"cmn_w","records":1,"summary":"Thumb-2 32-bit Compare Negative (Add and update flags).","page":"https://instructionsets.com/arm/cmn_w/","api":"https://instructionsets.com/api/v1/arm/cmn_w.json"},{"mnemonic":"cmp","slug":"cmp","records":2,"summary":"Subtracts immediate from register, updates flags (discard result). (Alias for SUBS)","page":"https://instructionsets.com/arm/cmp/","api":"https://instructionsets.com/api/v1/arm/cmp.json"},{"mnemonic":"cmp.w","slug":"cmp_w","records":1,"summary":"Thumb-2 32-bit Compare (Subtract and update flags).","page":"https://instructionsets.com/arm/cmp_w/","api":"https://instructionsets.com/api/v1/arm/cmp_w.json"},{"mnemonic":"cmpeq","slug":"cmpeq","records":1,"summary":"Sets predicate bits where elements are equal.","page":"https://instructionsets.com/arm/cmpeq/","api":"https://instructionsets.com/api/v1/arm/cmpeq.json"},{"mnemonic":"cmpgt","slug":"cmpgt","records":1,"summary":"Sets predicate bits where Zn > Zm.","page":"https://instructionsets.com/arm/cmpgt/","api":"https://instructionsets.com/api/v1/arm/cmpgt.json"},{"mnemonic":"cmtst","slug":"cmtst","records":1,"summary":"Tests if any bits match ((Vn & Vm) != 0).","page":"https://instructionsets.com/arm/cmtst/","api":"https://instructionsets.com/api/v1/arm/cmtst.json"},{"mnemonic":"cneg","slug":"cneg","records":1,"summary":"Negate register if condition is true, else copy. (Alias for CSNEG)","page":"https://instructionsets.com/arm/cneg/","api":"https://instructionsets.com/api/v1/arm/cneg.json"},{"mnemonic":"cnt","slug":"cnt","records":1,"summary":"Counts set bits (population count) per byte.","page":"https://instructionsets.com/arm/cnt/","api":"https://instructionsets.com/api/v1/arm/cnt.json"},{"mnemonic":"cntp","slug":"cntp","records":1,"summary":"Counts the number of true elements in a predicate.","page":"https://instructionsets.com/arm/cntp/","api":"https://instructionsets.com/api/v1/arm/cntp.json"},{"mnemonic":"compact","slug":"compact","records":1,"summary":"Packs active elements to the bottom of the vector.","page":"https://instructionsets.com/arm/compact/","api":"https://instructionsets.com/api/v1/arm/compact.json"},{"mnemonic":"cosp","slug":"cosp","records":1,"summary":"Prevents speculation from determining that the instruction is executed.","page":"https://instructionsets.com/arm/cosp/","api":"https://instructionsets.com/api/v1/arm/cosp.json"},{"mnemonic":"cpp","slug":"cpp","records":1,"summary":"Prevents cache prefetch prediction past this instruction.","page":"https://instructionsets.com/arm/cpp/","api":"https://instructionsets.com/api/v1/arm/cpp.json"},{"mnemonic":"cps","slug":"cps","records":2,"summary":"Changes the processor mode or interrupt masks.","page":"https://instructionsets.com/arm/cps/","api":"https://instructionsets.com/api/v1/arm/cps.json"},{"mnemonic":"cpy","slug":"cpy","records":2,"summary":"Copies scalar value to active vector elements (Alias for DUP predicated).","page":"https://instructionsets.com/arm/cpy/","api":"https://instructionsets.com/api/v1/arm/cpy.json"},{"mnemonic":"crc32b","slug":"crc32b","records":2,"summary":"CRC32 checksum update (Byte).","page":"https://instructionsets.com/arm/crc32b/","api":"https://instructionsets.com/api/v1/arm/crc32b.json"},{"mnemonic":"crc32cb","slug":"crc32cb","records":1,"summary":"Updates CRC32C (Castagnoli) checksum with a byte.","page":"https://instructionsets.com/arm/crc32cb/","api":"https://instructionsets.com/api/v1/arm/crc32cb.json"},{"mnemonic":"crc32w","slug":"crc32w","records":2,"summary":"CRC32 checksum update (Word).","page":"https://instructionsets.com/arm/crc32w/","api":"https://instructionsets.com/api/v1/arm/crc32w.json"},{"mnemonic":"crc32x","slug":"crc32x","records":1,"summary":"Updates CRC32 checksum with a doubleword (64-bit).","page":"https://instructionsets.com/arm/crc32x/","api":"https://instructionsets.com/api/v1/arm/crc32x.json"},{"mnemonic":"csdb","slug":"csdb","records":2,"summary":"Prevents speculative data consumption (v8.0).","page":"https://instructionsets.com/arm/csdb/","api":"https://instructionsets.com/api/v1/arm/csdb.json"},{"mnemonic":"csel","slug":"csel","records":1,"summary":"Selects between two registers based on condition.","page":"https://instructionsets.com/arm/csel/","api":"https://instructionsets.com/api/v1/arm/csel.json"},{"mnemonic":"cset","slug":"cset","records":1,"summary":"Sets register to 1 if condition true, else 0. (Alias for CSINC)","page":"https://instructionsets.com/arm/cset/","api":"https://instructionsets.com/api/v1/arm/cset.json"},{"mnemonic":"csinc","slug":"csinc","records":1,"summary":"Selects Wn if cond true, else (Wm + 1).","page":"https://instructionsets.com/arm/csinc/","api":"https://instructionsets.com/api/v1/arm/csinc.json"},{"mnemonic":"csinv","slug":"csinv","records":1,"summary":"Selects Wn if cond true, else NOT Wm.","page":"https://instructionsets.com/arm/csinv/","api":"https://instructionsets.com/api/v1/arm/csinv.json"},{"mnemonic":"csneg","slug":"csneg","records":1,"summary":"Selects Wn if cond true, else -Wm.","page":"https://instructionsets.com/arm/csneg/","api":"https://instructionsets.com/api/v1/arm/csneg.json"},{"mnemonic":"dbg","slug":"dbg","records":2,"summary":"Provides a hint to the debug system.","page":"https://instructionsets.com/arm/dbg/","api":"https://instructionsets.com/api/v1/arm/dbg.json"},{"mnemonic":"dc","slug":"dc","records":1,"summary":"Performs data cache maintenance (Clean, Invalidate, Flush).","page":"https://instructionsets.com/arm/dc/","api":"https://instructionsets.com/api/v1/arm/dc.json"},{"mnemonic":"dcps1","slug":"dcps1","records":2,"summary":"Switches execution to EL1 (Debug).","page":"https://instructionsets.com/arm/dcps1/","api":"https://instructionsets.com/api/v1/arm/dcps1.json"},{"mnemonic":"dcps2","slug":"dcps2","records":2,"summary":"Switches execution to EL2 (Debug).","page":"https://instructionsets.com/arm/dcps2/","api":"https://instructionsets.com/api/v1/arm/dcps2.json"},{"mnemonic":"dcps3","slug":"dcps3","records":2,"summary":"Switches execution to EL3 (Debug).","page":"https://instructionsets.com/arm/dcps3/","api":"https://instructionsets.com/api/v1/arm/dcps3.json"},{"mnemonic":"decb","slug":"decb","records":1,"summary":"Decrements a register by the number of active bytes.","page":"https://instructionsets.com/arm/decb/","api":"https://instructionsets.com/api/v1/arm/decb.json"},{"mnemonic":"decd","slug":"decd","records":1,"summary":"Decrements a register by the number of active doublewords.","page":"https://instructionsets.com/arm/decd/","api":"https://instructionsets.com/api/v1/arm/decd.json"},{"mnemonic":"decw","slug":"decw","records":1,"summary":"Decrements a register by the number of active words.","page":"https://instructionsets.com/arm/decw/","api":"https://instructionsets.com/api/v1/arm/decw.json"},{"mnemonic":"dfb","slug":"dfb","records":1,"summary":"Deprecated alias for DSB.","page":"https://instructionsets.com/arm/dfb/","api":"https://instructionsets.com/api/v1/arm/dfb.json"},{"mnemonic":"dgh","slug":"dgh","records":1,"summary":"Hints that multiple memory accesses should be merged.","page":"https://instructionsets.com/arm/dgh/","api":"https://instructionsets.com/api/v1/arm/dgh.json"},{"mnemonic":"dmb","slug":"dmb","records":3,"summary":"Ensures memory access ordering.","page":"https://instructionsets.com/arm/dmb/","api":"https://instructionsets.com/api/v1/arm/dmb.json"},{"mnemonic":"drps","slug":"drps","records":1,"summary":"Restores state from SPSR_ELx and DLR_EL0.","page":"https://instructionsets.com/arm/drps/","api":"https://instructionsets.com/api/v1/arm/drps.json"},{"mnemonic":"dsb","slug":"dsb","records":3,"summary":"Ensures completion of memory accesses.","page":"https://instructionsets.com/arm/dsb/","api":"https://instructionsets.com/api/v1/arm/dsb.json"},{"mnemonic":"dup","slug":"dup","records":3,"summary":"Duplicates a general-purpose register to all vector elements.","page":"https://instructionsets.com/arm/dup/","api":"https://instructionsets.com/api/v1/arm/dup.json"},{"mnemonic":"eon","slug":"eon","records":2,"summary":"XORs register with NOT of shifted register (XNOR).","page":"https://instructionsets.com/arm/eon/","api":"https://instructionsets.com/api/v1/arm/eon.json"},{"mnemonic":"eor","slug":"eor","records":5,"summary":"XORs register with immediate.","page":"https://instructionsets.com/arm/eor/","api":"https://instructionsets.com/api/v1/arm/eor.json"},{"mnemonic":"eor.w","slug":"eor_w","records":1,"summary":"Thumb-2 32-bit XOR.","page":"https://instructionsets.com/arm/eor_w/","api":"https://instructionsets.com/api/v1/arm/eor_w.json"},{"mnemonic":"eorv","slug":"eorv","records":1,"summary":"XORs all active elements into a scalar.","page":"https://instructionsets.com/arm/eorv/","api":"https://instructionsets.com/api/v1/arm/eorv.json"},{"mnemonic":"eret","slug":"eret","records":3,"summary":"Returns from an exception.","page":"https://instructionsets.com/arm/eret/","api":"https://instructionsets.com/api/v1/arm/eret.json"},{"mnemonic":"esb","slug":"esb","records":2,"summary":"Synchronizes system errors (v8.2).","page":"https://instructionsets.com/arm/esb/","api":"https://instructionsets.com/api/v1/arm/esb.json"},{"mnemonic":"ext","slug":"ext","records":2,"summary":"Extracts a vector from a pair (sliding window) using immediate byte index.","page":"https://instructionsets.com/arm/ext/","api":"https://instructionsets.com/api/v1/arm/ext.json"},{"mnemonic":"extr","slug":"extr","records":2,"summary":"Extracts a register from a pair of registers.","page":"https://instructionsets.com/arm/extr/","api":"https://instructionsets.com/api/v1/arm/extr.json"},{"mnemonic":"fabs","slug":"fabs","records":4,"summary":"Calculates absolute value of floats.","page":"https://instructionsets.com/arm/fabs/","api":"https://instructionsets.com/api/v1/arm/fabs.json"},{"mnemonic":"fadd","slug":"fadd","records":6,"summary":"Adds two floating-point values.","page":"https://instructionsets.com/arm/fadd/","api":"https://instructionsets.com/api/v1/arm/fadd.json"},{"mnemonic":"faddp","slug":"faddp","records":1,"summary":"Adds adjacent pairs of float elements.","page":"https://instructionsets.com/arm/faddp/","api":"https://instructionsets.com/api/v1/arm/faddp.json"},{"mnemonic":"faddv","slug":"faddv","records":1,"summary":"Sums all active floating-point elements into a scalar result.","page":"https://instructionsets.com/arm/faddv/","api":"https://instructionsets.com/api/v1/arm/faddv.json"},{"mnemonic":"fcadd","slug":"fcadd","records":2,"summary":"Performs complex addition with rotation.","page":"https://instructionsets.com/arm/fcadd/","api":"https://instructionsets.com/api/v1/arm/fcadd.json"},{"mnemonic":"fccmp","slug":"fccmp","records":1,"summary":"Compares floats only if condition is met, else sets flags to immediate.","page":"https://instructionsets.com/arm/fccmp/","api":"https://instructionsets.com/api/v1/arm/fccmp.json"},{"mnemonic":"fcmeq","slug":"fcmeq","records":1,"summary":"Sets predicate bits where float elements are equal.","page":"https://instructionsets.com/arm/fcmeq/","api":"https://instructionsets.com/api/v1/arm/fcmeq.json"},{"mnemonic":"fcmgt","slug":"fcmgt","records":1,"summary":"Sets predicate bits where float Zn > Zm.","page":"https://instructionsets.com/arm/fcmgt/","api":"https://instructionsets.com/api/v1/arm/fcmgt.json"},{"mnemonic":"fcmla","slug":"fcmla","records":2,"summary":"Performs complex multiply-accumulate.","page":"https://instructionsets.com/arm/fcmla/","api":"https://instructionsets.com/api/v1/arm/fcmla.json"},{"mnemonic":"fcmp","slug":"fcmp","records":3,"summary":"Compares two floating-point values and updates process flags (NZCV).","page":"https://instructionsets.com/arm/fcmp/","api":"https://instructionsets.com/api/v1/arm/fcmp.json"},{"mnemonic":"fcsel","slug":"fcsel","records":1,"summary":"Selects one of two floats based on condition flags.","page":"https://instructionsets.com/arm/fcsel/","api":"https://instructionsets.com/api/v1/arm/fcsel.json"},{"mnemonic":"fcvt","slug":"fcvt","records":1,"summary":"Converts between float precisions (e.g., Half <-> Single <-> Double).","page":"https://instructionsets.com/arm/fcvt/","api":"https://instructionsets.com/api/v1/arm/fcvt.json"},{"mnemonic":"fcvtas","slug":"fcvtas","records":1,"summary":"Converts float to signed integer, rounding to nearest.","page":"https://instructionsets.com/arm/fcvtas/","api":"https://instructionsets.com/api/v1/arm/fcvtas.json"},{"mnemonic":"fcvtau","slug":"fcvtau","records":1,"summary":"Converts float to unsigned integer, rounding to nearest.","page":"https://instructionsets.com/arm/fcvtau/","api":"https://instructionsets.com/api/v1/arm/fcvtau.json"},{"mnemonic":"fcvtl","slug":"fcvtl","records":2,"summary":"Converts Half-precision (Bottom) to Single-precision.","page":"https://instructionsets.com/arm/fcvtl/","api":"https://instructionsets.com/api/v1/arm/fcvtl.json"},{"mnemonic":"fcvtl2","slug":"fcvtl2","records":1,"summary":"Converts Half-precision (Top) to Single-precision.","page":"https://instructionsets.com/arm/fcvtl2/","api":"https://instructionsets.com/api/v1/arm/fcvtl2.json"},{"mnemonic":"fcvtms","slug":"fcvtms","records":1,"summary":"Converts float to signed integer, rounding towards minus infinity (Floor).","page":"https://instructionsets.com/arm/fcvtms/","api":"https://instructionsets.com/api/v1/arm/fcvtms.json"},{"mnemonic":"fcvtmu","slug":"fcvtmu","records":1,"summary":"Converts float to unsigned integer, rounding towards minus infinity.","page":"https://instructionsets.com/arm/fcvtmu/","api":"https://instructionsets.com/api/v1/arm/fcvtmu.json"},{"mnemonic":"fcvtn","slug":"fcvtn","records":2,"summary":"Converts Single-precision to Half-precision (Bottom).","page":"https://instructionsets.com/arm/fcvtn/","api":"https://instructionsets.com/api/v1/arm/fcvtn.json"},{"mnemonic":"fcvtn2","slug":"fcvtn2","records":1,"summary":"Converts Single-precision to Half-precision (Top).","page":"https://instructionsets.com/arm/fcvtn2/","api":"https://instructionsets.com/api/v1/arm/fcvtn2.json"},{"mnemonic":"fcvtns","slug":"fcvtns","records":1,"summary":"Converts float to signed integer, rounding to nearest (bankers' round).","page":"https://instructionsets.com/arm/fcvtns/","api":"https://instructionsets.com/api/v1/arm/fcvtns.json"},{"mnemonic":"fcvtnu","slug":"fcvtnu","records":1,"summary":"Converts float to unsigned integer, rounding to nearest (bankers' round).","page":"https://instructionsets.com/arm/fcvtnu/","api":"https://instructionsets.com/api/v1/arm/fcvtnu.json"},{"mnemonic":"fcvtps","slug":"fcvtps","records":1,"summary":"Converts float to signed integer, rounding towards plus infinity (Ceil).","page":"https://instructionsets.com/arm/fcvtps/","api":"https://instructionsets.com/api/v1/arm/fcvtps.json"},{"mnemonic":"fcvtpu","slug":"fcvtpu","records":1,"summary":"Converts float to unsigned integer, rounding towards plus infinity.","page":"https://instructionsets.com/arm/fcvtpu/","api":"https://instructionsets.com/api/v1/arm/fcvtpu.json"},{"mnemonic":"fcvtzs","slug":"fcvtzs","records":4,"summary":"Converts floats to signed integers (Truncate).","page":"https://instructionsets.com/arm/fcvtzs/","api":"https://instructionsets.com/api/v1/arm/fcvtzs.json"},{"mnemonic":"fcvtzu","slug":"fcvtzu","records":3,"summary":"Converts floats to unsigned integers (Truncate).","page":"https://instructionsets.com/arm/fcvtzu/","api":"https://instructionsets.com/api/v1/arm/fcvtzu.json"},{"mnemonic":"fdiv","slug":"fdiv","records":6,"summary":"Divides two floating-point values.","page":"https://instructionsets.com/arm/fdiv/","api":"https://instructionsets.com/api/v1/arm/fdiv.json"},{"mnemonic":"fjcvtzs","slug":"fjcvtzs","records":1,"summary":"Converts double to signed 32-bit integer with JS rounding semantics.","page":"https://instructionsets.com/arm/fjcvtzs/","api":"https://instructionsets.com/api/v1/arm/fjcvtzs.json"},{"mnemonic":"fmadd","slug":"fmadd","records":1,"summary":"Calculates (Vn * Vm) + Va without intermediate rounding.","page":"https://instructionsets.com/arm/fmadd/","api":"https://instructionsets.com/api/v1/arm/fmadd.json"},{"mnemonic":"fmax","slug":"fmax","records":4,"summary":"Returns the larger of two values.","page":"https://instructionsets.com/arm/fmax/","api":"https://instructionsets.com/api/v1/arm/fmax.json"},{"mnemonic":"fmaxnm","slug":"fmaxnm","records":1,"summary":"Returns larger value, handling NaNs according to IEEE 754-2008 'maxNum'.","page":"https://instructionsets.com/arm/fmaxnm/","api":"https://instructionsets.com/api/v1/arm/fmaxnm.json"},{"mnemonic":"fmaxp","slug":"fmaxp","records":1,"summary":"Max of adjacent float elements.","page":"https://instructionsets.com/arm/fmaxp/","api":"https://instructionsets.com/api/v1/arm/fmaxp.json"},{"mnemonic":"fmaxv","slug":"fmaxv","records":2,"summary":"Finds max float in vector.","page":"https://instructionsets.com/arm/fmaxv/","api":"https://instructionsets.com/api/v1/arm/fmaxv.json"},{"mnemonic":"fmin","slug":"fmin","records":4,"summary":"Returns the smaller of two values.","page":"https://instructionsets.com/arm/fmin/","api":"https://instructionsets.com/api/v1/arm/fmin.json"},{"mnemonic":"fminnm","slug":"fminnm","records":1,"summary":"Returns smaller value, handling NaNs according to IEEE 754-2008 'minNum'.","page":"https://instructionsets.com/arm/fminnm/","api":"https://instructionsets.com/api/v1/arm/fminnm.json"},{"mnemonic":"fminp","slug":"fminp","records":1,"summary":"Min of adjacent float elements.","page":"https://instructionsets.com/arm/fminp/","api":"https://instructionsets.com/api/v1/arm/fminp.json"},{"mnemonic":"fminv","slug":"fminv","records":2,"summary":"Finds min float in vector.","page":"https://instructionsets.com/arm/fminv/","api":"https://instructionsets.com/api/v1/arm/fminv.json"},{"mnemonic":"fmla","slug":"fmla","records":3,"summary":"Multiplies and adds to destination (Vd = Vd + Vn * Vm).","page":"https://instructionsets.com/arm/fmla/","api":"https://instructionsets.com/api/v1/arm/fmla.json"},{"mnemonic":"fmls","slug":"fmls","records":3,"summary":"Multiplies and subtracts from destination (Vd = Vd - Vn * Vm).","page":"https://instructionsets.com/arm/fmls/","api":"https://instructionsets.com/api/v1/arm/fmls.json"},{"mnemonic":"fmov","slug":"fmov","records":6,"summary":"Moves a floating-point immediate into a scalar register.","page":"https://instructionsets.com/arm/fmov/","api":"https://instructionsets.com/api/v1/arm/fmov.json"},{"mnemonic":"fmsub","slug":"fmsub","records":1,"summary":"Calculates (Vn * Vm) - Va.","page":"https://instructionsets.com/arm/fmsub/","api":"https://instructionsets.com/api/v1/arm/fmsub.json"},{"mnemonic":"fmul","slug":"fmul","records":6,"summary":"Multiplies two floating-point values.","page":"https://instructionsets.com/arm/fmul/","api":"https://instructionsets.com/api/v1/arm/fmul.json"},{"mnemonic":"fneg","slug":"fneg","records":4,"summary":"Negates floats.","page":"https://instructionsets.com/arm/fneg/","api":"https://instructionsets.com/api/v1/arm/fneg.json"},{"mnemonic":"fnmadd","slug":"fnmadd","records":1,"summary":"Calculates -((Vn * Vm) + Va).","page":"https://instructionsets.com/arm/fnmadd/","api":"https://instructionsets.com/api/v1/arm/fnmadd.json"},{"mnemonic":"fnmsub","slug":"fnmsub","records":1,"summary":"Calculates -((Vn * Vm) - Va).","page":"https://instructionsets.com/arm/fnmsub/","api":"https://instructionsets.com/api/v1/arm/fnmsub.json"},{"mnemonic":"fnmul","slug":"fnmul","records":1,"summary":"Calculates -(Vn * Vm).","page":"https://instructionsets.com/arm/fnmul/","api":"https://instructionsets.com/api/v1/arm/fnmul.json"},{"mnemonic":"frecpe","slug":"frecpe","records":1,"summary":"Estimates reciprocal (1/x) for floats.","page":"https://instructionsets.com/arm/frecpe/","api":"https://instructionsets.com/api/v1/arm/frecpe.json"},{"mnemonic":"frecps","slug":"frecps","records":1,"summary":"Newton-Raphson step for reciprocal refinement.","page":"https://instructionsets.com/arm/frecps/","api":"https://instructionsets.com/api/v1/arm/frecps.json"},{"mnemonic":"frint32x","slug":"frint32x","records":1,"summary":"Rounds to 32-bit integer, exact exception.","page":"https://instructionsets.com/arm/frint32x/","api":"https://instructionsets.com/api/v1/arm/frint32x.json"},{"mnemonic":"frint32z","slug":"frint32z","records":1,"summary":"Rounds to 32-bit integer towards zero.","page":"https://instructionsets.com/arm/frint32z/","api":"https://instructionsets.com/api/v1/arm/frint32z.json"},{"mnemonic":"frint64x","slug":"frint64x","records":1,"summary":"Rounds to 64-bit integer, exact exception.","page":"https://instructionsets.com/arm/frint64x/","api":"https://instructionsets.com/api/v1/arm/frint64x.json"},{"mnemonic":"frint64z","slug":"frint64z","records":1,"summary":"Rounds to 64-bit integer towards zero.","page":"https://instructionsets.com/arm/frint64z/","api":"https://instructionsets.com/api/v1/arm/frint64z.json"},{"mnemonic":"frinta","slug":"frinta","records":1,"summary":"Rounds float to nearest integral value (ties away from zero).","page":"https://instructionsets.com/arm/frinta/","api":"https://instructionsets.com/api/v1/arm/frinta.json"},{"mnemonic":"frinti","slug":"frinti","records":1,"summary":"Rounds float to integral value using current FPCR rounding mode.","page":"https://instructionsets.com/arm/frinti/","api":"https://instructionsets.com/api/v1/arm/frinti.json"},{"mnemonic":"frintm","slug":"frintm","records":1,"summary":"Rounds float to integral value towards minus infinity (Floor).","page":"https://instructionsets.com/arm/frintm/","api":"https://instructionsets.com/api/v1/arm/frintm.json"},{"mnemonic":"frintn","slug":"frintn","records":1,"summary":"Rounds float to integral value nearest, ties to even.","page":"https://instructionsets.com/arm/frintn/","api":"https://instructionsets.com/api/v1/arm/frintn.json"},{"mnemonic":"frintp","slug":"frintp","records":1,"summary":"Rounds float to integral value towards plus infinity (Ceil).","page":"https://instructionsets.com/arm/frintp/","api":"https://instructionsets.com/api/v1/arm/frintp.json"},{"mnemonic":"frintx","slug":"frintx","records":1,"summary":"Rounds float to integral value using current mode, raising Inexact exception.","page":"https://instructionsets.com/arm/frintx/","api":"https://instructionsets.com/api/v1/arm/frintx.json"},{"mnemonic":"frintz","slug":"frintz","records":1,"summary":"Rounds float to integral value towards zero (Truncate).","page":"https://instructionsets.com/arm/frintz/","api":"https://instructionsets.com/api/v1/arm/frintz.json"},{"mnemonic":"frsqrte","slug":"frsqrte","records":1,"summary":"Estimates reciprocal square root (1/sqrt(x)).","page":"https://instructionsets.com/arm/frsqrte/","api":"https://instructionsets.com/api/v1/arm/frsqrte.json"},{"mnemonic":"frsqrts","slug":"frsqrts","records":1,"summary":"Newton-Raphson step for reciprocal square root refinement.","page":"https://instructionsets.com/arm/frsqrts/","api":"https://instructionsets.com/api/v1/arm/frsqrts.json"},{"mnemonic":"fsqrt","slug":"fsqrt","records":4,"summary":"Calculates square root of floats.","page":"https://instructionsets.com/arm/fsqrt/","api":"https://instructionsets.com/api/v1/arm/fsqrt.json"},{"mnemonic":"fsub","slug":"fsub","records":6,"summary":"Subtracts two floating-point values.","page":"https://instructionsets.com/arm/fsub/","api":"https://instructionsets.com/api/v1/arm/fsub.json"},{"mnemonic":"gcspopm","slug":"gcspopm","records":1,"summary":"Pops the value from the Guarded Control Stack into LR.","page":"https://instructionsets.com/arm/gcspopm/","api":"https://instructionsets.com/api/v1/arm/gcspopm.json"},{"mnemonic":"gcsss1","slug":"gcsss1","records":1,"summary":"First step to switch the GCS pointer.","page":"https://instructionsets.com/arm/gcsss1/","api":"https://instructionsets.com/api/v1/arm/gcsss1.json"},{"mnemonic":"gcsss2","slug":"gcsss2","records":1,"summary":"Second step to switch the GCS pointer.","page":"https://instructionsets.com/arm/gcsss2/","api":"https://instructionsets.com/api/v1/arm/gcsss2.json"},{"mnemonic":"gmi","slug":"gmi","records":1,"summary":"Calculates a mask of excluded tags (MTE).","page":"https://instructionsets.com/arm/gmi/","api":"https://instructionsets.com/api/v1/arm/gmi.json"},{"mnemonic":"hint","slug":"hint","records":1,"summary":"Provides a hint to the processor (e.g., NOP, YIELD).","page":"https://instructionsets.com/arm/hint/","api":"https://instructionsets.com/api/v1/arm/hint.json"},{"mnemonic":"hlt","slug":"hlt","records":3,"summary":"Enters Halting debug mode.","page":"https://instructionsets.com/arm/hlt/","api":"https://instructionsets.com/api/v1/arm/hlt.json"},{"mnemonic":"hvc","slug":"hvc","records":3,"summary":"Generates a Hypervisor Call exception to EL2.","page":"https://instructionsets.com/arm/hvc/","api":"https://instructionsets.com/api/v1/arm/hvc.json"},{"mnemonic":"ic","slug":"ic","records":1,"summary":"Performs instruction cache maintenance.","page":"https://instructionsets.com/arm/ic/","api":"https://instructionsets.com/api/v1/arm/ic.json"},{"mnemonic":"incb","slug":"incb","records":1,"summary":"Increments a general-purpose register by the number of active bytes in the pattern.","page":"https://instructionsets.com/arm/incb/","api":"https://instructionsets.com/api/v1/arm/incb.json"},{"mnemonic":"incd","slug":"incd","records":1,"summary":"Increments a register by the number of active doublewords.","page":"https://instructionsets.com/arm/incd/","api":"https://instructionsets.com/api/v1/arm/incd.json"},{"mnemonic":"incw","slug":"incw","records":1,"summary":"Increments a register by the number of active words.","page":"https://instructionsets.com/arm/incw/","api":"https://instructionsets.com/api/v1/arm/incw.json"},{"mnemonic":"index","slug":"index","records":1,"summary":"Generates a vector of indices: V[i] = Start + i * Step.","page":"https://instructionsets.com/arm/index/","api":"https://instructionsets.com/api/v1/arm/index.json"},{"mnemonic":"ins","slug":"ins","records":1,"summary":"Moves data from a GPR to a specific vector element.","page":"https://instructionsets.com/arm/ins/","api":"https://instructionsets.com/api/v1/arm/ins.json"},{"mnemonic":"insr","slug":"insr","records":1,"summary":"Inserts scalar into bottom of vector, shifting other elements up.","page":"https://instructionsets.com/arm/insr/","api":"https://instructionsets.com/api/v1/arm/insr.json"},{"mnemonic":"irg","slug":"irg","records":1,"summary":"Inserts a random Allocation Tag into a pointer (MTE).","page":"https://instructionsets.com/arm/irg/","api":"https://instructionsets.com/api/v1/arm/irg.json"},{"mnemonic":"isb","slug":"isb","records":3,"summary":"Flushes the pipeline and prefetches.","page":"https://instructionsets.com/arm/isb/","api":"https://instructionsets.com/api/v1/arm/isb.json"},{"mnemonic":"it","slug":"it","records":1,"summary":"Makes up to 4 following instructions conditional (Thumb-only).","page":"https://instructionsets.com/arm/it/","api":"https://instructionsets.com/api/v1/arm/it.json"},{"mnemonic":"lasta","slug":"lasta","records":1,"summary":"Extracts element after last active (SIMD scalar destination).","page":"https://instructionsets.com/arm/lasta/","api":"https://instructionsets.com/api/v1/arm/lasta.json"},{"mnemonic":"lastb","slug":"lastb","records":1,"summary":"Extracts last active element (SIMD scalar destination).","page":"https://instructionsets.com/arm/lastb/","api":"https://instructionsets.com/api/v1/arm/lastb.json"},{"mnemonic":"ld1","slug":"ld1","records":1,"summary":"Loads one element structure from memory into 1-4 registers.","page":"https://instructionsets.com/arm/ld1/","api":"https://instructionsets.com/api/v1/arm/ld1.json"},{"mnemonic":"ld1b","slug":"ld1b","records":1,"summary":"Loads bytes from memory into a vector under predicate control.","page":"https://instructionsets.com/arm/ld1b/","api":"https://instructionsets.com/api/v1/arm/ld1b.json"},{"mnemonic":"ld1d","slug":"ld1d","records":1,"summary":"Loads doublewords from memory into a vector under predicate control.","page":"https://instructionsets.com/arm/ld1d/","api":"https://instructionsets.com/api/v1/arm/ld1d.json"},{"mnemonic":"ld1h","slug":"ld1h","records":1,"summary":"Loads halfwords from memory into a vector under predicate control.","page":"https://instructionsets.com/arm/ld1h/","api":"https://instructionsets.com/api/v1/arm/ld1h.json"},{"mnemonic":"ld1r","slug":"ld1r","records":1,"summary":"Loads one element and replicates it to all lanes of the vector.","page":"https://instructionsets.com/arm/ld1r/","api":"https://instructionsets.com/api/v1/arm/ld1r.json"},{"mnemonic":"ld1w","slug":"ld1w","records":2,"summary":"Loads words from memory into a vector under predicate control.","page":"https://instructionsets.com/arm/ld1w/","api":"https://instructionsets.com/api/v1/arm/ld1w.json"},{"mnemonic":"ld2","slug":"ld2","records":1,"summary":"Loads two-element structures from memory into two registers (De-interleave).","page":"https://instructionsets.com/arm/ld2/","api":"https://instructionsets.com/api/v1/arm/ld2.json"},{"mnemonic":"ld2r","slug":"ld2r","records":1,"summary":"Loads 2 elements and replicates them to all lanes.","page":"https://instructionsets.com/arm/ld2r/","api":"https://instructionsets.com/api/v1/arm/ld2r.json"},{"mnemonic":"ld3","slug":"ld3","records":1,"summary":"Loads three-element structures (e.g., RGB) into three registers.","page":"https://instructionsets.com/arm/ld3/","api":"https://instructionsets.com/api/v1/arm/ld3.json"},{"mnemonic":"ld4","slug":"ld4","records":1,"summary":"Loads four-element structures (e.g., RGBA) into four registers.","page":"https://instructionsets.com/arm/ld4/","api":"https://instructionsets.com/api/v1/arm/ld4.json"},{"mnemonic":"ld64b","slug":"ld64b","records":1,"summary":"Loads a 64-byte block of data atomically (Accelerator support).","page":"https://instructionsets.com/arm/ld64b/","api":"https://instructionsets.com/api/v1/arm/ld64b.json"},{"mnemonic":"lda","slug":"lda","records":1,"summary":"Loads a word with Acquire semantics.","page":"https://instructionsets.com/arm/lda/","api":"https://instructionsets.com/api/v1/arm/lda.json"},{"mnemonic":"ldadd","slug":"ldadd","records":1,"summary":"Atomic add to memory, return old value.","page":"https://instructionsets.com/arm/ldadd/","api":"https://instructionsets.com/api/v1/arm/ldadd.json"},{"mnemonic":"ldaex","slug":"ldaex","records":1,"summary":"Loads a word with Acquire Exclusive semantics.","page":"https://instructionsets.com/arm/ldaex/","api":"https://instructionsets.com/api/v1/arm/ldaex.json"},{"mnemonic":"ldaexb","slug":"ldaexb","records":1,"summary":"Loads a byte, acquires semantics, marks exclusive.","page":"https://instructionsets.com/arm/ldaexb/","api":"https://instructionsets.com/api/v1/arm/ldaexb.json"},{"mnemonic":"ldaexd","slug":"ldaexd","records":1,"summary":"Loads a doubleword, acquires semantics, marks exclusive.","page":"https://instructionsets.com/arm/ldaexd/","api":"https://instructionsets.com/api/v1/arm/ldaexd.json"},{"mnemonic":"ldaexh","slug":"ldaexh","records":1,"summary":"Loads a halfword, acquires semantics, marks exclusive.","page":"https://instructionsets.com/arm/ldaexh/","api":"https://instructionsets.com/api/v1/arm/ldaexh.json"},{"mnemonic":"ldapr","slug":"ldapr","records":1,"summary":"Loads a word with RCpc Acquire semantics.","page":"https://instructionsets.com/arm/ldapr/","api":"https://instructionsets.com/api/v1/arm/ldapr.json"},{"mnemonic":"ldaprb","slug":"ldaprb","records":1,"summary":"Loads a byte with Release Consistency (process consistent) Acquire semantics.","page":"https://instructionsets.com/arm/ldaprb/","api":"https://instructionsets.com/api/v1/arm/ldaprb.json"},{"mnemonic":"ldaprh","slug":"ldaprh","records":1,"summary":"Loads a halfword with RCpc Acquire semantics.","page":"https://instructionsets.com/arm/ldaprh/","api":"https://instructionsets.com/api/v1/arm/ldaprh.json"},{"mnemonic":"ldar","slug":"ldar","records":1,"summary":"Loads a word with Acquire semantics.","page":"https://instructionsets.com/arm/ldar/","api":"https://instructionsets.com/api/v1/arm/ldar.json"},{"mnemonic":"ldarb","slug":"ldarb","records":1,"summary":"Loads a byte with Acquire semantics.","page":"https://instructionsets.com/arm/ldarb/","api":"https://instructionsets.com/api/v1/arm/ldarb.json"},{"mnemonic":"ldarh","slug":"ldarh","records":1,"summary":"Loads a halfword with Acquire semantics.","page":"https://instructionsets.com/arm/ldarh/","api":"https://instructionsets.com/api/v1/arm/ldarh.json"},{"mnemonic":"ldaxr","slug":"ldaxr","records":1,"summary":"Loads a word with Acquire Exclusive semantics.","page":"https://instructionsets.com/arm/ldaxr/","api":"https://instructionsets.com/api/v1/arm/ldaxr.json"},{"mnemonic":"ldaxrb","slug":"ldaxrb","records":1,"summary":"Loads a byte with Acquire Exclusive semantics.","page":"https://instructionsets.com/arm/ldaxrb/","api":"https://instructionsets.com/api/v1/arm/ldaxrb.json"},{"mnemonic":"ldaxrh","slug":"ldaxrh","records":1,"summary":"Loads a halfword with Acquire Exclusive semantics.","page":"https://instructionsets.com/arm/ldaxrh/","api":"https://instructionsets.com/api/v1/arm/ldaxrh.json"},{"mnemonic":"ldc","slug":"ldc","records":1,"summary":"Loads memory into a coprocessor.","page":"https://instructionsets.com/arm/ldc/","api":"https://instructionsets.com/api/v1/arm/ldc.json"},{"mnemonic":"ldc2","slug":"ldc2","records":1,"summary":"Loads memory into a coprocessor (Extension encoding).","page":"https://instructionsets.com/arm/ldc2/","api":"https://instructionsets.com/api/v1/arm/ldc2.json"},{"mnemonic":"ldclr","slug":"ldclr","records":1,"summary":"Atomic bit clear (AND NOT) to memory.","page":"https://instructionsets.com/arm/ldclr/","api":"https://instructionsets.com/api/v1/arm/ldclr.json"},{"mnemonic":"ldeor","slug":"ldeor","records":1,"summary":"Atomic XOR to memory.","page":"https://instructionsets.com/arm/ldeor/","api":"https://instructionsets.com/api/v1/arm/ldeor.json"},{"mnemonic":"ldff1b","slug":"ldff1b","records":1,"summary":"Loads bytes speculatively; suppresses faults after the first active element.","page":"https://instructionsets.com/arm/ldff1b/","api":"https://instructionsets.com/api/v1/arm/ldff1b.json"},{"mnemonic":"ldff1d","slug":"ldff1d","records":1,"summary":"Loads doublewords speculatively; suppresses faults after the first active element.","page":"https://instructionsets.com/arm/ldff1d/","api":"https://instructionsets.com/api/v1/arm/ldff1d.json"},{"mnemonic":"ldff1h","slug":"ldff1h","records":1,"summary":"Loads halfwords speculatively; suppresses faults after the first active element.","page":"https://instructionsets.com/arm/ldff1h/","api":"https://instructionsets.com/api/v1/arm/ldff1h.json"},{"mnemonic":"ldff1w","slug":"ldff1w","records":1,"summary":"Loads words speculatively; suppresses faults after the first active element.","page":"https://instructionsets.com/arm/ldff1w/","api":"https://instructionsets.com/api/v1/arm/ldff1w.json"},{"mnemonic":"ldg","slug":"ldg","records":1,"summary":"Loads the Allocation Tag from memory.","page":"https://instructionsets.com/arm/ldg/","api":"https://instructionsets.com/api/v1/arm/ldg.json"},{"mnemonic":"ldm","slug":"ldm","records":2,"summary":"Load multiple registers (Thumb 16-bit).","page":"https://instructionsets.com/arm/ldm/","api":"https://instructionsets.com/api/v1/arm/ldm.json"},{"mnemonic":"ldm.w","slug":"ldm_w","records":1,"summary":"Thumb-2 32-bit Load Multiple.","page":"https://instructionsets.com/arm/ldm_w/","api":"https://instructionsets.com/api/v1/arm/ldm_w.json"},{"mnemonic":"ldnf1b","slug":"ldnf1b","records":1,"summary":"Loads bytes without faulting; returns 0 if fault occurs.","page":"https://instructionsets.com/arm/ldnf1b/","api":"https://instructionsets.com/api/v1/arm/ldnf1b.json"},{"mnemonic":"ldnf1d","slug":"ldnf1d","records":1,"summary":"Loads doublewords without faulting.","page":"https://instructionsets.com/arm/ldnf1d/","api":"https://instructionsets.com/api/v1/arm/ldnf1d.json"},{"mnemonic":"ldnf1h","slug":"ldnf1h","records":1,"summary":"Loads halfwords without faulting.","page":"https://instructionsets.com/arm/ldnf1h/","api":"https://instructionsets.com/api/v1/arm/ldnf1h.json"},{"mnemonic":"ldnf1w","slug":"ldnf1w","records":1,"summary":"Loads words without faulting.","page":"https://instructionsets.com/arm/ldnf1w/","api":"https://instructionsets.com/api/v1/arm/ldnf1w.json"},{"mnemonic":"ldnp","slug":"ldnp","records":1,"summary":"Loads two words, hinting non-temporal data (no caching).","page":"https://instructionsets.com/arm/ldnp/","api":"https://instructionsets.com/api/v1/arm/ldnp.json"},{"mnemonic":"ldp","slug":"ldp","records":3,"summary":"Loads two floating-point/SIMD registers.","page":"https://instructionsets.com/arm/ldp/","api":"https://instructionsets.com/api/v1/arm/ldp.json"},{"mnemonic":"ldpsw","slug":"ldpsw","records":1,"summary":"Loads two words and sign-extends them to 64-bit.","page":"https://instructionsets.com/arm/ldpsw/","api":"https://instructionsets.com/api/v1/arm/ldpsw.json"},{"mnemonic":"ldr","slug":"ldr","records":7,"summary":"Loads a floating-point/SIMD register from memory.","page":"https://instructionsets.com/arm/ldr/","api":"https://instructionsets.com/api/v1/arm/ldr.json"},{"mnemonic":"ldr.w","slug":"ldr_w","records":1,"summary":"Thumb-2 32-bit Load Word.","page":"https://instructionsets.com/arm/ldr_w/","api":"https://instructionsets.com/api/v1/arm/ldr_w.json"},{"mnemonic":"ldraa","slug":"ldraa","records":1,"summary":"Loads a value, authenticating the address with Key A.","page":"https://instructionsets.com/arm/ldraa/","api":"https://instructionsets.com/api/v1/arm/ldraa.json"},{"mnemonic":"ldrab","slug":"ldrab","records":1,"summary":"Loads a value, authenticating the address with Key B.","page":"https://instructionsets.com/arm/ldrab/","api":"https://instructionsets.com/api/v1/arm/ldrab.json"},{"mnemonic":"ldrb","slug":"ldrb","records":3,"summary":"Loads a byte from memory (zero-extended) using immediate offset.","page":"https://instructionsets.com/arm/ldrb/","api":"https://instructionsets.com/api/v1/arm/ldrb.json"},{"mnemonic":"ldrb.w","slug":"ldrb_w","records":1,"summary":"Thumb-2 32-bit Load Byte.","page":"https://instructionsets.com/arm/ldrb_w/","api":"https://instructionsets.com/api/v1/arm/ldrb_w.json"},{"mnemonic":"ldrbt","slug":"ldrbt","records":1,"summary":"Loads a byte using User Mode permissions.","page":"https://instructionsets.com/arm/ldrbt/","api":"https://instructionsets.com/api/v1/arm/ldrbt.json"},{"mnemonic":"ldrd","slug":"ldrd","records":2,"summary":"Loads two words from memory (Thumb).","page":"https://instructionsets.com/arm/ldrd/","api":"https://instructionsets.com/api/v1/arm/ldrd.json"},{"mnemonic":"ldrex","slug":"ldrex","records":2,"summary":"Loads word and sets exclusive monitor (Thumb).","page":"https://instructionsets.com/arm/ldrex/","api":"https://instructionsets.com/api/v1/arm/ldrex.json"},{"mnemonic":"ldrexb","slug":"ldrexb","records":2,"summary":"Loads a byte and marks address as exclusive.","page":"https://instructionsets.com/arm/ldrexb/","api":"https://instructionsets.com/api/v1/arm/ldrexb.json"},{"mnemonic":"ldrexd","slug":"ldrexd","records":1,"summary":"Loads a doubleword and marks address as exclusive.","page":"https://instructionsets.com/arm/ldrexd/","api":"https://instructionsets.com/api/v1/arm/ldrexd.json"},{"mnemonic":"ldrexh","slug":"ldrexh","records":2,"summary":"Loads a halfword and marks address as exclusive.","page":"https://instructionsets.com/arm/ldrexh/","api":"https://instructionsets.com/api/v1/arm/ldrexh.json"},{"mnemonic":"ldrh","slug":"ldrh","records":3,"summary":"Loads a halfword from memory (zero-extended).","page":"https://instructionsets.com/arm/ldrh/","api":"https://instructionsets.com/api/v1/arm/ldrh.json"},{"mnemonic":"ldrh.w","slug":"ldrh_w","records":1,"summary":"Thumb-2 32-bit Load Halfword.","page":"https://instructionsets.com/arm/ldrh_w/","api":"https://instructionsets.com/api/v1/arm/ldrh_w.json"},{"mnemonic":"ldrht","slug":"ldrht","records":1,"summary":"Loads a halfword using User Mode permissions.","page":"https://instructionsets.com/arm/ldrht/","api":"https://instructionsets.com/api/v1/arm/ldrht.json"},{"mnemonic":"ldrsb","slug":"ldrsb","records":3,"summary":"Loads a byte and sign-extends it to 32-bits.","page":"https://instructionsets.com/arm/ldrsb/","api":"https://instructionsets.com/api/v1/arm/ldrsb.json"},{"mnemonic":"ldrsb.w","slug":"ldrsb_w","records":1,"summary":"Thumb-2 32-bit Load Signed Byte.","page":"https://instructionsets.com/arm/ldrsb_w/","api":"https://instructionsets.com/api/v1/arm/ldrsb_w.json"},{"mnemonic":"ldrsbt","slug":"ldrsbt","records":1,"summary":"Loads a signed byte using User Mode permissions.","page":"https://instructionsets.com/arm/ldrsbt/","api":"https://instructionsets.com/api/v1/arm/ldrsbt.json"},{"mnemonic":"ldrsh","slug":"ldrsh","records":1,"summary":"Loads a halfword and sign-extends it.","page":"https://instructionsets.com/arm/ldrsh/","api":"https://instructionsets.com/api/v1/arm/ldrsh.json"},{"mnemonic":"ldrsh.w","slug":"ldrsh_w","records":1,"summary":"Thumb-2 32-bit Load Signed Halfword.","page":"https://instructionsets.com/arm/ldrsh_w/","api":"https://instructionsets.com/api/v1/arm/ldrsh_w.json"},{"mnemonic":"ldrsht","slug":"ldrsht","records":1,"summary":"Loads a signed halfword using User Mode permissions.","page":"https://instructionsets.com/arm/ldrsht/","api":"https://instructionsets.com/api/v1/arm/ldrsht.json"},{"mnemonic":"ldrsw","slug":"ldrsw","records":2,"summary":"Loads a word and sign-extends it to 64-bits.","page":"https://instructionsets.com/arm/ldrsw/","api":"https://instructionsets.com/api/v1/arm/ldrsw.json"},{"mnemonic":"ldrt","slug":"ldrt","records":1,"summary":"Loads a word using User Mode permissions (even if Privileged).","page":"https://instructionsets.com/arm/ldrt/","api":"https://instructionsets.com/api/v1/arm/ldrt.json"},{"mnemonic":"ldset","slug":"ldset","records":1,"summary":"Atomic bit set (OR) to memory.","page":"https://instructionsets.com/arm/ldset/","api":"https://instructionsets.com/api/v1/arm/ldset.json"},{"mnemonic":"ldsmax","slug":"ldsmax","records":1,"summary":"Atomic signed max to memory.","page":"https://instructionsets.com/arm/ldsmax/","api":"https://instructionsets.com/api/v1/arm/ldsmax.json"},{"mnemonic":"ldsmin","slug":"ldsmin","records":1,"summary":"Atomic signed min to memory.","page":"https://instructionsets.com/arm/ldsmin/","api":"https://instructionsets.com/api/v1/arm/ldsmin.json"},{"mnemonic":"ldtr","slug":"ldtr","records":1,"summary":"Loads a word as if in EL0 (User mode).","page":"https://instructionsets.com/arm/ldtr/","api":"https://instructionsets.com/api/v1/arm/ldtr.json"},{"mnemonic":"ldumax","slug":"ldumax","records":1,"summary":"Atomic unsigned max to memory.","page":"https://instructionsets.com/arm/ldumax/","api":"https://instructionsets.com/api/v1/arm/ldumax.json"},{"mnemonic":"ldumin","slug":"ldumin","records":1,"summary":"Atomic unsigned min to memory.","page":"https://instructionsets.com/arm/ldumin/","api":"https://instructionsets.com/api/v1/arm/ldumin.json"},{"mnemonic":"ldur","slug":"ldur","records":1,"summary":"Loads a word using an unscaled immediate offset.","page":"https://instructionsets.com/arm/ldur/","api":"https://instructionsets.com/api/v1/arm/ldur.json"},{"mnemonic":"ldxp","slug":"ldxp","records":1,"summary":"Loads two words as an exclusive operation.","page":"https://instructionsets.com/arm/ldxp/","api":"https://instructionsets.com/api/v1/arm/ldxp.json"},{"mnemonic":"ldxr","slug":"ldxr","records":1,"summary":"Loads a word and marks physical address as exclusive access.","page":"https://instructionsets.com/arm/ldxr/","api":"https://instructionsets.com/api/v1/arm/ldxr.json"},{"mnemonic":"lsl","slug":"lsl","records":3,"summary":"Shifts register left by variable amount.","page":"https://instructionsets.com/arm/lsl/","api":"https://instructionsets.com/api/v1/arm/lsl.json"},{"mnemonic":"lsr","slug":"lsr","records":3,"summary":"Shifts register right by variable amount.","page":"https://instructionsets.com/arm/lsr/","api":"https://instructionsets.com/api/v1/arm/lsr.json"},{"mnemonic":"madd","slug":"madd","records":2,"summary":"Calculates (Ra + (Rn * Rm)).","page":"https://instructionsets.com/arm/madd/","api":"https://instructionsets.com/api/v1/arm/madd.json"},{"mnemonic":"mcr","slug":"mcr","records":1,"summary":"Writes a general-purpose register to a coprocessor register (e.g., CP15).","page":"https://instructionsets.com/arm/mcr/","api":"https://instructionsets.com/api/v1/arm/mcr.json"},{"mnemonic":"mcr2","slug":"mcr2","records":1,"summary":"Writes a general-purpose register to a coprocessor (Extension encoding).","page":"https://instructionsets.com/arm/mcr2/","api":"https://instructionsets.com/api/v1/arm/mcr2.json"},{"mnemonic":"mcrr","slug":"mcrr","records":1,"summary":"Writes two general-purpose registers to a coprocessor (64-bit transfer).","page":"https://instructionsets.com/arm/mcrr/","api":"https://instructionsets.com/api/v1/arm/mcrr.json"},{"mnemonic":"mcrr2","slug":"mcrr2","records":1,"summary":"Writes two registers to a coprocessor (Extension encoding).","page":"https://instructionsets.com/arm/mcrr2/","api":"https://instructionsets.com/api/v1/arm/mcrr2.json"},{"mnemonic":"mia","slug":"mia","records":1,"summary":"Multiplies two 32-bit values and adds to 40-bit internal acc (XScale Legacy).","page":"https://instructionsets.com/arm/mia/","api":"https://instructionsets.com/api/v1/arm/mia.json"},{"mnemonic":"miaph","slug":"miaph","records":1,"summary":"SIMD multiply of packed halfwords to internal acc (XScale Legacy).","page":"https://instructionsets.com/arm/miaph/","api":"https://instructionsets.com/api/v1/arm/miaph.json"},{"mnemonic":"mla","slug":"mla","records":3,"summary":"Multiplies elements and adds to destination (Vd = Vd + Vn * Vm).","page":"https://instructionsets.com/arm/mla/","api":"https://instructionsets.com/api/v1/arm/mla.json"},{"mnemonic":"mls","slug":"mls","records":3,"summary":"Multiplies elements and subtracts from destination (Vd = Vd - Vn * Vm).","page":"https://instructionsets.com/arm/mls/","api":"https://instructionsets.com/api/v1/arm/mls.json"},{"mnemonic":"mov","slug":"mov","records":3,"summary":"Copies a vector register (Alias for ORR Vd, Vn, Vn).","page":"https://instructionsets.com/arm/mov/","api":"https://instructionsets.com/api/v1/arm/mov.json"},{"mnemonic":"mov.w","slug":"mov_w","records":1,"summary":"Thumb-2 32-bit Move.","page":"https://instructionsets.com/arm/mov_w/","api":"https://instructionsets.com/api/v1/arm/mov_w.json"},{"mnemonic":"movi","slug":"movi","records":1,"summary":"Moves an immediate value into every element of a vector.","page":"https://instructionsets.com/arm/movi/","api":"https://instructionsets.com/api/v1/arm/movi.json"},{"mnemonic":"movk","slug":"movk","records":1,"summary":"Inserts a 16-bit immediate into a register, keeping other bits unchanged.","page":"https://instructionsets.com/arm/movk/","api":"https://instructionsets.com/api/v1/arm/movk.json"},{"mnemonic":"movn","slug":"movn","records":1,"summary":"Moves inverted 16-bit immediate to register.","page":"https://instructionsets.com/arm/movn/","api":"https://instructionsets.com/api/v1/arm/movn.json"},{"mnemonic":"movt","slug":"movt","records":1,"summary":"Writes a 16-bit immediate to the top half of a register.","page":"https://instructionsets.com/arm/movt/","api":"https://instructionsets.com/api/v1/arm/movt.json"},{"mnemonic":"movw","slug":"movw","records":1,"summary":"Writes a 16-bit immediate to the bottom half, zeroing top.","page":"https://instructionsets.com/arm/movw/","api":"https://instructionsets.com/api/v1/arm/movw.json"},{"mnemonic":"movz","slug":"movz","records":1,"summary":"Moves 16-bit immediate to register, zeroing other bits.","page":"https://instructionsets.com/arm/movz/","api":"https://instructionsets.com/api/v1/arm/movz.json"},{"mnemonic":"mrc","slug":"mrc","records":1,"summary":"Reads a coprocessor register into a general-purpose register.","page":"https://instructionsets.com/arm/mrc/","api":"https://instructionsets.com/api/v1/arm/mrc.json"},{"mnemonic":"mrc2","slug":"mrc2","records":1,"summary":"Reads a coprocessor register into a general-purpose register (Extension encoding).","page":"https://instructionsets.com/arm/mrc2/","api":"https://instructionsets.com/api/v1/arm/mrc2.json"},{"mnemonic":"mrrc","slug":"mrrc","records":1,"summary":"Reads a coprocessor register into two general-purpose registers.","page":"https://instructionsets.com/arm/mrrc/","api":"https://instructionsets.com/api/v1/arm/mrrc.json"},{"mnemonic":"mrrc2","slug":"mrrc2","records":1,"summary":"Reads a coprocessor register into two registers (Extension encoding).","page":"https://instructionsets.com/arm/mrrc2/","api":"https://instructionsets.com/api/v1/arm/mrrc2.json"},{"mnemonic":"mrrs","slug":"mrrs","records":1,"summary":"Reads a 128-bit system register into two general-purpose registers.","page":"https://instructionsets.com/arm/mrrs/","api":"https://instructionsets.com/api/v1/arm/mrrs.json"},{"mnemonic":"mrs","slug":"mrs","records":4,"summary":"Moves system register to general-purpose register.","page":"https://instructionsets.com/arm/mrs/","api":"https://instructionsets.com/api/v1/arm/mrs.json"},{"mnemonic":"msr","slug":"msr","records":6,"summary":"Moves general-purpose register to system register.","page":"https://instructionsets.com/arm/msr/","api":"https://instructionsets.com/api/v1/arm/msr.json"},{"mnemonic":"msrr","slug":"msrr","records":1,"summary":"Writes two general-purpose registers into a 128-bit system register.","page":"https://instructionsets.com/arm/msrr/","api":"https://instructionsets.com/api/v1/arm/msrr.json"},{"mnemonic":"msub","slug":"msub","records":1,"summary":"Calculates (Ra - (Rn * Rm)).","page":"https://instructionsets.com/arm/msub/","api":"https://instructionsets.com/api/v1/arm/msub.json"},{"mnemonic":"mul","slug":"mul","records":3,"summary":"Multiplies corresponding elements in two vectors.","page":"https://instructionsets.com/arm/mul/","api":"https://instructionsets.com/api/v1/arm/mul.json"},{"mnemonic":"mvn","slug":"mvn","records":2,"summary":"Bitwise NOT of a vector.","page":"https://instructionsets.com/arm/mvn/","api":"https://instructionsets.com/api/v1/arm/mvn.json"},{"mnemonic":"mvn.w","slug":"mvn_w","records":1,"summary":"Thumb-2 32-bit Move Inverse.","page":"https://instructionsets.com/arm/mvn_w/","api":"https://instructionsets.com/api/v1/arm/mvn_w.json"},{"mnemonic":"mvni","slug":"mvni","records":1,"summary":"Moves the inverse of an immediate value into every element.","page":"https://instructionsets.com/arm/mvni/","api":"https://instructionsets.com/api/v1/arm/mvni.json"},{"mnemonic":"neg","slug":"neg","records":2,"summary":"Negates integers.","page":"https://instructionsets.com/arm/neg/","api":"https://instructionsets.com/api/v1/arm/neg.json"},{"mnemonic":"nop","slug":"nop","records":3,"summary":"Does nothing. Used for padding or timing.","page":"https://instructionsets.com/arm/nop/","api":"https://instructionsets.com/api/v1/arm/nop.json"},{"mnemonic":"not","slug":"not","records":2,"summary":"Inverts bits.","page":"https://instructionsets.com/arm/not/","api":"https://instructionsets.com/api/v1/arm/not.json"},{"mnemonic":"orn","slug":"orn","records":2,"summary":"ORs register with NOT of shifted register.","page":"https://instructionsets.com/arm/orn/","api":"https://instructionsets.com/api/v1/arm/orn.json"},{"mnemonic":"orn.w","slug":"orn_w","records":1,"summary":"Thumb-2 32-bit OR NOT.","page":"https://instructionsets.com/arm/orn_w/","api":"https://instructionsets.com/api/v1/arm/orn_w.json"},{"mnemonic":"orr","slug":"orr","records":5,"summary":"ORs register with logical immediate.","page":"https://instructionsets.com/arm/orr/","api":"https://instructionsets.com/api/v1/arm/orr.json"},{"mnemonic":"orr.w","slug":"orr_w","records":1,"summary":"Thumb-2 32-bit OR.","page":"https://instructionsets.com/arm/orr_w/","api":"https://instructionsets.com/api/v1/arm/orr_w.json"},{"mnemonic":"orv","slug":"orv","records":1,"summary":"ORs all active elements into a scalar.","page":"https://instructionsets.com/arm/orv/","api":"https://instructionsets.com/api/v1/arm/orv.json"},{"mnemonic":"pacda","slug":"pacda","records":2,"summary":"Signs a data pointer using Key A.","page":"https://instructionsets.com/arm/pacda/","api":"https://instructionsets.com/api/v1/arm/pacda.json"},{"mnemonic":"pacdb","slug":"pacdb","records":2,"summary":"Signs a data pointer using Key B.","page":"https://instructionsets.com/arm/pacdb/","api":"https://instructionsets.com/api/v1/arm/pacdb.json"},{"mnemonic":"pacga","slug":"pacga","records":1,"summary":"Computes a pointer authentication code for an address and modifier.","page":"https://instructionsets.com/arm/pacga/","api":"https://instructionsets.com/api/v1/arm/pacga.json"},{"mnemonic":"pacia","slug":"pacia","records":2,"summary":"Signs a pointer in Xd using Key A and modifier Xm (or SP).","page":"https://instructionsets.com/arm/pacia/","api":"https://instructionsets.com/api/v1/arm/pacia.json"},{"mnemonic":"pacib","slug":"pacib","records":2,"summary":"Signs a pointer in Xd using Key B.","page":"https://instructionsets.com/arm/pacib/","api":"https://instructionsets.com/api/v1/arm/pacib.json"},{"mnemonic":"pfalse","slug":"pfalse","records":1,"summary":"Clears all elements of the predicate register.","page":"https://instructionsets.com/arm/pfalse/","api":"https://instructionsets.com/api/v1/arm/pfalse.json"},{"mnemonic":"pfirst","slug":"pfirst","records":1,"summary":"Sets destination predicate to true only at the first active element.","page":"https://instructionsets.com/arm/pfirst/","api":"https://instructionsets.com/api/v1/arm/pfirst.json"},{"mnemonic":"pkhbt","slug":"pkhbt","records":1,"summary":"Combines bottom half of Rn with top half of shifted Rm.","page":"https://instructionsets.com/arm/pkhbt/","api":"https://instructionsets.com/api/v1/arm/pkhbt.json"},{"mnemonic":"pkhtb","slug":"pkhtb","records":1,"summary":"Combines top half of Rn with bottom half of shifted Rm.","page":"https://instructionsets.com/arm/pkhtb/","api":"https://instructionsets.com/api/v1/arm/pkhtb.json"},{"mnemonic":"pld","slug":"pld","records":1,"summary":"Hints memory system to bring data into cache.","page":"https://instructionsets.com/arm/pld/","api":"https://instructionsets.com/api/v1/arm/pld.json"},{"mnemonic":"pldw","slug":"pldw","records":2,"summary":"Hints memory system to bring data into cache for writing.","page":"https://instructionsets.com/arm/pldw/","api":"https://instructionsets.com/api/v1/arm/pldw.json"},{"mnemonic":"pli","slug":"pli","records":1,"summary":"Hints memory system to bring instructions into cache.","page":"https://instructionsets.com/arm/pli/","api":"https://instructionsets.com/api/v1/arm/pli.json"},{"mnemonic":"pmul","slug":"pmul","records":1,"summary":"Performs polynomial multiplication over {0,1}.","page":"https://instructionsets.com/arm/pmul/","api":"https://instructionsets.com/api/v1/arm/pmul.json"},{"mnemonic":"pmull","slug":"pmull","records":2,"summary":"Polynomial multiply long (NEON).","page":"https://instructionsets.com/arm/pmull/","api":"https://instructionsets.com/api/v1/arm/pmull.json"},{"mnemonic":"pnext","slug":"pnext","records":1,"summary":"Finds the next active predicate bit.","page":"https://instructionsets.com/arm/pnext/","api":"https://instructionsets.com/api/v1/arm/pnext.json"},{"mnemonic":"pop","slug":"pop","records":2,"summary":"Pop registers from stack (Thumb 16-bit).","page":"https://instructionsets.com/arm/pop/","api":"https://instructionsets.com/api/v1/arm/pop.json"},{"mnemonic":"pop.w","slug":"pop_w","records":1,"summary":"Thumb-2 32-bit Pop.","page":"https://instructionsets.com/arm/pop_w/","api":"https://instructionsets.com/api/v1/arm/pop_w.json"},{"mnemonic":"prfm","slug":"prfm","records":3,"summary":"Signals the memory system to prefetch data into cache.","page":"https://instructionsets.com/arm/prfm/","api":"https://instructionsets.com/api/v1/arm/prfm.json"},{"mnemonic":"psb","slug":"psb","records":1,"summary":"Synchronizes the statistical profiling unit.","page":"https://instructionsets.com/arm/psb/","api":"https://instructionsets.com/api/v1/arm/psb.json"},{"mnemonic":"pssbb","slug":"pssbb","records":2,"summary":"Prevents speculation on physical resources (v8.0).","page":"https://instructionsets.com/arm/pssbb/","api":"https://instructionsets.com/api/v1/arm/pssbb.json"},{"mnemonic":"ptest","slug":"ptest","records":1,"summary":"Updates processor flags (NZCV) based on predicate state.","page":"https://instructionsets.com/arm/ptest/","api":"https://instructionsets.com/api/v1/arm/ptest.json"},{"mnemonic":"ptrue","slug":"ptrue","records":1,"summary":"Sets elements of the predicate register to true (all active).","page":"https://instructionsets.com/arm/ptrue/","api":"https://instructionsets.com/api/v1/arm/ptrue.json"},{"mnemonic":"push","slug":"push","records":2,"summary":"Push registers to stack (Thumb 16-bit).","page":"https://instructionsets.com/arm/push/","api":"https://instructionsets.com/api/v1/arm/push.json"},{"mnemonic":"push.w","slug":"push_w","records":1,"summary":"Thumb-2 32-bit Push.","page":"https://instructionsets.com/arm/push_w/","api":"https://instructionsets.com/api/v1/arm/push_w.json"},{"mnemonic":"qadd","slug":"qadd","records":1,"summary":"Adds two values and saturates the result.","page":"https://instructionsets.com/arm/qadd/","api":"https://instructionsets.com/api/v1/arm/qadd.json"},{"mnemonic":"qadd16","slug":"qadd16","records":1,"summary":"Parallel saturating add of 2 signed halfwords.","page":"https://instructionsets.com/arm/qadd16/","api":"https://instructionsets.com/api/v1/arm/qadd16.json"},{"mnemonic":"qadd8","slug":"qadd8","records":1,"summary":"Parallel saturating add of 4 signed bytes.","page":"https://instructionsets.com/arm/qadd8/","api":"https://instructionsets.com/api/v1/arm/qadd8.json"},{"mnemonic":"qdadd","slug":"qdadd","records":1,"summary":"Doubles the second operand, adds to first, and saturates.","page":"https://instructionsets.com/arm/qdadd/","api":"https://instructionsets.com/api/v1/arm/qdadd.json"},{"mnemonic":"qdsub","slug":"qdsub","records":1,"summary":"Doubles the second operand, subtracts from first, and saturates.","page":"https://instructionsets.com/arm/qdsub/","api":"https://instructionsets.com/api/v1/arm/qdsub.json"},{"mnemonic":"qsub","slug":"qsub","records":1,"summary":"Subtracts two values and saturates the result.","page":"https://instructionsets.com/arm/qsub/","api":"https://instructionsets.com/api/v1/arm/qsub.json"},{"mnemonic":"qsub16","slug":"qsub16","records":1,"summary":"Parallel saturating subtract of 2 signed halfwords.","page":"https://instructionsets.com/arm/qsub16/","api":"https://instructionsets.com/api/v1/arm/qsub16.json"},{"mnemonic":"qsub8","slug":"qsub8","records":1,"summary":"Parallel saturating subtract of 4 signed bytes.","page":"https://instructionsets.com/arm/qsub8/","api":"https://instructionsets.com/api/v1/arm/qsub8.json"},{"mnemonic":"rbit","slug":"rbit","records":5,"summary":"Reverses bits in each element.","page":"https://instructionsets.com/arm/rbit/","api":"https://instructionsets.com/api/v1/arm/rbit.json"},{"mnemonic":"rcwsswpp","slug":"rcwsswpp","records":1,"summary":"Read Check Write with soft failure reporting (Translation Hardening).","page":"https://instructionsets.com/arm/rcwsswpp/","api":"https://instructionsets.com/api/v1/arm/rcwsswpp.json"},{"mnemonic":"rcwswpp","slug":"rcwswpp","records":1,"summary":"Atomically swaps a 128-bit register pair with a checked descriptor in memory (Translation Hardening).","page":"https://instructionsets.com/arm/rcwswpp/","api":"https://instructionsets.com/api/v1/arm/rcwswpp.json"},{"mnemonic":"rcwswppa","slug":"rcwswppa","records":1,"summary":"Atomically swaps a 128-bit register pair with a checked descriptor in memory, with Acquire semantics (Translation Hardening).","page":"https://instructionsets.com/arm/rcwswppa/","api":"https://instructionsets.com/api/v1/arm/rcwswppa.json"},{"mnemonic":"rcwswppal","slug":"rcwswppal","records":1,"summary":"Atomically swaps a 128-bit register pair with a checked descriptor in memory, with Acquire and Release semantics (Translation Hardening).","page":"https://instructionsets.com/arm/rcwswppal/","api":"https://instructionsets.com/api/v1/arm/rcwswppal.json"},{"mnemonic":"ret","slug":"ret","records":1,"summary":"Branches to address in LR (or specified register).","page":"https://instructionsets.com/arm/ret/","api":"https://instructionsets.com/api/v1/arm/ret.json"},{"mnemonic":"rev","slug":"rev","records":6,"summary":"Reverses the order of elements in the vector.","page":"https://instructionsets.com/arm/rev/","api":"https://instructionsets.com/api/v1/arm/rev.json"},{"mnemonic":"rev16","slug":"rev16","records":3,"summary":"Reverse bytes in halfwords (Thumb).","page":"https://instructionsets.com/arm/rev16/","api":"https://instructionsets.com/api/v1/arm/rev16.json"},{"mnemonic":"rev32","slug":"rev32","records":1,"summary":"Reverses bytes in each 32-bit word (64-bit op).","page":"https://instructionsets.com/arm/rev32/","api":"https://instructionsets.com/api/v1/arm/rev32.json"},{"mnemonic":"revb","slug":"revb","records":1,"summary":"Reverses bytes within 16/32/64-bit elements.","page":"https://instructionsets.com/arm/revb/","api":"https://instructionsets.com/api/v1/arm/revb.json"},{"mnemonic":"revh","slug":"revh","records":1,"summary":"Reverses halfwords within 32/64-bit elements.","page":"https://instructionsets.com/arm/revh/","api":"https://instructionsets.com/api/v1/arm/revh.json"},{"mnemonic":"revsh","slug":"revsh","records":2,"summary":"Reverse bytes in low halfword, sign extend (Thumb).","page":"https://instructionsets.com/arm/revsh/","api":"https://instructionsets.com/api/v1/arm/revsh.json"},{"mnemonic":"revw","slug":"revw","records":1,"summary":"Reverses words within 64-bit elements.","page":"https://instructionsets.com/arm/revw/","api":"https://instructionsets.com/api/v1/arm/revw.json"},{"mnemonic":"rfe","slug":"rfe","records":1,"summary":"Loads PC and CPSR from the stack.","page":"https://instructionsets.com/arm/rfe/","api":"https://instructionsets.com/api/v1/arm/rfe.json"},{"mnemonic":"rmif","slug":"rmif","records":1,"summary":"Rotates a register and inserts bits into the Process State flags.","page":"https://instructionsets.com/arm/rmif/","api":"https://instructionsets.com/api/v1/arm/rmif.json"},{"mnemonic":"rndr","slug":"rndr","records":1,"summary":"Reads a random number from hardware entropy source.","page":"https://instructionsets.com/arm/rndr/","api":"https://instructionsets.com/api/v1/arm/rndr.json"},{"mnemonic":"rndrrs","slug":"rndrrs","records":1,"summary":"Reads a random number and requests reseed.","page":"https://instructionsets.com/arm/rndrrs/","api":"https://instructionsets.com/api/v1/arm/rndrrs.json"},{"mnemonic":"ror","slug":"ror","records":1,"summary":"Rotates register right.","page":"https://instructionsets.com/arm/ror/","api":"https://instructionsets.com/api/v1/arm/ror.json"},{"mnemonic":"rorv","slug":"rorv","records":1,"summary":"Rotates register right by variable amount.","page":"https://instructionsets.com/arm/rorv/","api":"https://instructionsets.com/api/v1/arm/rorv.json"},{"mnemonic":"rrx","slug":"rrx","records":2,"summary":"Shifts register right by 1, inserting Carry flag into MSB.","page":"https://instructionsets.com/arm/rrx/","api":"https://instructionsets.com/api/v1/arm/rrx.json"},{"mnemonic":"rsb","slug":"rsb","records":2,"summary":"Reverse Subtract (Thumb 16-bit).","page":"https://instructionsets.com/arm/rsb/","api":"https://instructionsets.com/api/v1/arm/rsb.json"},{"mnemonic":"rsb.w","slug":"rsb_w","records":1,"summary":"Thumb-2 32-bit reverse subtract.","page":"https://instructionsets.com/arm/rsb_w/","api":"https://instructionsets.com/api/v1/arm/rsb_w.json"},{"mnemonic":"rsc","slug":"rsc","records":1,"summary":"Calculates Rd = Operand2 - Rn - NOT(Carry).","page":"https://instructionsets.com/arm/rsc/","api":"https://instructionsets.com/api/v1/arm/rsc.json"},{"mnemonic":"sadd16","slug":"sadd16","records":1,"summary":"Parallel add of two signed 16-bit halfwords.","page":"https://instructionsets.com/arm/sadd16/","api":"https://instructionsets.com/api/v1/arm/sadd16.json"},{"mnemonic":"sadd8","slug":"sadd8","records":1,"summary":"Parallel add of four signed 8-bit bytes.","page":"https://instructionsets.com/arm/sadd8/","api":"https://instructionsets.com/api/v1/arm/sadd8.json"},{"mnemonic":"saddl","slug":"saddl","records":1,"summary":"Adds lower/upper halves of signed vectors, producing wider result (Widening).","page":"https://instructionsets.com/arm/saddl/","api":"https://instructionsets.com/api/v1/arm/saddl.json"},{"mnemonic":"saddv","slug":"saddv","records":1,"summary":"Sums all active signed elements into a scalar result.","page":"https://instructionsets.com/arm/saddv/","api":"https://instructionsets.com/api/v1/arm/saddv.json"},{"mnemonic":"saddw","slug":"saddw","records":1,"summary":"Adds a wide vector to the lower/upper half of a narrow vector.","page":"https://instructionsets.com/arm/saddw/","api":"https://instructionsets.com/api/v1/arm/saddw.json"},{"mnemonic":"sb","slug":"sb","records":2,"summary":"Prevents speculative execution across the barrier (v8.0).","page":"https://instructionsets.com/arm/sb/","api":"https://instructionsets.com/api/v1/arm/sb.json"},{"mnemonic":"sbc","slug":"sbc","records":2,"summary":"Subtracts with borrow (Carry - 1).","page":"https://instructionsets.com/arm/sbc/","api":"https://instructionsets.com/api/v1/arm/sbc.json"},{"mnemonic":"sbc.w","slug":"sbc_w","records":1,"summary":"Thumb-2 32-bit subtract with carry.","page":"https://instructionsets.com/arm/sbc_w/","api":"https://instructionsets.com/api/v1/arm/sbc_w.json"},{"mnemonic":"sbcs","slug":"sbcs","records":1,"summary":"Subtracts with borrow and updates flags.","page":"https://instructionsets.com/arm/sbcs/","api":"https://instructionsets.com/api/v1/arm/sbcs.json"},{"mnemonic":"sbfm","slug":"sbfm","records":1,"summary":"Extracts/Inserts bitfield with sign extension.","page":"https://instructionsets.com/arm/sbfm/","api":"https://instructionsets.com/api/v1/arm/sbfm.json"},{"mnemonic":"sbfx","slug":"sbfx","records":2,"summary":"Extracts bits from a register and sign-extends them.","page":"https://instructionsets.com/arm/sbfx/","api":"https://instructionsets.com/api/v1/arm/sbfx.json"},{"mnemonic":"scvtf","slug":"scvtf","records":3,"summary":"Converts signed integers to floats.","page":"https://instructionsets.com/arm/scvtf/","api":"https://instructionsets.com/api/v1/arm/scvtf.json"},{"mnemonic":"sdiv","slug":"sdiv","records":4,"summary":"Divides signed integers.","page":"https://instructionsets.com/arm/sdiv/","api":"https://instructionsets.com/api/v1/arm/sdiv.json"},{"mnemonic":"sdot","slug":"sdot","records":4,"summary":"Computes dot product of signed integers (AI Acceleration).","page":"https://instructionsets.com/arm/sdot/","api":"https://instructionsets.com/api/v1/arm/sdot.json"},{"mnemonic":"sel","slug":"sel","records":2,"summary":"Selects elements from Zn or Zm based on predicate.","page":"https://instructionsets.com/arm/sel/","api":"https://instructionsets.com/api/v1/arm/sel.json"},{"mnemonic":"setend","slug":"setend","records":2,"summary":"Sets the endianness for data accesses (BE/LE).","page":"https://instructionsets.com/arm/setend/","api":"https://instructionsets.com/api/v1/arm/setend.json"},{"mnemonic":"setf16","slug":"setf16","records":1,"summary":"Sets PSTATE flags based on 16-bit operand.","page":"https://instructionsets.com/arm/setf16/","api":"https://instructionsets.com/api/v1/arm/setf16.json"},{"mnemonic":"setf8","slug":"setf8","records":1,"summary":"Sets PSTATE flags based on 8-bit operand.","page":"https://instructionsets.com/arm/setf8/","api":"https://instructionsets.com/api/v1/arm/setf8.json"},{"mnemonic":"setpan","slug":"setpan","records":1,"summary":"Enables/Disables PAN (Prevents kernel accessing user memory).","page":"https://instructionsets.com/arm/setpan/","api":"https://instructionsets.com/api/v1/arm/setpan.json"},{"mnemonic":"sev","slug":"sev","records":3,"summary":"Sends an event to all processors in the cluster (wakes up WFE).","page":"https://instructionsets.com/arm/sev/","api":"https://instructionsets.com/api/v1/arm/sev.json"},{"mnemonic":"sevl","slug":"sevl","records":3,"summary":"Sends an event locally to the executing processor.","page":"https://instructionsets.com/arm/sevl/","api":"https://instructionsets.com/api/v1/arm/sevl.json"},{"mnemonic":"sha1c","slug":"sha1c","records":3,"summary":"SHA1 hash update (Choose).","page":"https://instructionsets.com/arm/sha1c/","api":"https://instructionsets.com/api/v1/arm/sha1c.json"},{"mnemonic":"sha1h","slug":"sha1h","records":2,"summary":"Updates SHA1 hash state.","page":"https://instructionsets.com/arm/sha1h/","api":"https://instructionsets.com/api/v1/arm/sha1h.json"},{"mnemonic":"sha1m","slug":"sha1m","records":2,"summary":"SHA1 hash update (Majority).","page":"https://instructionsets.com/arm/sha1m/","api":"https://instructionsets.com/api/v1/arm/sha1m.json"},{"mnemonic":"sha1p","slug":"sha1p","records":2,"summary":"SHA1 hash update (Parity).","page":"https://instructionsets.com/arm/sha1p/","api":"https://instructionsets.com/api/v1/arm/sha1p.json"},{"mnemonic":"sha256h","slug":"sha256h","records":3,"summary":"SHA256 hash update (part 1).","page":"https://instructionsets.com/arm/sha256h/","api":"https://instructionsets.com/api/v1/arm/sha256h.json"},{"mnemonic":"sha256h2","slug":"sha256h2","records":3,"summary":"SHA256 hash update (part 2).","page":"https://instructionsets.com/arm/sha256h2/","api":"https://instructionsets.com/api/v1/arm/sha256h2.json"},{"mnemonic":"sha256su0","slug":"sha256su0","records":1,"summary":"SHA256 schedule update instruction 0.","page":"https://instructionsets.com/arm/sha256su0/","api":"https://instructionsets.com/api/v1/arm/sha256su0.json"},{"mnemonic":"sha256su1","slug":"sha256su1","records":1,"summary":"SHA256 schedule update instruction 1.","page":"https://instructionsets.com/arm/sha256su1/","api":"https://instructionsets.com/api/v1/arm/sha256su1.json"},{"mnemonic":"sha512h","slug":"sha512h","records":1,"summary":"SHA512 hash update part 1.","page":"https://instructionsets.com/arm/sha512h/","api":"https://instructionsets.com/api/v1/arm/sha512h.json"},{"mnemonic":"sha512h2","slug":"sha512h2","records":1,"summary":"SHA512 hash update part 2.","page":"https://instructionsets.com/arm/sha512h2/","api":"https://instructionsets.com/api/v1/arm/sha512h2.json"},{"mnemonic":"sha512su0","slug":"sha512su0","records":1,"summary":"SHA512 schedule update instruction 0.","page":"https://instructionsets.com/arm/sha512su0/","api":"https://instructionsets.com/api/v1/arm/sha512su0.json"},{"mnemonic":"sha512su1","slug":"sha512su1","records":1,"summary":"SHA512 schedule update instruction 1.","page":"https://instructionsets.com/arm/sha512su1/","api":"https://instructionsets.com/api/v1/arm/sha512su1.json"},{"mnemonic":"shadd16","slug":"shadd16","records":1,"summary":"Signed add and halving (average) of 2 halfwords.","page":"https://instructionsets.com/arm/shadd16/","api":"https://instructionsets.com/api/v1/arm/shadd16.json"},{"mnemonic":"shadd8","slug":"shadd8","records":1,"summary":"Signed add and halving (average) of 4 bytes.","page":"https://instructionsets.com/arm/shadd8/","api":"https://instructionsets.com/api/v1/arm/shadd8.json"},{"mnemonic":"shl","slug":"shl","records":1,"summary":"Shifts elements left by immediate value.","page":"https://instructionsets.com/arm/shl/","api":"https://instructionsets.com/api/v1/arm/shl.json"},{"mnemonic":"shll","slug":"shll","records":1,"summary":"Shifts narrow vector left, extending to wide result.","page":"https://instructionsets.com/arm/shll/","api":"https://instructionsets.com/api/v1/arm/shll.json"},{"mnemonic":"shrn","slug":"shrn","records":1,"summary":"Shifts wide vector right, narrowing to destination (Upper/Lower).","page":"https://instructionsets.com/arm/shrn/","api":"https://instructionsets.com/api/v1/arm/shrn.json"},{"mnemonic":"shsub16","slug":"shsub16","records":1,"summary":"Signed subtract and halving of 2 halfwords.","page":"https://instructionsets.com/arm/shsub16/","api":"https://instructionsets.com/api/v1/arm/shsub16.json"},{"mnemonic":"shsub8","slug":"shsub8","records":1,"summary":"Signed subtract and halving of 4 bytes.","page":"https://instructionsets.com/arm/shsub8/","api":"https://instructionsets.com/api/v1/arm/shsub8.json"},{"mnemonic":"sli","slug":"sli","records":1,"summary":"Shifts source left and inserts into destination.","page":"https://instructionsets.com/arm/sli/","api":"https://instructionsets.com/api/v1/arm/sli.json"},{"mnemonic":"sm3partw1","slug":"sm3partw1","records":1,"summary":"SM3 schedule update part 1.","page":"https://instructionsets.com/arm/sm3partw1/","api":"https://instructionsets.com/api/v1/arm/sm3partw1.json"},{"mnemonic":"sm3partw2","slug":"sm3partw2","records":1,"summary":"SM3 schedule update part 2.","page":"https://instructionsets.com/arm/sm3partw2/","api":"https://instructionsets.com/api/v1/arm/sm3partw2.json"},{"mnemonic":"sm3ss1","slug":"sm3ss1","records":1,"summary":"SM3 cryptographic hash step 1.","page":"https://instructionsets.com/arm/sm3ss1/","api":"https://instructionsets.com/api/v1/arm/sm3ss1.json"},{"mnemonic":"sm3tt1a","slug":"sm3tt1a","records":1,"summary":"SM3 cryptographic hash step 2A.","page":"https://instructionsets.com/arm/sm3tt1a/","api":"https://instructionsets.com/api/v1/arm/sm3tt1a.json"},{"mnemonic":"sm3tt1b","slug":"sm3tt1b","records":1,"summary":"SM3 cryptographic hash step 2B.","page":"https://instructionsets.com/arm/sm3tt1b/","api":"https://instructionsets.com/api/v1/arm/sm3tt1b.json"},{"mnemonic":"sm3tt2a","slug":"sm3tt2a","records":1,"summary":"SM3 cryptographic hash step 3A.","page":"https://instructionsets.com/arm/sm3tt2a/","api":"https://instructionsets.com/api/v1/arm/sm3tt2a.json"},{"mnemonic":"sm3tt2b","slug":"sm3tt2b","records":1,"summary":"SM3 cryptographic hash step 3B.","page":"https://instructionsets.com/arm/sm3tt2b/","api":"https://instructionsets.com/api/v1/arm/sm3tt2b.json"},{"mnemonic":"sm4e","slug":"sm4e","records":1,"summary":"SM4 encryption step.","page":"https://instructionsets.com/arm/sm4e/","api":"https://instructionsets.com/api/v1/arm/sm4e.json"},{"mnemonic":"sm4ekey","slug":"sm4ekey","records":1,"summary":"SM4 key schedule step.","page":"https://instructionsets.com/arm/sm4ekey/","api":"https://instructionsets.com/api/v1/arm/sm4ekey.json"},{"mnemonic":"smaddl","slug":"smaddl","records":1,"summary":"Multiplies two 32-bit registers, adds to 64-bit register (64-bit result).","page":"https://instructionsets.com/arm/smaddl/","api":"https://instructionsets.com/api/v1/arm/smaddl.json"},{"mnemonic":"smax","slug":"smax","records":2,"summary":"Determines maximum signed value per element.","page":"https://instructionsets.com/arm/smax/","api":"https://instructionsets.com/api/v1/arm/smax.json"},{"mnemonic":"smaxv","slug":"smaxv","records":2,"summary":"Finds max signed element in vector.","page":"https://instructionsets.com/arm/smaxv/","api":"https://instructionsets.com/api/v1/arm/smaxv.json"},{"mnemonic":"smc","slug":"smc","records":2,"summary":"Calls the Secure Monitor (EL3).","page":"https://instructionsets.com/arm/smc/","api":"https://instructionsets.com/api/v1/arm/smc.json"},{"mnemonic":"smin","slug":"smin","records":2,"summary":"Determines minimum signed value per element.","page":"https://instructionsets.com/arm/smin/","api":"https://instructionsets.com/api/v1/arm/smin.json"},{"mnemonic":"sminv","slug":"sminv","records":1,"summary":"Finds min signed element in vector.","page":"https://instructionsets.com/arm/sminv/","api":"https://instructionsets.com/api/v1/arm/sminv.json"},{"mnemonic":"smlabb","slug":"smlabb","records":1,"summary":"Accumulates (Rn.B * Rm.B) into Ra.","page":"https://instructionsets.com/arm/smlabb/","api":"https://instructionsets.com/api/v1/arm/smlabb.json"},{"mnemonic":"smlabt","slug":"smlabt","records":1,"summary":"Accumulates (Rn.B * Rm.T) into Ra.","page":"https://instructionsets.com/arm/smlabt/","api":"https://instructionsets.com/api/v1/arm/smlabt.json"},{"mnemonic":"smlad","slug":"smlad","records":1,"summary":"Dual multiply add + accumulate.","page":"https://instructionsets.com/arm/smlad/","api":"https://instructionsets.com/api/v1/arm/smlad.json"},{"mnemonic":"smlal","slug":"smlal","records":2,"summary":"Signed Multiply Accumulate (64-bit result).","page":"https://instructionsets.com/arm/smlal/","api":"https://instructionsets.com/api/v1/arm/smlal.json"},{"mnemonic":"smlalbb","slug":"smlalbb","records":1,"summary":"Accumulates (Rn.B * Rm.B) into 64-bit pair.","page":"https://instructionsets.com/arm/smlalbb/","api":"https://instructionsets.com/api/v1/arm/smlalbb.json"},{"mnemonic":"smlalbt","slug":"smlalbt","records":1,"summary":"Accumulates (Rn.B * Rm.T) into 64-bit pair.","page":"https://instructionsets.com/arm/smlalbt/","api":"https://instructionsets.com/api/v1/arm/smlalbt.json"},{"mnemonic":"smlald","slug":"smlald","records":1,"summary":"Dual multiply add + 64-bit accumulate.","page":"https://instructionsets.com/arm/smlald/","api":"https://instructionsets.com/api/v1/arm/smlald.json"},{"mnemonic":"smlaltb","slug":"smlaltb","records":1,"summary":"Accumulates (Rn.T * Rm.B) into 64-bit pair.","page":"https://instructionsets.com/arm/smlaltb/","api":"https://instructionsets.com/api/v1/arm/smlaltb.json"},{"mnemonic":"smlaltt","slug":"smlaltt","records":1,"summary":"Accumulates (Rn.T * Rm.T) into 64-bit pair.","page":"https://instructionsets.com/arm/smlaltt/","api":"https://instructionsets.com/api/v1/arm/smlaltt.json"},{"mnemonic":"smlatb","slug":"smlatb","records":1,"summary":"Accumulates (Rn.T * Rm.B) into Ra.","page":"https://instructionsets.com/arm/smlatb/","api":"https://instructionsets.com/api/v1/arm/smlatb.json"},{"mnemonic":"smlatt","slug":"smlatt","records":1,"summary":"Accumulates (Rn.T * Rm.T) into Ra.","page":"https://instructionsets.com/arm/smlatt/","api":"https://instructionsets.com/api/v1/arm/smlatt.json"},{"mnemonic":"smlawb","slug":"smlawb","records":1,"summary":"Performs SMULWB and adds to accumulator.","page":"https://instructionsets.com/arm/smlawb/","api":"https://instructionsets.com/api/v1/arm/smlawb.json"},{"mnemonic":"smlawt","slug":"smlawt","records":1,"summary":"Performs SMULWT and adds to accumulator.","page":"https://instructionsets.com/arm/smlawt/","api":"https://instructionsets.com/api/v1/arm/smlawt.json"},{"mnemonic":"smlsd","slug":"smlsd","records":1,"summary":"Dual multiply subtract + accumulate.","page":"https://instructionsets.com/arm/smlsd/","api":"https://instructionsets.com/api/v1/arm/smlsd.json"},{"mnemonic":"smlsld","slug":"smlsld","records":1,"summary":"Dual multiply subtract + 64-bit accumulate.","page":"https://instructionsets.com/arm/smlsld/","api":"https://instructionsets.com/api/v1/arm/smlsld.json"},{"mnemonic":"smmla","slug":"smmla","records":2,"summary":"Performs 2x2 matrix multiplication on Signed Int8 tiles.","page":"https://instructionsets.com/arm/smmla/","api":"https://instructionsets.com/api/v1/arm/smmla.json"},{"mnemonic":"smmul","slug":"smmul","records":1,"summary":"Multiplies and returns the top 32-bits of the 64-bit result.","page":"https://instructionsets.com/arm/smmul/","api":"https://instructionsets.com/api/v1/arm/smmul.json"},{"mnemonic":"smsubl","slug":"smsubl","records":1,"summary":"Calculates (Xa - (Wn * Wm)) (64-bit result).","page":"https://instructionsets.com/arm/smsubl/","api":"https://instructionsets.com/api/v1/arm/smsubl.json"},{"mnemonic":"smuad","slug":"smuad","records":1,"summary":"Performs two 16x16 multiplies and adds results (Top*Top + Bot*Bot).","page":"https://instructionsets.com/arm/smuad/","api":"https://instructionsets.com/api/v1/arm/smuad.json"},{"mnemonic":"smulbb","slug":"smulbb","records":1,"summary":"Multiplies bottom 16 bits of Rn and Rm.","page":"https://instructionsets.com/arm/smulbb/","api":"https://instructionsets.com/api/v1/arm/smulbb.json"},{"mnemonic":"smulbt","slug":"smulbt","records":1,"summary":"Multiplies bottom 16 bits of Rn and top 16 bits of Rm.","page":"https://instructionsets.com/arm/smulbt/","api":"https://instructionsets.com/api/v1/arm/smulbt.json"},{"mnemonic":"smulh","slug":"smulh","records":1,"summary":"Multiplies two 64-bit registers, keeps high 64 bits.","page":"https://instructionsets.com/arm/smulh/","api":"https://instructionsets.com/api/v1/arm/smulh.json"},{"mnemonic":"smull","slug":"smull","records":2,"summary":"Signed Multiply (64-bit result).","page":"https://instructionsets.com/arm/smull/","api":"https://instructionsets.com/api/v1/arm/smull.json"},{"mnemonic":"smultb","slug":"smultb","records":1,"summary":"Multiplies top 16 bits of Rn and bottom 16 bits of Rm.","page":"https://instructionsets.com/arm/smultb/","api":"https://instructionsets.com/api/v1/arm/smultb.json"},{"mnemonic":"smultt","slug":"smultt","records":1,"summary":"Multiplies top 16 bits of Rn and top 16 bits of Rm.","page":"https://instructionsets.com/arm/smultt/","api":"https://instructionsets.com/api/v1/arm/smultt.json"},{"mnemonic":"smulwb","slug":"smulwb","records":1,"summary":"Multiplies 32-bit Rn by bottom 16-bits of Rm, takes top 32-bits of result.","page":"https://instructionsets.com/arm/smulwb/","api":"https://instructionsets.com/api/v1/arm/smulwb.json"},{"mnemonic":"smulwt","slug":"smulwt","records":1,"summary":"Multiplies 32-bit Rn by top 16-bits of Rm, takes top 32-bits of result.","page":"https://instructionsets.com/arm/smulwt/","api":"https://instructionsets.com/api/v1/arm/smulwt.json"},{"mnemonic":"smusd","slug":"smusd","records":1,"summary":"Performs two 16x16 multiplies and subtracts results.","page":"https://instructionsets.com/arm/smusd/","api":"https://instructionsets.com/api/v1/arm/smusd.json"},{"mnemonic":"splice","slug":"splice","records":1,"summary":"Splices two vectors based on the last active element of the first.","page":"https://instructionsets.com/arm/splice/","api":"https://instructionsets.com/api/v1/arm/splice.json"},{"mnemonic":"sqadd","slug":"sqadd","records":1,"summary":"Adds signed integers with saturation.","page":"https://instructionsets.com/arm/sqadd/","api":"https://instructionsets.com/api/v1/arm/sqadd.json"},{"mnemonic":"sqsub","slug":"sqsub","records":1,"summary":"Subtracts signed integers with saturation.","page":"https://instructionsets.com/arm/sqsub/","api":"https://instructionsets.com/api/v1/arm/sqsub.json"},{"mnemonic":"sqxtn","slug":"sqxtn","records":1,"summary":"Reads wide elements, saturates, and narrows.","page":"https://instructionsets.com/arm/sqxtn/","api":"https://instructionsets.com/api/v1/arm/sqxtn.json"},{"mnemonic":"sri","slug":"sri","records":1,"summary":"Shifts source right and inserts into destination.","page":"https://instructionsets.com/arm/sri/","api":"https://instructionsets.com/api/v1/arm/sri.json"},{"mnemonic":"srs","slug":"srs","records":1,"summary":"Stores LR and SPSR to the stack of a specific mode.","page":"https://instructionsets.com/arm/srs/","api":"https://instructionsets.com/api/v1/arm/srs.json"},{"mnemonic":"ssat","slug":"ssat","records":1,"summary":"Saturates a signed value to a specified bit width.","page":"https://instructionsets.com/arm/ssat/","api":"https://instructionsets.com/api/v1/arm/ssat.json"},{"mnemonic":"ssat16","slug":"ssat16","records":1,"summary":"Saturates two signed 16-bit values.","page":"https://instructionsets.com/arm/ssat16/","api":"https://instructionsets.com/api/v1/arm/ssat16.json"},{"mnemonic":"ssbb","slug":"ssbb","records":1,"summary":"Prevents speculative loads bypassing earlier stores (v8.0).","page":"https://instructionsets.com/arm/ssbb/","api":"https://instructionsets.com/api/v1/arm/ssbb.json"},{"mnemonic":"sshr","slug":"sshr","records":1,"summary":"Shifts elements right (arithmetic/sign-extending).","page":"https://instructionsets.com/arm/sshr/","api":"https://instructionsets.com/api/v1/arm/sshr.json"},{"mnemonic":"ssra","slug":"ssra","records":1,"summary":"Arithmetic right shift and add to destination.","page":"https://instructionsets.com/arm/ssra/","api":"https://instructionsets.com/api/v1/arm/ssra.json"},{"mnemonic":"ssub16","slug":"ssub16","records":1,"summary":"Parallel sub of two signed 16-bit halfwords.","page":"https://instructionsets.com/arm/ssub16/","api":"https://instructionsets.com/api/v1/arm/ssub16.json"},{"mnemonic":"ssubl","slug":"ssubl","records":1,"summary":"Subtracts signed narrow vectors, producing wider result.","page":"https://instructionsets.com/arm/ssubl/","api":"https://instructionsets.com/api/v1/arm/ssubl.json"},{"mnemonic":"st1","slug":"st1","records":1,"summary":"Stores one element structure from 1-4 registers to memory.","page":"https://instructionsets.com/arm/st1/","api":"https://instructionsets.com/api/v1/arm/st1.json"},{"mnemonic":"st1b","slug":"st1b","records":1,"summary":"Stores active bytes from vector to memory.","page":"https://instructionsets.com/arm/st1b/","api":"https://instructionsets.com/api/v1/arm/st1b.json"},{"mnemonic":"st1d","slug":"st1d","records":1,"summary":"Stores active doublewords from vector to memory.","page":"https://instructionsets.com/arm/st1d/","api":"https://instructionsets.com/api/v1/arm/st1d.json"},{"mnemonic":"st1h","slug":"st1h","records":1,"summary":"Stores active halfwords from vector to memory.","page":"https://instructionsets.com/arm/st1h/","api":"https://instructionsets.com/api/v1/arm/st1h.json"},{"mnemonic":"st1w","slug":"st1w","records":2,"summary":"Stores active words from vector to memory.","page":"https://instructionsets.com/arm/st1w/","api":"https://instructionsets.com/api/v1/arm/st1w.json"},{"mnemonic":"st2","slug":"st2","records":1,"summary":"Stores two-element structures from two registers to memory (Interleave).","page":"https://instructionsets.com/arm/st2/","api":"https://instructionsets.com/api/v1/arm/st2.json"},{"mnemonic":"st2g","slug":"st2g","records":1,"summary":"Stores the Allocation Tag to two memory granules.","page":"https://instructionsets.com/arm/st2g/","api":"https://instructionsets.com/api/v1/arm/st2g.json"},{"mnemonic":"st3","slug":"st3","records":1,"summary":"Stores three-element structures from three registers (Interleave RGB).","page":"https://instructionsets.com/arm/st3/","api":"https://instructionsets.com/api/v1/arm/st3.json"},{"mnemonic":"st4","slug":"st4","records":1,"summary":"Stores four-element structures from four registers (Interleave RGBA).","page":"https://instructionsets.com/arm/st4/","api":"https://instructionsets.com/api/v1/arm/st4.json"},{"mnemonic":"st64b","slug":"st64b","records":1,"summary":"Stores a 64-byte block of data atomically.","page":"https://instructionsets.com/arm/st64b/","api":"https://instructionsets.com/api/v1/arm/st64b.json"},{"mnemonic":"st64bv","slug":"st64bv","records":1,"summary":"Stores 64 bytes atomically and returns status (Success/Fail).","page":"https://instructionsets.com/arm/st64bv/","api":"https://instructionsets.com/api/v1/arm/st64bv.json"},{"mnemonic":"st64bv0","slug":"st64bv0","records":1,"summary":"Stores 64 bytes (eliding the first 8 bytes as zero) and returns status.","page":"https://instructionsets.com/arm/st64bv0/","api":"https://instructionsets.com/api/v1/arm/st64bv0.json"},{"mnemonic":"stc","slug":"stc","records":1,"summary":"Stores coprocessor contents to memory.","page":"https://instructionsets.com/arm/stc/","api":"https://instructionsets.com/api/v1/arm/stc.json"},{"mnemonic":"stc2","slug":"stc2","records":1,"summary":"Stores coprocessor contents to memory (Extension encoding).","page":"https://instructionsets.com/arm/stc2/","api":"https://instructionsets.com/api/v1/arm/stc2.json"},{"mnemonic":"stg","slug":"stg","records":2,"summary":"Stores the Allocation Tag to memory.","page":"https://instructionsets.com/arm/stg/","api":"https://instructionsets.com/api/v1/arm/stg.json"},{"mnemonic":"stgp","slug":"stgp","records":1,"summary":"Stores Tag and two 64-bit data values.","page":"https://instructionsets.com/arm/stgp/","api":"https://instructionsets.com/api/v1/arm/stgp.json"},{"mnemonic":"stl","slug":"stl","records":1,"summary":"Stores a word with Release semantics.","page":"https://instructionsets.com/arm/stl/","api":"https://instructionsets.com/api/v1/arm/stl.json"},{"mnemonic":"stlex","slug":"stlex","records":1,"summary":"Stores a word with Release Exclusive semantics.","page":"https://instructionsets.com/arm/stlex/","api":"https://instructionsets.com/api/v1/arm/stlex.json"},{"mnemonic":"stlexb","slug":"stlexb","records":1,"summary":"Stores a byte with Release semantics if exclusive.","page":"https://instructionsets.com/arm/stlexb/","api":"https://instructionsets.com/api/v1/arm/stlexb.json"},{"mnemonic":"stlexd","slug":"stlexd","records":1,"summary":"Stores a doubleword with Release semantics if exclusive.","page":"https://instructionsets.com/arm/stlexd/","api":"https://instructionsets.com/api/v1/arm/stlexd.json"},{"mnemonic":"stlexh","slug":"stlexh","records":1,"summary":"Stores a halfword with Release semantics if exclusive.","page":"https://instructionsets.com/arm/stlexh/","api":"https://instructionsets.com/api/v1/arm/stlexh.json"},{"mnemonic":"stlr","slug":"stlr","records":1,"summary":"Stores a word with Release semantics.","page":"https://instructionsets.com/arm/stlr/","api":"https://instructionsets.com/api/v1/arm/stlr.json"},{"mnemonic":"stlrb","slug":"stlrb","records":1,"summary":"Stores a byte with Release semantics.","page":"https://instructionsets.com/arm/stlrb/","api":"https://instructionsets.com/api/v1/arm/stlrb.json"},{"mnemonic":"stlrh","slug":"stlrh","records":1,"summary":"Stores a halfword with Release semantics.","page":"https://instructionsets.com/arm/stlrh/","api":"https://instructionsets.com/api/v1/arm/stlrh.json"},{"mnemonic":"stlxr","slug":"stlxr","records":1,"summary":"Stores a word with Release Exclusive semantics.","page":"https://instructionsets.com/arm/stlxr/","api":"https://instructionsets.com/api/v1/arm/stlxr.json"},{"mnemonic":"stlxrb","slug":"stlxrb","records":1,"summary":"Stores a byte with Release Exclusive semantics.","page":"https://instructionsets.com/arm/stlxrb/","api":"https://instructionsets.com/api/v1/arm/stlxrb.json"},{"mnemonic":"stlxrh","slug":"stlxrh","records":1,"summary":"Stores a halfword with Release Exclusive semantics.","page":"https://instructionsets.com/arm/stlxrh/","api":"https://instructionsets.com/api/v1/arm/stlxrh.json"},{"mnemonic":"stm","slug":"stm","records":2,"summary":"Store multiple registers (Thumb 16-bit).","page":"https://instructionsets.com/arm/stm/","api":"https://instructionsets.com/api/v1/arm/stm.json"},{"mnemonic":"stm.w","slug":"stm_w","records":1,"summary":"Thumb-2 32-bit Store Multiple.","page":"https://instructionsets.com/arm/stm_w/","api":"https://instructionsets.com/api/v1/arm/stm_w.json"},{"mnemonic":"stnp","slug":"stnp","records":1,"summary":"Stores two registers, hinting non-temporal data.","page":"https://instructionsets.com/arm/stnp/","api":"https://instructionsets.com/api/v1/arm/stnp.json"},{"mnemonic":"stp","slug":"stp","records":3,"summary":"Stores two floating-point/SIMD registers.","page":"https://instructionsets.com/arm/stp/","api":"https://instructionsets.com/api/v1/arm/stp.json"},{"mnemonic":"str","slug":"str","records":4,"summary":"Stores a floating-point/SIMD register to memory.","page":"https://instructionsets.com/arm/str/","api":"https://instructionsets.com/api/v1/arm/str.json"},{"mnemonic":"str.w","slug":"str_w","records":1,"summary":"Thumb-2 32-bit Store Word.","page":"https://instructionsets.com/arm/str_w/","api":"https://instructionsets.com/api/v1/arm/str_w.json"},{"mnemonic":"strb","slug":"strb","records":2,"summary":"Stores the low byte of a register.","page":"https://instructionsets.com/arm/strb/","api":"https://instructionsets.com/api/v1/arm/strb.json"},{"mnemonic":"strb.w","slug":"strb_w","records":1,"summary":"Thumb-2 32-bit Store Byte.","page":"https://instructionsets.com/arm/strb_w/","api":"https://instructionsets.com/api/v1/arm/strb_w.json"},{"mnemonic":"strbt","slug":"strbt","records":1,"summary":"Stores a byte using User Mode permissions.","page":"https://instructionsets.com/arm/strbt/","api":"https://instructionsets.com/api/v1/arm/strbt.json"},{"mnemonic":"strd","slug":"strd","records":1,"summary":"Stores two words to memory (Thumb).","page":"https://instructionsets.com/arm/strd/","api":"https://instructionsets.com/api/v1/arm/strd.json"},{"mnemonic":"strex","slug":"strex","records":1,"summary":"Stores word if exclusive monitor is open (Thumb).","page":"https://instructionsets.com/arm/strex/","api":"https://instructionsets.com/api/v1/arm/strex.json"},{"mnemonic":"strexb","slug":"strexb","records":2,"summary":"Stores a byte if address is still exclusive.","page":"https://instructionsets.com/arm/strexb/","api":"https://instructionsets.com/api/v1/arm/strexb.json"},{"mnemonic":"strexd","slug":"strexd","records":1,"summary":"Stores a doubleword if address is still exclusive.","page":"https://instructionsets.com/arm/strexd/","api":"https://instructionsets.com/api/v1/arm/strexd.json"},{"mnemonic":"strexh","slug":"strexh","records":2,"summary":"Stores a halfword if address is still exclusive.","page":"https://instructionsets.com/arm/strexh/","api":"https://instructionsets.com/api/v1/arm/strexh.json"},{"mnemonic":"strh","slug":"strh","records":2,"summary":"Stores the low halfword of a register.","page":"https://instructionsets.com/arm/strh/","api":"https://instructionsets.com/api/v1/arm/strh.json"},{"mnemonic":"strh.w","slug":"strh_w","records":1,"summary":"Thumb-2 32-bit Store Halfword.","page":"https://instructionsets.com/arm/strh_w/","api":"https://instructionsets.com/api/v1/arm/strh_w.json"},{"mnemonic":"strht","slug":"strht","records":1,"summary":"Stores a halfword using User Mode permissions.","page":"https://instructionsets.com/arm/strht/","api":"https://instructionsets.com/api/v1/arm/strht.json"},{"mnemonic":"strt","slug":"strt","records":1,"summary":"Stores a word using User Mode permissions.","page":"https://instructionsets.com/arm/strt/","api":"https://instructionsets.com/api/v1/arm/strt.json"},{"mnemonic":"sttr","slug":"sttr","records":1,"summary":"Stores a register as if in EL0 (User mode).","page":"https://instructionsets.com/arm/sttr/","api":"https://instructionsets.com/api/v1/arm/sttr.json"},{"mnemonic":"sttrb","slug":"sttrb","records":1,"summary":"Stores a byte as if in EL0.","page":"https://instructionsets.com/arm/sttrb/","api":"https://instructionsets.com/api/v1/arm/sttrb.json"},{"mnemonic":"sttrh","slug":"sttrh","records":1,"summary":"Stores a halfword as if in EL0.","page":"https://instructionsets.com/arm/sttrh/","api":"https://instructionsets.com/api/v1/arm/sttrh.json"},{"mnemonic":"stur","slug":"stur","records":1,"summary":"Stores a register using an unscaled immediate offset.","page":"https://instructionsets.com/arm/stur/","api":"https://instructionsets.com/api/v1/arm/stur.json"},{"mnemonic":"sturb","slug":"sturb","records":1,"summary":"Stores a byte using an unscaled immediate offset.","page":"https://instructionsets.com/arm/sturb/","api":"https://instructionsets.com/api/v1/arm/sturb.json"},{"mnemonic":"sturh","slug":"sturh","records":1,"summary":"Stores a halfword using an unscaled immediate offset.","page":"https://instructionsets.com/arm/sturh/","api":"https://instructionsets.com/api/v1/arm/sturh.json"},{"mnemonic":"stxp","slug":"stxp","records":1,"summary":"Stores two registers if exclusive monitor matches.","page":"https://instructionsets.com/arm/stxp/","api":"https://instructionsets.com/api/v1/arm/stxp.json"},{"mnemonic":"stxr","slug":"stxr","records":1,"summary":"Stores a word if exclusive monitor matches.","page":"https://instructionsets.com/arm/stxr/","api":"https://instructionsets.com/api/v1/arm/stxr.json"},{"mnemonic":"stxrb","slug":"stxrb","records":1,"summary":"Stores a byte if exclusive monitor matches.","page":"https://instructionsets.com/arm/stxrb/","api":"https://instructionsets.com/api/v1/arm/stxrb.json"},{"mnemonic":"stxrh","slug":"stxrh","records":1,"summary":"Stores a halfword if exclusive monitor matches.","page":"https://instructionsets.com/arm/stxrh/","api":"https://instructionsets.com/api/v1/arm/stxrh.json"},{"mnemonic":"stz2g","slug":"stz2g","records":1,"summary":"Stores Tag and zeros memory for two granules.","page":"https://instructionsets.com/arm/stz2g/","api":"https://instructionsets.com/api/v1/arm/stz2g.json"},{"mnemonic":"stzg","slug":"stzg","records":1,"summary":"Stores the Allocation Tag and zeros the data granule.","page":"https://instructionsets.com/arm/stzg/","api":"https://instructionsets.com/api/v1/arm/stzg.json"},{"mnemonic":"sub","slug":"sub","records":6,"summary":"Subtracts extended register from register.","page":"https://instructionsets.com/arm/sub/","api":"https://instructionsets.com/api/v1/arm/sub.json"},{"mnemonic":"sub.w","slug":"sub_w","records":1,"summary":"Thumb-2 32-bit subtract.","page":"https://instructionsets.com/arm/sub_w/","api":"https://instructionsets.com/api/v1/arm/sub_w.json"},{"mnemonic":"subg","slug":"subg","records":1,"summary":"Subtracts an immediate from an address, modifying the Allocation Tag (MTE).","page":"https://instructionsets.com/arm/subg/","api":"https://instructionsets.com/api/v1/arm/subg.json"},{"mnemonic":"subp","slug":"subp","records":1,"summary":"Subtracts pointers ignoring Tags.","page":"https://instructionsets.com/arm/subp/","api":"https://instructionsets.com/api/v1/arm/subp.json"},{"mnemonic":"subps","slug":"subps","records":1,"summary":"Subtracts pointers (ignoring tags) and sets condition flags.","page":"https://instructionsets.com/arm/subps/","api":"https://instructionsets.com/api/v1/arm/subps.json"},{"mnemonic":"subs","slug":"subs","records":4,"summary":"Subtracts extended register and updates flags.","page":"https://instructionsets.com/arm/subs/","api":"https://instructionsets.com/api/v1/arm/subs.json"},{"mnemonic":"sudot","slug":"sudot","records":1,"summary":"Dot product of Signed Int8 and Unsigned Int8 (Indexed).","page":"https://instructionsets.com/arm/sudot/","api":"https://instructionsets.com/api/v1/arm/sudot.json"},{"mnemonic":"sunpkhi","slug":"sunpkhi","records":1,"summary":"Unpacks and sign-extends upper half of vector elements.","page":"https://instructionsets.com/arm/sunpkhi/","api":"https://instructionsets.com/api/v1/arm/sunpkhi.json"},{"mnemonic":"sunpklo","slug":"sunpklo","records":1,"summary":"Unpacks and sign-extends lower half of vector elements.","page":"https://instructionsets.com/arm/sunpklo/","api":"https://instructionsets.com/api/v1/arm/sunpklo.json"},{"mnemonic":"svc","slug":"svc","records":3,"summary":"Causes a Supervisor Call exception (to EL1).","page":"https://instructionsets.com/arm/svc/","api":"https://instructionsets.com/api/v1/arm/svc.json"},{"mnemonic":"swp","slug":"swp","records":2,"summary":"Atomic swap of a word.","page":"https://instructionsets.com/arm/swp/","api":"https://instructionsets.com/api/v1/arm/swp.json"},{"mnemonic":"sxtab","slug":"sxtab","records":1,"summary":"Sign-extends a byte from Rm and adds to Rn.","page":"https://instructionsets.com/arm/sxtab/","api":"https://instructionsets.com/api/v1/arm/sxtab.json"},{"mnemonic":"sxtab16","slug":"sxtab16","records":1,"summary":"Sign-extends two bytes and adds to two halfwords.","page":"https://instructionsets.com/arm/sxtab16/","api":"https://instructionsets.com/api/v1/arm/sxtab16.json"},{"mnemonic":"sxtah","slug":"sxtah","records":1,"summary":"Sign-extends a halfword and adds to Rn.","page":"https://instructionsets.com/arm/sxtah/","api":"https://instructionsets.com/api/v1/arm/sxtah.json"},{"mnemonic":"sxtb","slug":"sxtb","records":3,"summary":"Sign-extends byte to word (Thumb).","page":"https://instructionsets.com/arm/sxtb/","api":"https://instructionsets.com/api/v1/arm/sxtb.json"},{"mnemonic":"sxtb16","slug":"sxtb16","records":1,"summary":"Sign-extends two bytes to two halfwords.","page":"https://instructionsets.com/arm/sxtb16/","api":"https://instructionsets.com/api/v1/arm/sxtb16.json"},{"mnemonic":"sxth","slug":"sxth","records":2,"summary":"Sign-extends halfword to word (Thumb).","page":"https://instructionsets.com/arm/sxth/","api":"https://instructionsets.com/api/v1/arm/sxth.json"},{"mnemonic":"sxtw","slug":"sxtw","records":1,"summary":"Sign-extends a 32-bit register to 64 bits (Alias for SBFM).","page":"https://instructionsets.com/arm/sxtw/","api":"https://instructionsets.com/api/v1/arm/sxtw.json"},{"mnemonic":"sys","slug":"sys","records":1,"summary":"Executes a system instruction (cache/TLB maintenance).","page":"https://instructionsets.com/arm/sys/","api":"https://instructionsets.com/api/v1/arm/sys.json"},{"mnemonic":"tbb","slug":"tbb","records":1,"summary":"PC-relative branch using a table of bytes (Switch statements).","page":"https://instructionsets.com/arm/tbb/","api":"https://instructionsets.com/api/v1/arm/tbb.json"},{"mnemonic":"tbh","slug":"tbh","records":1,"summary":"PC-relative branch using a table of halfwords.","page":"https://instructionsets.com/arm/tbh/","api":"https://instructionsets.com/api/v1/arm/tbh.json"},{"mnemonic":"tbl","slug":"tbl","records":2,"summary":"Look up elements in a table of vectors using indices.","page":"https://instructionsets.com/arm/tbl/","api":"https://instructionsets.com/api/v1/arm/tbl.json"},{"mnemonic":"tbnz","slug":"tbnz","records":1,"summary":"Branches if specified bit is 1.","page":"https://instructionsets.com/arm/tbnz/","api":"https://instructionsets.com/api/v1/arm/tbnz.json"},{"mnemonic":"tbz","slug":"tbz","records":1,"summary":"Branches if specified bit is 0.","page":"https://instructionsets.com/arm/tbz/","api":"https://instructionsets.com/api/v1/arm/tbz.json"},{"mnemonic":"tcommit","slug":"tcommit","records":1,"summary":"Commits the current transaction.","page":"https://instructionsets.com/arm/tcommit/","api":"https://instructionsets.com/api/v1/arm/tcommit.json"},{"mnemonic":"teq","slug":"teq","records":1,"summary":"Bitwise Exclusive OR and update flags (discard result).","page":"https://instructionsets.com/arm/teq/","api":"https://instructionsets.com/api/v1/arm/teq.json"},{"mnemonic":"teq.w","slug":"teq_w","records":1,"summary":"Thumb-2 32-bit Test Equivalence (XOR and update flags).","page":"https://instructionsets.com/arm/teq_w/","api":"https://instructionsets.com/api/v1/arm/teq_w.json"},{"mnemonic":"tlbi","slug":"tlbi","records":3,"summary":"Invalidates all TLB entries in the inner shareable domain.","page":"https://instructionsets.com/arm/tlbi/","api":"https://instructionsets.com/api/v1/arm/tlbi.json"},{"mnemonic":"trcit","slug":"trcit","records":1,"summary":"Generates a trace packet.","page":"https://instructionsets.com/arm/trcit/","api":"https://instructionsets.com/api/v1/arm/trcit.json"},{"mnemonic":"trn1","slug":"trn1","records":2,"summary":"Transposes elements (Lower).","page":"https://instructionsets.com/arm/trn1/","api":"https://instructionsets.com/api/v1/arm/trn1.json"},{"mnemonic":"trn2","slug":"trn2","records":2,"summary":"Transposes elements (Upper).","page":"https://instructionsets.com/arm/trn2/","api":"https://instructionsets.com/api/v1/arm/trn2.json"},{"mnemonic":"tsb","slug":"tsb","records":2,"summary":"Ensures trace generation is complete (v8.2).","page":"https://instructionsets.com/arm/tsb/","api":"https://instructionsets.com/api/v1/arm/tsb.json"},{"mnemonic":"tst","slug":"tst","records":1,"summary":"Bitwise AND and update flags (discard result).","page":"https://instructionsets.com/arm/tst/","api":"https://instructionsets.com/api/v1/arm/tst.json"},{"mnemonic":"tst.w","slug":"tst_w","records":1,"summary":"Thumb-2 32-bit Test (AND and update flags).","page":"https://instructionsets.com/arm/tst_w/","api":"https://instructionsets.com/api/v1/arm/tst_w.json"},{"mnemonic":"tstart","slug":"tstart","records":1,"summary":"Starts a memory transaction. Returns 0 if successful.","page":"https://instructionsets.com/arm/tstart/","api":"https://instructionsets.com/api/v1/arm/tstart.json"},{"mnemonic":"ttest","slug":"ttest","records":1,"summary":"Tests the transaction nesting depth.","page":"https://instructionsets.com/arm/ttest/","api":"https://instructionsets.com/api/v1/arm/ttest.json"},{"mnemonic":"uadd16","slug":"uadd16","records":1,"summary":"Parallel add of two unsigned 16-bit halfwords.","page":"https://instructionsets.com/arm/uadd16/","api":"https://instructionsets.com/api/v1/arm/uadd16.json"},{"mnemonic":"uadd8","slug":"uadd8","records":1,"summary":"Parallel add of four unsigned 8-bit bytes.","page":"https://instructionsets.com/arm/uadd8/","api":"https://instructionsets.com/api/v1/arm/uadd8.json"},{"mnemonic":"uaddl","slug":"uaddl","records":1,"summary":"Adds lower/upper halves of unsigned vectors, producing wider result.","page":"https://instructionsets.com/arm/uaddl/","api":"https://instructionsets.com/api/v1/arm/uaddl.json"},{"mnemonic":"uaddv","slug":"uaddv","records":1,"summary":"Sums all active unsigned elements into a scalar result.","page":"https://instructionsets.com/arm/uaddv/","api":"https://instructionsets.com/api/v1/arm/uaddv.json"},{"mnemonic":"uaddw","slug":"uaddw","records":1,"summary":"Adds a wide vector to the lower/upper half of a narrow vector (Unsigned).","page":"https://instructionsets.com/arm/uaddw/","api":"https://instructionsets.com/api/v1/arm/uaddw.json"},{"mnemonic":"ubfm","slug":"ubfm","records":1,"summary":"Extracts/Inserts bitfield (Zero Extend).","page":"https://instructionsets.com/arm/ubfm/","api":"https://instructionsets.com/api/v1/arm/ubfm.json"},{"mnemonic":"ubfx","slug":"ubfx","records":2,"summary":"Extracts bits from a register and zero-extends them.","page":"https://instructionsets.com/arm/ubfx/","api":"https://instructionsets.com/api/v1/arm/ubfx.json"},{"mnemonic":"ucvtf","slug":"ucvtf","records":2,"summary":"Converts unsigned integers to floats.","page":"https://instructionsets.com/arm/ucvtf/","api":"https://instructionsets.com/api/v1/arm/ucvtf.json"},{"mnemonic":"udf","slug":"udf","records":2,"summary":"Permanently undefined instruction (generates Undefined Instruction exception).","page":"https://instructionsets.com/arm/udf/","api":"https://instructionsets.com/api/v1/arm/udf.json"},{"mnemonic":"udiv","slug":"udiv","records":4,"summary":"Divides unsigned integers.","page":"https://instructionsets.com/arm/udiv/","api":"https://instructionsets.com/api/v1/arm/udiv.json"},{"mnemonic":"udot","slug":"udot","records":4,"summary":"Computes dot product of unsigned integers.","page":"https://instructionsets.com/arm/udot/","api":"https://instructionsets.com/api/v1/arm/udot.json"},{"mnemonic":"uhadd16","slug":"uhadd16","records":1,"summary":"Unsigned average of 2 halfwords.","page":"https://instructionsets.com/arm/uhadd16/","api":"https://instructionsets.com/api/v1/arm/uhadd16.json"},{"mnemonic":"uhadd8","slug":"uhadd8","records":1,"summary":"Unsigned average of 4 bytes.","page":"https://instructionsets.com/arm/uhadd8/","api":"https://instructionsets.com/api/v1/arm/uhadd8.json"},{"mnemonic":"uhsub16","slug":"uhsub16","records":1,"summary":"Unsigned halving subtract of 2 halfwords.","page":"https://instructionsets.com/arm/uhsub16/","api":"https://instructionsets.com/api/v1/arm/uhsub16.json"},{"mnemonic":"uhsub8","slug":"uhsub8","records":1,"summary":"Unsigned halving subtract of 4 bytes.","page":"https://instructionsets.com/arm/uhsub8/","api":"https://instructionsets.com/api/v1/arm/uhsub8.json"},{"mnemonic":"umaal","slug":"umaal","records":1,"summary":"Calculates (Rn * Rm) + RdLo + RdHi -> 64-bit result.","page":"https://instructionsets.com/arm/umaal/","api":"https://instructionsets.com/api/v1/arm/umaal.json"},{"mnemonic":"umaddl","slug":"umaddl","records":1,"summary":"Multiplies two 32-bit regs, adds to 64-bit reg (Unsigned).","page":"https://instructionsets.com/arm/umaddl/","api":"https://instructionsets.com/api/v1/arm/umaddl.json"},{"mnemonic":"umax","slug":"umax","records":2,"summary":"Determines maximum unsigned value per element.","page":"https://instructionsets.com/arm/umax/","api":"https://instructionsets.com/api/v1/arm/umax.json"},{"mnemonic":"umaxv","slug":"umaxv","records":1,"summary":"Finds max unsigned element in vector.","page":"https://instructionsets.com/arm/umaxv/","api":"https://instructionsets.com/api/v1/arm/umaxv.json"},{"mnemonic":"umin","slug":"umin","records":2,"summary":"Determines minimum unsigned value per element.","page":"https://instructionsets.com/arm/umin/","api":"https://instructionsets.com/api/v1/arm/umin.json"},{"mnemonic":"uminv","slug":"uminv","records":2,"summary":"Finds min unsigned element in vector.","page":"https://instructionsets.com/arm/uminv/","api":"https://instructionsets.com/api/v1/arm/uminv.json"},{"mnemonic":"umlal","slug":"umlal","records":3,"summary":"Unsigned Multiply Accumulate (64-bit result).","page":"https://instructionsets.com/arm/umlal/","api":"https://instructionsets.com/api/v1/arm/umlal.json"},{"mnemonic":"ummla","slug":"ummla","records":1,"summary":"Performs 2x2 matrix multiplication on Unsigned Int8 tiles.","page":"https://instructionsets.com/arm/ummla/","api":"https://instructionsets.com/api/v1/arm/ummla.json"},{"mnemonic":"umsubl","slug":"umsubl","records":1,"summary":"Calculates (Xa - (Wn * Wm)) (Unsigned 64-bit).","page":"https://instructionsets.com/arm/umsubl/","api":"https://instructionsets.com/api/v1/arm/umsubl.json"},{"mnemonic":"umulh","slug":"umulh","records":1,"summary":"Multiplies two 64-bit registers, keeps high 64 bits (Unsigned).","page":"https://instructionsets.com/arm/umulh/","api":"https://instructionsets.com/api/v1/arm/umulh.json"},{"mnemonic":"umull","slug":"umull","records":3,"summary":"Unsigned Multiply (64-bit result).","page":"https://instructionsets.com/arm/umull/","api":"https://instructionsets.com/api/v1/arm/umull.json"},{"mnemonic":"uqadd","slug":"uqadd","records":1,"summary":"Adds unsigned integers with saturation.","page":"https://instructionsets.com/arm/uqadd/","api":"https://instructionsets.com/api/v1/arm/uqadd.json"},{"mnemonic":"uqadd16","slug":"uqadd16","records":1,"summary":"Unsigned saturating add of 2 halfwords.","page":"https://instructionsets.com/arm/uqadd16/","api":"https://instructionsets.com/api/v1/arm/uqadd16.json"},{"mnemonic":"uqadd8","slug":"uqadd8","records":1,"summary":"Unsigned saturating add of 4 bytes.","page":"https://instructionsets.com/arm/uqadd8/","api":"https://instructionsets.com/api/v1/arm/uqadd8.json"},{"mnemonic":"uqsub","slug":"uqsub","records":1,"summary":"Subtracts unsigned integers with saturation.","page":"https://instructionsets.com/arm/uqsub/","api":"https://instructionsets.com/api/v1/arm/uqsub.json"},{"mnemonic":"uqsub16","slug":"uqsub16","records":1,"summary":"Unsigned saturating subtract of 2 halfwords.","page":"https://instructionsets.com/arm/uqsub16/","api":"https://instructionsets.com/api/v1/arm/uqsub16.json"},{"mnemonic":"uqsub8","slug":"uqsub8","records":1,"summary":"Unsigned saturating subtract of 4 bytes.","page":"https://instructionsets.com/arm/uqsub8/","api":"https://instructionsets.com/api/v1/arm/uqsub8.json"},{"mnemonic":"uqxtn","slug":"uqxtn","records":1,"summary":"Reads wide unsigned elements, saturates, and narrows.","page":"https://instructionsets.com/arm/uqxtn/","api":"https://instructionsets.com/api/v1/arm/uqxtn.json"},{"mnemonic":"urecpe","slug":"urecpe","records":1,"summary":"Estimates reciprocal for unsigned integers.","page":"https://instructionsets.com/arm/urecpe/","api":"https://instructionsets.com/api/v1/arm/urecpe.json"},{"mnemonic":"usad8","slug":"usad8","records":1,"summary":"Computes sum of absolute differences of bytes (Video Codec).","page":"https://instructionsets.com/arm/usad8/","api":"https://instructionsets.com/api/v1/arm/usad8.json"},{"mnemonic":"usada8","slug":"usada8","records":1,"summary":"USAD8 plus accumulator.","page":"https://instructionsets.com/arm/usada8/","api":"https://instructionsets.com/api/v1/arm/usada8.json"},{"mnemonic":"usat","slug":"usat","records":1,"summary":"Saturates an unsigned value to a specified bit width.","page":"https://instructionsets.com/arm/usat/","api":"https://instructionsets.com/api/v1/arm/usat.json"},{"mnemonic":"usat16","slug":"usat16","records":1,"summary":"Saturates two unsigned 16-bit values.","page":"https://instructionsets.com/arm/usat16/","api":"https://instructionsets.com/api/v1/arm/usat16.json"},{"mnemonic":"usdot","slug":"usdot","records":2,"summary":"Dot product of unsigned and signed integers.","page":"https://instructionsets.com/arm/usdot/","api":"https://instructionsets.com/api/v1/arm/usdot.json"},{"mnemonic":"ushr","slug":"ushr","records":1,"summary":"Shifts elements right (logical).","page":"https://instructionsets.com/arm/ushr/","api":"https://instructionsets.com/api/v1/arm/ushr.json"},{"mnemonic":"usmmla","slug":"usmmla","records":1,"summary":"Matrix multiply Unsigned Int8 with Signed Int8.","page":"https://instructionsets.com/arm/usmmla/","api":"https://instructionsets.com/api/v1/arm/usmmla.json"},{"mnemonic":"usra","slug":"usra","records":1,"summary":"Logical right shift and add to destination.","page":"https://instructionsets.com/arm/usra/","api":"https://instructionsets.com/api/v1/arm/usra.json"},{"mnemonic":"usub16","slug":"usub16","records":1,"summary":"Parallel sub of two unsigned 16-bit halfwords.","page":"https://instructionsets.com/arm/usub16/","api":"https://instructionsets.com/api/v1/arm/usub16.json"},{"mnemonic":"usubl","slug":"usubl","records":1,"summary":"Subtracts unsigned narrow vectors, producing wider result.","page":"https://instructionsets.com/arm/usubl/","api":"https://instructionsets.com/api/v1/arm/usubl.json"},{"mnemonic":"uunpkhi","slug":"uunpkhi","records":1,"summary":"Unpacks and zero-extends upper half of vector elements.","page":"https://instructionsets.com/arm/uunpkhi/","api":"https://instructionsets.com/api/v1/arm/uunpkhi.json"},{"mnemonic":"uunpklo","slug":"uunpklo","records":1,"summary":"Unpacks and zero-extends lower half of vector elements.","page":"https://instructionsets.com/arm/uunpklo/","api":"https://instructionsets.com/api/v1/arm/uunpklo.json"},{"mnemonic":"uxtab","slug":"uxtab","records":1,"summary":"Zero-extends a byte and adds to Rn.","page":"https://instructionsets.com/arm/uxtab/","api":"https://instructionsets.com/api/v1/arm/uxtab.json"},{"mnemonic":"uxtab16","slug":"uxtab16","records":1,"summary":"Zero-extends two bytes and adds to two halfwords.","page":"https://instructionsets.com/arm/uxtab16/","api":"https://instructionsets.com/api/v1/arm/uxtab16.json"},{"mnemonic":"uxtah","slug":"uxtah","records":1,"summary":"Zero-extends a halfword and adds to Rn.","page":"https://instructionsets.com/arm/uxtah/","api":"https://instructionsets.com/api/v1/arm/uxtah.json"},{"mnemonic":"uxtb","slug":"uxtb","records":2,"summary":"Zero-extends byte to word (Thumb).","page":"https://instructionsets.com/arm/uxtb/","api":"https://instructionsets.com/api/v1/arm/uxtb.json"},{"mnemonic":"uxtb16","slug":"uxtb16","records":1,"summary":"Zero-extends two bytes to two halfwords.","page":"https://instructionsets.com/arm/uxtb16/","api":"https://instructionsets.com/api/v1/arm/uxtb16.json"},{"mnemonic":"uxth","slug":"uxth","records":2,"summary":"Zero-extends halfword to word (Thumb).","page":"https://instructionsets.com/arm/uxth/","api":"https://instructionsets.com/api/v1/arm/uxth.json"},{"mnemonic":"uzp1","slug":"uzp1","records":2,"summary":"De-interleaves lower halves (Selects odd elements).","page":"https://instructionsets.com/arm/uzp1/","api":"https://instructionsets.com/api/v1/arm/uzp1.json"},{"mnemonic":"uzp2","slug":"uzp2","records":2,"summary":"De-interleaves upper halves (Selects even elements).","page":"https://instructionsets.com/arm/uzp2/","api":"https://instructionsets.com/api/v1/arm/uzp2.json"},{"mnemonic":"vaba","slug":"vaba","records":1,"summary":"Computes absolute difference and adds to accumulator.","page":"https://instructionsets.com/arm/vaba/","api":"https://instructionsets.com/api/v1/arm/vaba.json"},{"mnemonic":"vabal","slug":"vabal","records":1,"summary":"Computes absolute difference of narrow elements and adds to wide acc.","page":"https://instructionsets.com/arm/vabal/","api":"https://instructionsets.com/api/v1/arm/vabal.json"},{"mnemonic":"vabd","slug":"vabd","records":1,"summary":"Computes absolute difference between elements.","page":"https://instructionsets.com/arm/vabd/","api":"https://instructionsets.com/api/v1/arm/vabd.json"},{"mnemonic":"vabdl","slug":"vabdl","records":1,"summary":"Computes absolute difference of narrow elements to wide result.","page":"https://instructionsets.com/arm/vabdl/","api":"https://instructionsets.com/api/v1/arm/vabdl.json"},{"mnemonic":"vabs","slug":"vabs","records":3,"summary":"Absolute value of double-precision register.","page":"https://instructionsets.com/arm/vabs/","api":"https://instructionsets.com/api/v1/arm/vabs.json"},{"mnemonic":"vacge","slug":"vacge","records":1,"summary":"Compares absolute values (|Vn| >= |Vm|).","page":"https://instructionsets.com/arm/vacge/","api":"https://instructionsets.com/api/v1/arm/vacge.json"},{"mnemonic":"vacgt","slug":"vacgt","records":1,"summary":"Compares absolute values (|Vn| > |Vm|).","page":"https://instructionsets.com/arm/vacgt/","api":"https://instructionsets.com/api/v1/arm/vacgt.json"},{"mnemonic":"vadd","slug":"vadd","records":3,"summary":"Adds two floating-point values.","page":"https://instructionsets.com/arm/vadd/","api":"https://instructionsets.com/api/v1/arm/vadd.json"},{"mnemonic":"vaddhn","slug":"vaddhn","records":1,"summary":"Adds 2N-bit elements, selects high N-bits for result.","page":"https://instructionsets.com/arm/vaddhn/","api":"https://instructionsets.com/api/v1/arm/vaddhn.json"},{"mnemonic":"vaddl","slug":"vaddl","records":1,"summary":"Adds N-bit elements, producing 2N-bit results.","page":"https://instructionsets.com/arm/vaddl/","api":"https://instructionsets.com/api/v1/arm/vaddl.json"},{"mnemonic":"vaddw","slug":"vaddw","records":1,"summary":"Adds N-bit vector to 2N-bit vector.","page":"https://instructionsets.com/arm/vaddw/","api":"https://instructionsets.com/api/v1/arm/vaddw.json"},{"mnemonic":"vand","slug":"vand","records":1,"summary":"Bitwise AND of two vectors.","page":"https://instructionsets.com/arm/vand/","api":"https://instructionsets.com/api/v1/arm/vand.json"},{"mnemonic":"vbfcvt","slug":"vbfcvt","records":1,"summary":"Converts Float32 to BFloat16.","page":"https://instructionsets.com/arm/vbfcvt/","api":"https://instructionsets.com/api/v1/arm/vbfcvt.json"},{"mnemonic":"vbfmmla","slug":"vbfmmla","records":1,"summary":"BFloat16 matrix multiply-accumulate.","page":"https://instructionsets.com/arm/vbfmmla/","api":"https://instructionsets.com/api/v1/arm/vbfmmla.json"},{"mnemonic":"vbic","slug":"vbic","records":1,"summary":"ANDs Vd with NOT of Vm (Vd & ~Vm).","page":"https://instructionsets.com/arm/vbic/","api":"https://instructionsets.com/api/v1/arm/vbic.json"},{"mnemonic":"vbif","slug":"vbif","records":1,"summary":"Inserts bits from Vm into Vd where Vn (mask) is 0.","page":"https://instructionsets.com/arm/vbif/","api":"https://instructionsets.com/api/v1/arm/vbif.json"},{"mnemonic":"vbit","slug":"vbit","records":1,"summary":"Inserts bits from Vm into Vd where Vn (mask) is 1.","page":"https://instructionsets.com/arm/vbit/","api":"https://instructionsets.com/api/v1/arm/vbit.json"},{"mnemonic":"vbsl","slug":"vbsl","records":1,"summary":"Selects bits from Vn or Vm based on Vd (mask).","page":"https://instructionsets.com/arm/vbsl/","api":"https://instructionsets.com/api/v1/arm/vbsl.json"},{"mnemonic":"vcadd","slug":"vcadd","records":1,"summary":"Complex integer addition with rotation (NEON).","page":"https://instructionsets.com/arm/vcadd/","api":"https://instructionsets.com/api/v1/arm/vcadd.json"},{"mnemonic":"vceq","slug":"vceq","records":1,"summary":"Sets destination bits to all 1s if elements equal, else 0s.","page":"https://instructionsets.com/arm/vceq/","api":"https://instructionsets.com/api/v1/arm/vceq.json"},{"mnemonic":"vcge","slug":"vcge","records":1,"summary":"Compares elements (>=) and sets result mask.","page":"https://instructionsets.com/arm/vcge/","api":"https://instructionsets.com/api/v1/arm/vcge.json"},{"mnemonic":"vcgt","slug":"vcgt","records":1,"summary":"Compares elements (>) and sets result mask.","page":"https://instructionsets.com/arm/vcgt/","api":"https://instructionsets.com/api/v1/arm/vcgt.json"},{"mnemonic":"vcle","slug":"vcle","records":1,"summary":"Compares elements (<=). Alias for VCGE with swapped operands.","page":"https://instructionsets.com/arm/vcle/","api":"https://instructionsets.com/api/v1/arm/vcle.json"},{"mnemonic":"vcls","slug":"vcls","records":1,"summary":"Counts number of consecutive sign bits.","page":"https://instructionsets.com/arm/vcls/","api":"https://instructionsets.com/api/v1/arm/vcls.json"},{"mnemonic":"vclt","slug":"vclt","records":1,"summary":"Compares elements (<). Alias for VCGT with swapped operands.","page":"https://instructionsets.com/arm/vclt/","api":"https://instructionsets.com/api/v1/arm/vclt.json"},{"mnemonic":"vclz","slug":"vclz","records":1,"summary":"Counts number of consecutive zeros.","page":"https://instructionsets.com/arm/vclz/","api":"https://instructionsets.com/api/v1/arm/vclz.json"},{"mnemonic":"vcmla","slug":"vcmla","records":1,"summary":"Complex integer multiply-accumulate with rotation.","page":"https://instructionsets.com/arm/vcmla/","api":"https://instructionsets.com/api/v1/arm/vcmla.json"},{"mnemonic":"vcmp","slug":"vcmp","records":3,"summary":"Compares a floating-point value with #0.0.","page":"https://instructionsets.com/arm/vcmp/","api":"https://instructionsets.com/api/v1/arm/vcmp.json"},{"mnemonic":"vcmpe","slug":"vcmpe","records":1,"summary":"Compares values and raises exception on NaN.","page":"https://instructionsets.com/arm/vcmpe/","api":"https://instructionsets.com/api/v1/arm/vcmpe.json"},{"mnemonic":"vcnt","slug":"vcnt","records":1,"summary":"Population count (number of 1s) per byte.","page":"https://instructionsets.com/arm/vcnt/","api":"https://instructionsets.com/api/v1/arm/vcnt.json"},{"mnemonic":"vcvt","slug":"vcvt","records":2,"summary":"Converts between floating-point and fixed-point.","page":"https://instructionsets.com/arm/vcvt/","api":"https://instructionsets.com/api/v1/arm/vcvt.json"},{"mnemonic":"vcvta","slug":"vcvta","records":2,"summary":"Converts double to integer, rounding to nearest.","page":"https://instructionsets.com/arm/vcvta/","api":"https://instructionsets.com/api/v1/arm/vcvta.json"},{"mnemonic":"vcvtb","slug":"vcvtb","records":1,"summary":"Converts single-precision to half-precision (Bottom half).","page":"https://instructionsets.com/arm/vcvtb/","api":"https://instructionsets.com/api/v1/arm/vcvtb.json"},{"mnemonic":"vcvtm","slug":"vcvtm","records":1,"summary":"Converts float to integer, rounding towards -Inf (Floor).","page":"https://instructionsets.com/arm/vcvtm/","api":"https://instructionsets.com/api/v1/arm/vcvtm.json"},{"mnemonic":"vcvtn","slug":"vcvtn","records":2,"summary":"Converts double to integer, rounding to nearest even.","page":"https://instructionsets.com/arm/vcvtn/","api":"https://instructionsets.com/api/v1/arm/vcvtn.json"},{"mnemonic":"vcvtp","slug":"vcvtp","records":1,"summary":"Converts float to integer, rounding towards +Inf (Ceil).","page":"https://instructionsets.com/arm/vcvtp/","api":"https://instructionsets.com/api/v1/arm/vcvtp.json"},{"mnemonic":"vcvtt","slug":"vcvtt","records":1,"summary":"Converts single-precision to half-precision (Top half).","page":"https://instructionsets.com/arm/vcvtt/","api":"https://instructionsets.com/api/v1/arm/vcvtt.json"},{"mnemonic":"vdiv","slug":"vdiv","records":2,"summary":"Divides two double-precision registers.","page":"https://instructionsets.com/arm/vdiv/","api":"https://instructionsets.com/api/v1/arm/vdiv.json"},{"mnemonic":"vdot","slug":"vdot","records":1,"summary":"BFloat16 dot product to float32 accumulator.","page":"https://instructionsets.com/arm/vdot/","api":"https://instructionsets.com/api/v1/arm/vdot.json"},{"mnemonic":"vdup","slug":"vdup","records":1,"summary":"Duplicates a scalar value to all lanes of a vector.","page":"https://instructionsets.com/arm/vdup/","api":"https://instructionsets.com/api/v1/arm/vdup.json"},{"mnemonic":"veor","slug":"veor","records":1,"summary":"Bitwise XOR of two vectors.","page":"https://instructionsets.com/arm/veor/","api":"https://instructionsets.com/api/v1/arm/veor.json"},{"mnemonic":"vext","slug":"vext","records":1,"summary":"Extracts a new vector from a pair of vectors (Sliding window).","page":"https://instructionsets.com/arm/vext/","api":"https://instructionsets.com/api/v1/arm/vext.json"},{"mnemonic":"vfma","slug":"vfma","records":2,"summary":"Fused multiply-add (Double).","page":"https://instructionsets.com/arm/vfma/","api":"https://instructionsets.com/api/v1/arm/vfma.json"},{"mnemonic":"vfms","slug":"vfms","records":2,"summary":"Fused multiply-subtract (Double).","page":"https://instructionsets.com/arm/vfms/","api":"https://instructionsets.com/api/v1/arm/vfms.json"},{"mnemonic":"vfnma","slug":"vfnma","records":1,"summary":"Computes Vd = Vd - (Vn * Vm).","page":"https://instructionsets.com/arm/vfnma/","api":"https://instructionsets.com/api/v1/arm/vfnma.json"},{"mnemonic":"vfnms","slug":"vfnms","records":1,"summary":"Computes Vd = -Vd + (Vn * Vm).","page":"https://instructionsets.com/arm/vfnms/","api":"https://instructionsets.com/api/v1/arm/vfnms.json"},{"mnemonic":"vhadd","slug":"vhadd","records":1,"summary":"Add elements and shift right by 1 (Average).","page":"https://instructionsets.com/arm/vhadd/","api":"https://instructionsets.com/api/v1/arm/vhadd.json"},{"mnemonic":"vhsub","slug":"vhsub","records":1,"summary":"Subtract elements and shift right by 1.","page":"https://instructionsets.com/arm/vhsub/","api":"https://instructionsets.com/api/v1/arm/vhsub.json"},{"mnemonic":"vjcvt","slug":"vjcvt","records":1,"summary":"Converts double to signed 32-bit integer (JS semantics).","page":"https://instructionsets.com/arm/vjcvt/","api":"https://instructionsets.com/api/v1/arm/vjcvt.json"},{"mnemonic":"vld1","slug":"vld1","records":1,"summary":"Loads vector data from memory (interleaved or sequential).","page":"https://instructionsets.com/arm/vld1/","api":"https://instructionsets.com/api/v1/arm/vld1.json"},{"mnemonic":"vld2","slug":"vld2","records":1,"summary":"De-interleaves 2 streams of data while loading.","page":"https://instructionsets.com/arm/vld2/","api":"https://instructionsets.com/api/v1/arm/vld2.json"},{"mnemonic":"vld3","slug":"vld3","records":1,"summary":"Loads three-element structures (e.g., RGB) and de-interleaves them into three registers.","page":"https://instructionsets.com/arm/vld3/","api":"https://instructionsets.com/api/v1/arm/vld3.json"},{"mnemonic":"vld4","slug":"vld4","records":1,"summary":"Loads four-element structures (e.g., RGBA) and de-interleaves them into four registers.","page":"https://instructionsets.com/arm/vld4/","api":"https://instructionsets.com/api/v1/arm/vld4.json"},{"mnemonic":"vldm","slug":"vldm","records":1,"summary":"Loads multiple VFP registers from memory.","page":"https://instructionsets.com/arm/vldm/","api":"https://instructionsets.com/api/v1/arm/vldm.json"},{"mnemonic":"vldr","slug":"vldr","records":1,"summary":"Loads a floating-point register from memory.","page":"https://instructionsets.com/arm/vldr/","api":"https://instructionsets.com/api/v1/arm/vldr.json"},{"mnemonic":"vmax","slug":"vmax","records":1,"summary":"Selects maximum value from elements.","page":"https://instructionsets.com/arm/vmax/","api":"https://instructionsets.com/api/v1/arm/vmax.json"},{"mnemonic":"vmaxnm","slug":"vmaxnm","records":2,"summary":"Returns larger value, handling NaNs per IEEE 754-2008.","page":"https://instructionsets.com/arm/vmaxnm/","api":"https://instructionsets.com/api/v1/arm/vmaxnm.json"},{"mnemonic":"vmin","slug":"vmin","records":1,"summary":"Selects minimum value from elements.","page":"https://instructionsets.com/arm/vmin/","api":"https://instructionsets.com/api/v1/arm/vmin.json"},{"mnemonic":"vminnm","slug":"vminnm","records":2,"summary":"Returns smaller value, handling NaNs per IEEE 754-2008.","page":"https://instructionsets.com/arm/vminnm/","api":"https://instructionsets.com/api/v1/arm/vminnm.json"},{"mnemonic":"vmla","slug":"vmla","records":2,"summary":"Sd = Sd + (Sn * Sm).","page":"https://instructionsets.com/arm/vmla/","api":"https://instructionsets.com/api/v1/arm/vmla.json"},{"mnemonic":"vmls","slug":"vmls","records":2,"summary":"Sd = Sd - (Sn * Sm).","page":"https://instructionsets.com/arm/vmls/","api":"https://instructionsets.com/api/v1/arm/vmls.json"},{"mnemonic":"vmmla","slug":"vmmla","records":1,"summary":"Matrix multiply-accumulate (BFloat16/Int8).","page":"https://instructionsets.com/arm/vmmla/","api":"https://instructionsets.com/api/v1/arm/vmmla.json"},{"mnemonic":"vmov","slug":"vmov","records":5,"summary":"Moves data between Double registers.","page":"https://instructionsets.com/arm/vmov/","api":"https://instructionsets.com/api/v1/arm/vmov.json"},{"mnemonic":"vmovl","slug":"vmovl","records":1,"summary":"Copies N-bit elements to 2N-bit elements (Widening).","page":"https://instructionsets.com/arm/vmovl/","api":"https://instructionsets.com/api/v1/arm/vmovl.json"},{"mnemonic":"vmovn","slug":"vmovn","records":1,"summary":"Copies 2N-bit elements to N-bit elements (Narrowing).","page":"https://instructionsets.com/arm/vmovn/","api":"https://instructionsets.com/api/v1/arm/vmovn.json"},{"mnemonic":"vmrs","slug":"vmrs","records":1,"summary":"Reads a VFP system register (like FPSCR).","page":"https://instructionsets.com/arm/vmrs/","api":"https://instructionsets.com/api/v1/arm/vmrs.json"},{"mnemonic":"vmsr","slug":"vmsr","records":1,"summary":"Writes to a VFP system register.","page":"https://instructionsets.com/arm/vmsr/","api":"https://instructionsets.com/api/v1/arm/vmsr.json"},{"mnemonic":"vmul","slug":"vmul","records":2,"summary":"Multiplies two floating-point values.","page":"https://instructionsets.com/arm/vmul/","api":"https://instructionsets.com/api/v1/arm/vmul.json"},{"mnemonic":"vmull","slug":"vmull","records":1,"summary":"Multiplies N-bit elements producing 2N-bit results.","page":"https://instructionsets.com/arm/vmull/","api":"https://instructionsets.com/api/v1/arm/vmull.json"},{"mnemonic":"vmvn","slug":"vmvn","records":1,"summary":"Moves bitwise inverse of immediate/register.","page":"https://instructionsets.com/arm/vmvn/","api":"https://instructionsets.com/api/v1/arm/vmvn.json"},{"mnemonic":"vneg","slug":"vneg","records":3,"summary":"Negates double-precision register.","page":"https://instructionsets.com/arm/vneg/","api":"https://instructionsets.com/api/v1/arm/vneg.json"},{"mnemonic":"vnmul","slug":"vnmul","records":1,"summary":"Sd = -(Sn * Sm).","page":"https://instructionsets.com/arm/vnmul/","api":"https://instructionsets.com/api/v1/arm/vnmul.json"},{"mnemonic":"vorn","slug":"vorn","records":1,"summary":"Bitwise OR with NOT (Vd = Vn | ~Vm).","page":"https://instructionsets.com/arm/vorn/","api":"https://instructionsets.com/api/v1/arm/vorn.json"},{"mnemonic":"vorr","slug":"vorr","records":1,"summary":"Bitwise OR of two vectors.","page":"https://instructionsets.com/arm/vorr/","api":"https://instructionsets.com/api/v1/arm/vorr.json"},{"mnemonic":"vpadal","slug":"vpadal","records":1,"summary":"Adds adjacent pairs and accumulates into wide destination.","page":"https://instructionsets.com/arm/vpadal/","api":"https://instructionsets.com/api/v1/arm/vpadal.json"},{"mnemonic":"vpadd","slug":"vpadd","records":1,"summary":"Adds adjacent pairs of elements.","page":"https://instructionsets.com/arm/vpadd/","api":"https://instructionsets.com/api/v1/arm/vpadd.json"},{"mnemonic":"vpaddl","slug":"vpaddl","records":1,"summary":"Adds adjacent pairs and produces wide result.","page":"https://instructionsets.com/arm/vpaddl/","api":"https://instructionsets.com/api/v1/arm/vpaddl.json"},{"mnemonic":"vpmax","slug":"vpmax","records":1,"summary":"Maximum of adjacent pairs.","page":"https://instructionsets.com/arm/vpmax/","api":"https://instructionsets.com/api/v1/arm/vpmax.json"},{"mnemonic":"vpmin","slug":"vpmin","records":1,"summary":"Minimum of adjacent pairs.","page":"https://instructionsets.com/arm/vpmin/","api":"https://instructionsets.com/api/v1/arm/vpmin.json"},{"mnemonic":"vpop","slug":"vpop","records":1,"summary":"Pops VFP registers from the stack (Alias for VLDMIA SP!).","page":"https://instructionsets.com/arm/vpop/","api":"https://instructionsets.com/api/v1/arm/vpop.json"},{"mnemonic":"vpush","slug":"vpush","records":1,"summary":"Pushes VFP registers to the stack (Alias for VSTMDB SP!).","page":"https://instructionsets.com/arm/vpush/","api":"https://instructionsets.com/api/v1/arm/vpush.json"},{"mnemonic":"vqadd","slug":"vqadd","records":1,"summary":"Adds elements with saturation.","page":"https://instructionsets.com/arm/vqadd/","api":"https://instructionsets.com/api/v1/arm/vqadd.json"},{"mnemonic":"vqdmlal","slug":"vqdmlal","records":1,"summary":"Multiplies, doubles, saturates, and adds to accumulator (High precision DSP).","page":"https://instructionsets.com/arm/vqdmlal/","api":"https://instructionsets.com/api/v1/arm/vqdmlal.json"},{"mnemonic":"vqdmlsl","slug":"vqdmlsl","records":1,"summary":"Multiplies, doubles, saturates, and subtracts from accumulator.","page":"https://instructionsets.com/arm/vqdmlsl/","api":"https://instructionsets.com/api/v1/arm/vqdmlsl.json"},{"mnemonic":"vqdmulh","slug":"vqdmulh","records":1,"summary":"Multiplies, doubles, saturates, and keeps high half.","page":"https://instructionsets.com/arm/vqdmulh/","api":"https://instructionsets.com/api/v1/arm/vqdmulh.json"},{"mnemonic":"vqdmull","slug":"vqdmull","records":1,"summary":"Multiplies narrow elements, doubles, and saturates into wide elements.","page":"https://instructionsets.com/arm/vqdmull/","api":"https://instructionsets.com/api/v1/arm/vqdmull.json"},{"mnemonic":"vqrdmulh","slug":"vqrdmulh","records":1,"summary":"Fixed-point multiply with rounding and saturation.","page":"https://instructionsets.com/arm/vqrdmulh/","api":"https://instructionsets.com/api/v1/arm/vqrdmulh.json"},{"mnemonic":"vqrshl","slug":"vqrshl","records":1,"summary":"Shifts left with saturation and rounding.","page":"https://instructionsets.com/arm/vqrshl/","api":"https://instructionsets.com/api/v1/arm/vqrshl.json"},{"mnemonic":"vqrshrn","slug":"vqrshrn","records":1,"summary":"Shifts right, saturates, rounds, and narrows.","page":"https://instructionsets.com/arm/vqrshrn/","api":"https://instructionsets.com/api/v1/arm/vqrshrn.json"},{"mnemonic":"vqshl","slug":"vqshl","records":2,"summary":"Shifts left with saturation based on register.","page":"https://instructionsets.com/arm/vqshl/","api":"https://instructionsets.com/api/v1/arm/vqshl.json"},{"mnemonic":"vqshlu","slug":"vqshlu","records":1,"summary":"Shifts signed elements left, saturating to unsigned result.","page":"https://instructionsets.com/arm/vqshlu/","api":"https://instructionsets.com/api/v1/arm/vqshlu.json"},{"mnemonic":"vqshr","slug":"vqshr","records":1,"summary":"Shifts right with saturation (Unsigned).","page":"https://instructionsets.com/arm/vqshr/","api":"https://instructionsets.com/api/v1/arm/vqshr.json"},{"mnemonic":"vqshrn","slug":"vqshrn","records":1,"summary":"Shifts right, saturates, and narrows.","page":"https://instructionsets.com/arm/vqshrn/","api":"https://instructionsets.com/api/v1/arm/vqshrn.json"},{"mnemonic":"vqsub","slug":"vqsub","records":1,"summary":"Subtracts elements with saturation.","page":"https://instructionsets.com/arm/vqsub/","api":"https://instructionsets.com/api/v1/arm/vqsub.json"},{"mnemonic":"vraddhn","slug":"vraddhn","records":1,"summary":"Adds wide elements, rounds, and returns high narrow half.","page":"https://instructionsets.com/arm/vraddhn/","api":"https://instructionsets.com/api/v1/arm/vraddhn.json"},{"mnemonic":"vrecpe","slug":"vrecpe","records":1,"summary":"Estimates reciprocal (1/x).","page":"https://instructionsets.com/arm/vrecpe/","api":"https://instructionsets.com/api/v1/arm/vrecpe.json"},{"mnemonic":"vrecps","slug":"vrecps","records":1,"summary":"Newton-Raphson step for reciprocal refinement: (2 - Vn * Vm).","page":"https://instructionsets.com/arm/vrecps/","api":"https://instructionsets.com/api/v1/arm/vrecps.json"},{"mnemonic":"vrev16","slug":"vrev16","records":1,"summary":"Reverses bytes within 16-bit halfwords.","page":"https://instructionsets.com/arm/vrev16/","api":"https://instructionsets.com/api/v1/arm/vrev16.json"},{"mnemonic":"vrev32","slug":"vrev32","records":1,"summary":"Reverses elements within 32-bit words.","page":"https://instructionsets.com/arm/vrev32/","api":"https://instructionsets.com/api/v1/arm/vrev32.json"},{"mnemonic":"vrev64","slug":"vrev64","records":1,"summary":"Reverses elements within 64-bit doublewords.","page":"https://instructionsets.com/arm/vrev64/","api":"https://instructionsets.com/api/v1/arm/vrev64.json"},{"mnemonic":"vrinta","slug":"vrinta","records":1,"summary":"Rounds float to integral float (Nearest).","page":"https://instructionsets.com/arm/vrinta/","api":"https://instructionsets.com/api/v1/arm/vrinta.json"},{"mnemonic":"vrintm","slug":"vrintm","records":2,"summary":"Rounds float towards Minus Infinity (Floor).","page":"https://instructionsets.com/arm/vrintm/","api":"https://instructionsets.com/api/v1/arm/vrintm.json"},{"mnemonic":"vrintn","slug":"vrintn","records":1,"summary":"Rounds float to integral float (Nearest Even).","page":"https://instructionsets.com/arm/vrintn/","api":"https://instructionsets.com/api/v1/arm/vrintn.json"},{"mnemonic":"vrintp","slug":"vrintp","records":2,"summary":"Rounds float towards Plus Infinity (Ceil).","page":"https://instructionsets.com/arm/vrintp/","api":"https://instructionsets.com/api/v1/arm/vrintp.json"},{"mnemonic":"vrintr","slug":"vrintr","records":1,"summary":"Rounds float to integral float using FPSCR rounding mode.","page":"https://instructionsets.com/arm/vrintr/","api":"https://instructionsets.com/api/v1/arm/vrintr.json"},{"mnemonic":"vrintx","slug":"vrintx","records":1,"summary":"Rounds float to integral float, raising Inexact exception.","page":"https://instructionsets.com/arm/vrintx/","api":"https://instructionsets.com/api/v1/arm/vrintx.json"},{"mnemonic":"vrintz","slug":"vrintz","records":1,"summary":"Rounds float to integral float (Towards Zero).","page":"https://instructionsets.com/arm/vrintz/","api":"https://instructionsets.com/api/v1/arm/vrintz.json"},{"mnemonic":"vrshl","slug":"vrshl","records":1,"summary":"Shifts left with rounding based on a register value.","page":"https://instructionsets.com/arm/vrshl/","api":"https://instructionsets.com/api/v1/arm/vrshl.json"},{"mnemonic":"vrshr","slug":"vrshr","records":1,"summary":"Shifts right with rounding based on immediate.","page":"https://instructionsets.com/arm/vrshr/","api":"https://instructionsets.com/api/v1/arm/vrshr.json"},{"mnemonic":"vrshrn","slug":"vrshrn","records":1,"summary":"Shifts right, rounds, and narrows (2N -> N bits).","page":"https://instructionsets.com/arm/vrshrn/","api":"https://instructionsets.com/api/v1/arm/vrshrn.json"},{"mnemonic":"vrsqrte","slug":"vrsqrte","records":1,"summary":"Estimates reciprocal square root (1/sqrt(x)).","page":"https://instructionsets.com/arm/vrsqrte/","api":"https://instructionsets.com/api/v1/arm/vrsqrte.json"},{"mnemonic":"vrsqrts","slug":"vrsqrts","records":1,"summary":"Newton-Raphson step for reciprocal sqrt refinement: (3 - Vn * Vm) / 2.","page":"https://instructionsets.com/arm/vrsqrts/","api":"https://instructionsets.com/api/v1/arm/vrsqrts.json"},{"mnemonic":"vrsra","slug":"vrsra","records":1,"summary":"Shifts right with rounding and adds to accumulator.","page":"https://instructionsets.com/arm/vrsra/","api":"https://instructionsets.com/api/v1/arm/vrsra.json"},{"mnemonic":"vrsubhn","slug":"vrsubhn","records":1,"summary":"Subtracts wide elements, rounds, and returns high narrow half.","page":"https://instructionsets.com/arm/vrsubhn/","api":"https://instructionsets.com/api/v1/arm/vrsubhn.json"},{"mnemonic":"vsel","slug":"vsel","records":2,"summary":"Selects elements from Dn or Dm based on condition flags (predicated VFP).","page":"https://instructionsets.com/arm/vsel/","api":"https://instructionsets.com/api/v1/arm/vsel.json"},{"mnemonic":"vshl","slug":"vshl","records":1,"summary":"Shifts elements left.","page":"https://instructionsets.com/arm/vshl/","api":"https://instructionsets.com/api/v1/arm/vshl.json"},{"mnemonic":"vshr","slug":"vshr","records":1,"summary":"Shifts elements right.","page":"https://instructionsets.com/arm/vshr/","api":"https://instructionsets.com/api/v1/arm/vshr.json"},{"mnemonic":"vshrn","slug":"vshrn","records":1,"summary":"Shifts right and narrows result.","page":"https://instructionsets.com/arm/vshrn/","api":"https://instructionsets.com/api/v1/arm/vshrn.json"},{"mnemonic":"vsli","slug":"vsli","records":1,"summary":"Shifts bits left and inserts into destination (merging).","page":"https://instructionsets.com/arm/vsli/","api":"https://instructionsets.com/api/v1/arm/vsli.json"},{"mnemonic":"vsmmla","slug":"vsmmla","records":1,"summary":"Matrix multiply-accumulate (Signed Int8).","page":"https://instructionsets.com/arm/vsmmla/","api":"https://instructionsets.com/api/v1/arm/vsmmla.json"},{"mnemonic":"vsqrt","slug":"vsqrt","records":2,"summary":"Square root of double-precision register.","page":"https://instructionsets.com/arm/vsqrt/","api":"https://instructionsets.com/api/v1/arm/vsqrt.json"},{"mnemonic":"vsra","slug":"vsra","records":1,"summary":"Shifts elements right and adds to the destination accumulator.","page":"https://instructionsets.com/arm/vsra/","api":"https://instructionsets.com/api/v1/arm/vsra.json"},{"mnemonic":"vsri","slug":"vsri","records":1,"summary":"Shifts bits right and inserts into destination.","page":"https://instructionsets.com/arm/vsri/","api":"https://instructionsets.com/api/v1/arm/vsri.json"},{"mnemonic":"vst1","slug":"vst1","records":1,"summary":"Stores vector data to memory.","page":"https://instructionsets.com/arm/vst1/","api":"https://instructionsets.com/api/v1/arm/vst1.json"},{"mnemonic":"vst3","slug":"vst3","records":1,"summary":"Interleaves and stores three registers into memory (e.g., RGB).","page":"https://instructionsets.com/arm/vst3/","api":"https://instructionsets.com/api/v1/arm/vst3.json"},{"mnemonic":"vst4","slug":"vst4","records":1,"summary":"Interleaves and stores four registers into memory (e.g., RGBA).","page":"https://instructionsets.com/arm/vst4/","api":"https://instructionsets.com/api/v1/arm/vst4.json"},{"mnemonic":"vstm","slug":"vstm","records":1,"summary":"Stores multiple VFP registers to memory.","page":"https://instructionsets.com/arm/vstm/","api":"https://instructionsets.com/api/v1/arm/vstm.json"},{"mnemonic":"vstr","slug":"vstr","records":1,"summary":"Stores a floating-point register to memory.","page":"https://instructionsets.com/arm/vstr/","api":"https://instructionsets.com/api/v1/arm/vstr.json"},{"mnemonic":"vsub","slug":"vsub","records":2,"summary":"Subtracts two floating-point values.","page":"https://instructionsets.com/arm/vsub/","api":"https://instructionsets.com/api/v1/arm/vsub.json"},{"mnemonic":"vsubhn","slug":"vsubhn","records":1,"summary":"Subtracts wide elements and returns high narrow half.","page":"https://instructionsets.com/arm/vsubhn/","api":"https://instructionsets.com/api/v1/arm/vsubhn.json"},{"mnemonic":"vswp","slug":"vswp","records":1,"summary":"Swaps the contents of two vectors.","page":"https://instructionsets.com/arm/vswp/","api":"https://instructionsets.com/api/v1/arm/vswp.json"},{"mnemonic":"vtbl","slug":"vtbl","records":1,"summary":"Look up elements in a vector table.","page":"https://instructionsets.com/arm/vtbl/","api":"https://instructionsets.com/api/v1/arm/vtbl.json"},{"mnemonic":"vtbx","slug":"vtbx","records":1,"summary":"Inserts elements into a vector using a table lookup.","page":"https://instructionsets.com/arm/vtbx/","api":"https://instructionsets.com/api/v1/arm/vtbx.json"},{"mnemonic":"vtrn","slug":"vtrn","records":1,"summary":"Transposes elements of two vectors.","page":"https://instructionsets.com/arm/vtrn/","api":"https://instructionsets.com/api/v1/arm/vtrn.json"},{"mnemonic":"vtst","slug":"vtst","records":1,"summary":"Tests if any bits match (Vd = (Vn & Vm) != 0).","page":"https://instructionsets.com/arm/vtst/","api":"https://instructionsets.com/api/v1/arm/vtst.json"},{"mnemonic":"vummla","slug":"vummla","records":1,"summary":"Matrix multiply-accumulate (Unsigned Int8).","page":"https://instructionsets.com/arm/vummla/","api":"https://instructionsets.com/api/v1/arm/vummla.json"},{"mnemonic":"vusdot","slug":"vusdot","records":1,"summary":"Dot product of unsigned (src1) and signed (src2) bytes.","page":"https://instructionsets.com/arm/vusdot/","api":"https://instructionsets.com/api/v1/arm/vusdot.json"},{"mnemonic":"vusmmla","slug":"vusmmla","records":1,"summary":"Matrix multiply-accumulate (Unsigned x Signed Int8).","page":"https://instructionsets.com/arm/vusmmla/","api":"https://instructionsets.com/api/v1/arm/vusmmla.json"},{"mnemonic":"vuzp","slug":"vuzp","records":1,"summary":"De-interleaves vectors.","page":"https://instructionsets.com/arm/vuzp/","api":"https://instructionsets.com/api/v1/arm/vuzp.json"},{"mnemonic":"vzip","slug":"vzip","records":1,"summary":"Interleaves vectors.","page":"https://instructionsets.com/arm/vzip/","api":"https://instructionsets.com/api/v1/arm/vzip.json"},{"mnemonic":"wfe","slug":"wfe","records":3,"summary":"Puts the processor into a low-power state until an event occurs.","page":"https://instructionsets.com/arm/wfe/","api":"https://instructionsets.com/api/v1/arm/wfe.json"},{"mnemonic":"wfet","slug":"wfet","records":1,"summary":"Waits for an event or a timeout (using a counter).","page":"https://instructionsets.com/arm/wfet/","api":"https://instructionsets.com/api/v1/arm/wfet.json"},{"mnemonic":"wfi","slug":"wfi","records":3,"summary":"Puts the processor into a low-power state until an interrupt occurs.","page":"https://instructionsets.com/arm/wfi/","api":"https://instructionsets.com/api/v1/arm/wfi.json"},{"mnemonic":"wfit","slug":"wfit","records":1,"summary":"Waits for an interrupt or a timeout.","page":"https://instructionsets.com/arm/wfit/","api":"https://instructionsets.com/api/v1/arm/wfit.json"},{"mnemonic":"whilehi","slug":"whilehi","records":1,"summary":"Generates predicate for unsigned loop (while Xn > Xm).","page":"https://instructionsets.com/arm/whilehi/","api":"https://instructionsets.com/api/v1/arm/whilehi.json"},{"mnemonic":"whilehs","slug":"whilehs","records":1,"summary":"Generates predicate for unsigned loop (while Xn >= Xm).","page":"https://instructionsets.com/arm/whilehs/","api":"https://instructionsets.com/api/v1/arm/whilehs.json"},{"mnemonic":"whilele","slug":"whilele","records":1,"summary":"Generates a predicate based on loop counter (while Xn <= Xm).","page":"https://instructionsets.com/arm/whilele/","api":"https://instructionsets.com/api/v1/arm/whilele.json"},{"mnemonic":"whilelo","slug":"whilelo","records":1,"summary":"Generates predicate for unsigned loop (while Xn < Xm).","page":"https://instructionsets.com/arm/whilelo/","api":"https://instructionsets.com/api/v1/arm/whilelo.json"},{"mnemonic":"whilels","slug":"whilels","records":1,"summary":"Generates predicate for unsigned loop (while Xn <= Xm).","page":"https://instructionsets.com/arm/whilels/","api":"https://instructionsets.com/api/v1/arm/whilels.json"},{"mnemonic":"whilelt","slug":"whilelt","records":1,"summary":"Generates a predicate based on a loop counter (while Xn < Xm).","page":"https://instructionsets.com/arm/whilelt/","api":"https://instructionsets.com/api/v1/arm/whilelt.json"},{"mnemonic":"xpacd","slug":"xpacd","records":1,"summary":"Removes the PAC signature from a data pointer.","page":"https://instructionsets.com/arm/xpacd/","api":"https://instructionsets.com/api/v1/arm/xpacd.json"},{"mnemonic":"xpaci","slug":"xpaci","records":1,"summary":"Removes the PAC signature from an instruction pointer.","page":"https://instructionsets.com/arm/xpaci/","api":"https://instructionsets.com/api/v1/arm/xpaci.json"},{"mnemonic":"xpaclri","slug":"xpaclri","records":1,"summary":"Removes the pointer authentication code from an instruction address.","page":"https://instructionsets.com/arm/xpaclri/","api":"https://instructionsets.com/api/v1/arm/xpaclri.json"},{"mnemonic":"xtn","slug":"xtn","records":1,"summary":"Reads elements, narrows them, and writes to lower half of destination.","page":"https://instructionsets.com/arm/xtn/","api":"https://instructionsets.com/api/v1/arm/xtn.json"},{"mnemonic":"yield","slug":"yield","records":3,"summary":"Hints that the current thread is performing a spin-wait loop.","page":"https://instructionsets.com/arm/yield/","api":"https://instructionsets.com/api/v1/arm/yield.json"},{"mnemonic":"zip1","slug":"zip1","records":2,"summary":"Interleaves the lower halves of two vectors.","page":"https://instructionsets.com/arm/zip1/","api":"https://instructionsets.com/api/v1/arm/zip1.json"},{"mnemonic":"zip2","slug":"zip2","records":2,"summary":"Interleaves the upper halves of two vectors.","page":"https://instructionsets.com/arm/zip2/","api":"https://instructionsets.com/api/v1/arm/zip2.json"}]}